JPH08330995A - Satellite broadcasting reception equipment - Google Patents
Satellite broadcasting reception equipmentInfo
- Publication number
- JPH08330995A JPH08330995A JP7136466A JP13646695A JPH08330995A JP H08330995 A JPH08330995 A JP H08330995A JP 7136466 A JP7136466 A JP 7136466A JP 13646695 A JP13646695 A JP 13646695A JP H08330995 A JPH08330995 A JP H08330995A
- Authority
- JP
- Japan
- Prior art keywords
- satellite broadcast
- broadcast receiving
- switch circuit
- bit stream
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、衛星放送受信用チュー
ナのビットストリーム出力端子に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit stream output terminal of a satellite broadcast receiving tuner.
【０００２】[0002]
【従来の技術】従来、この分野の技術としては、例えば
衛星放送のデータ放送を受信する場合、衛星放送受信チ
ューナの電源を入れ、衛星放送チャンネルを選局し、そ
の状態を維持するための操作を必要としていた。2. Description of the Related Art Conventionally, as a technique in this field, when receiving a data broadcast of a satellite broadcast, for example, an operation for turning on the satellite broadcast receiving tuner, selecting a satellite broadcast channel, and maintaining the state. Was needed.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
ような操作を必要とする構成ではデータ放送を受信する
ための手段が繁雑になる傾向があり、誤操作の可能性も
有していた。However, in the configuration requiring the above-mentioned operation, the means for receiving the data broadcast tends to be complicated, and there is a possibility of an erroneous operation.
【０００４】[0004]
【課題を解決するための手段】本発明は、上記問題点を
解決するために、ビットストリーム端子に出力ピンが挿
入されていることを検出し、それを元に衛星放送受信用
チューナが受信状態となる構成としている。In order to solve the above-mentioned problems, the present invention detects that an output pin is inserted in a bit stream terminal, and based on this, the satellite broadcast receiving tuner receives the signal. The configuration is as follows.
【０００５】[0005]
【作用】上記構成によれば、ビットストリーム出力端子
に出力ピンが挿入されている場合は、マイクロコンピュ
ータにより電源投入及び選局を行い、繁雑な操作なしに
ビットストリーム出力端子より、ビットストリーム信号
が出力される。According to the above construction, when the output pin is inserted in the bitstream output terminal, the microcomputer turns on the power and tunes in, and the bitstream signal is output from the bitstream output terminal without complicated operations. Is output.
【０００６】[0006]
【実施例】以下、本発明の実施例について図面を参照し
ながら説明する。図１は本発明の第１の実施例を示す衛
星放送受信装置の概略構成図、図２は第２の実施例を示
す衛星放送受信装置の概略構成図、図３は本発明の第３
の実施例を示す衛星放送受信装置の概略構成図、図４は
第４の実施例を示す衛星放送受信装置の概略ブロック構
成図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a satellite broadcast receiving apparatus showing a first embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a satellite broadcast receiving apparatus showing a second embodiment, and FIG. 3 is a third embodiment of the present invention.
FIG. 4 is a schematic block diagram of the satellite broadcast receiving apparatus showing the embodiment of FIG. 4, and FIG. 4 is a schematic block configuration diagram of the satellite broadcast receiving apparatus showing the fourth embodiment.
【０００７】図１、図２、図３、図４において符号１は
マイクロコンピュータ、２は入力検出回路、３は衛星放
送受信用チューナ、４はビットストリーム出力端子、５
は電源スイッチ回路、６は制御信号スイッチ回路、７は
特定チャンネル受信用データ記憶用メモリーである。1, FIG. 2, FIG. 3, and FIG. 4, reference numeral 1 is a microcomputer, 2 is an input detection circuit, 3 is a satellite broadcast receiving tuner, 4 is a bit stream output terminal, 5
Is a power switch circuit, 6 is a control signal switch circuit, and 7 is a memory for storing data for receiving a specific channel.
【０００８】（実施例１）図１において衛星放送を受信
していない状態において、電源スイッチ回路５は、ＯＦ
Ｆの状態であり、この状態においてビットストリーム出
力端子４に出力ピンにが挿入されると入力検出回路２が
出力ピン挿入を検出し、マイクロコンピュータ１がその
状態を認識すると、電源スイッチ回路５がＯＮし、衛星
放送受信用チューナ３が受信状態になり、ビットストリ
ーム出力端子よりビットストリーム信号が出力される。(Embodiment 1) In FIG. 1, when the satellite broadcast is not received, the power switch circuit 5 is turned off.
In the F state, when the output pin is inserted into the bit stream output terminal 4 in this state, the input detection circuit 2 detects the output pin insertion, and when the microcomputer 1 recognizes the state, the power switch circuit 5 When turned on, the satellite broadcast receiving tuner 3 enters the receiving state, and a bit stream signal is output from the bit stream output terminal.
【０００９】（実施例２）図２において衛星放送を受信
していない状態において、電源スイッチ回路５と、制御
信号スイッチ回路６は、ＯＦＦの状態であり、この状態
においてビットストリーム出力端子４に出力ピンにが挿
入されると入力検出回路２が出力ピン挿入を検出し、マ
イクロコンピュータ１がその状態を認識すると、電源ス
イッチ回路５と、制御信号スイッチ回路６がＯＮし、衛
星放送受信用チューナ３が受信状態になり、ビットスト
リーム出力端子よりビットストリーム信号が出力され
る。(Embodiment 2) In FIG. 2, the power switch circuit 5 and the control signal switch circuit 6 are in an OFF state when satellite broadcasting is not being received, and in this state, output to the bit stream output terminal 4. When the pin is inserted, the input detection circuit 2 detects the insertion of the output pin, and when the microcomputer 1 recognizes that state, the power switch circuit 5 and the control signal switch circuit 6 are turned on, and the satellite broadcast receiving tuner 3 is turned on. Becomes a receiving state, and a bitstream signal is output from the bitstream output terminal.
【００１０】（実施例３）図３において衛星放送を受信
していない状態において、電源スイッチ回路５は、ＯＦ
Ｆの状態であり、この状態においてビットストリーム出
力端子４に出力ピンにが挿入されると入力検出回路２が
出力ピン挿入を検出し、マイクロコンピュータ１がその
状態を認識すると、電源スイッチ回路５がＯＮし、衛星
放送受信用チューナ３がメモリー７に記憶されている特
定チャンネルの受信状態になり、ビットストリーム出力
端子よりビットストリーム信号が出力される。(Embodiment 3) In FIG. 3, when the satellite broadcast is not received, the power switch circuit 5 is turned off.
In the F state, when the output pin is inserted into the bitstream output terminal 4 in this state, the input detection circuit 2 detects the output pin insertion, and when the microcomputer 1 recognizes the state, the power switch circuit 5 When turned on, the satellite broadcast receiving tuner 3 enters the receiving state of the specific channel stored in the memory 7, and the bit stream signal is output from the bit stream output terminal.
【００１１】（実施例４）図４において衛星放送を受信
していない状態において、電源スイッチ回路５と、制御
信号スイッチ回路６は、ＯＦＦの状態であり、この状態
においてビットストリーム出力端子４に出力ピンにが挿
入されると入力検出回路２が出力ピン挿入を検出し、マ
イクロコンピュータ１がその状態を認識すると、電源ス
イッチ回路５と、制御信号スイッチ回路６がＯＮし、衛
星放送受信用チューナ３がメモリー７に記憶されている
特定チャンネルの受信状態になり、ビットストリーム出
力端子よりビットストリーム信号が出力される。(Embodiment 4) In FIG. 4, the power switch circuit 5 and the control signal switch circuit 6 are in an OFF state when satellite broadcasting is not being received, and in this state, the signal is output to the bit stream output terminal 4. When the pin is inserted, the input detection circuit 2 detects the insertion of the output pin, and when the microcomputer 1 recognizes that state, the power switch circuit 5 and the control signal switch circuit 6 are turned on, and the satellite broadcast receiving tuner 3 is turned on. Becomes the reception state of the specific channel stored in the memory 7, and the bit stream signal is output from the bit stream output terminal.
【００１２】[0012]
【発明の効果】以上のように本発明の衛星放送受信装置
によれば、データ放送受信時に衛星放送の特定チャンネ
ルの受信状態を維持するための繁雑な操作を必要とする
事なく、ビットストリーム出力端子に出力ピンを挿入す
るだけで容易に上記操作が行なえる。As described above, according to the satellite broadcast receiving apparatus of the present invention, it is possible to output a bit stream without requiring a complicated operation for maintaining a receiving state of a specific channel of the satellite broadcast when receiving the data broadcast. The above operation can be easily performed by inserting the output pin into the terminal.
【００１３】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.
【図１】本発明の第１の実施例における衛星放送受信装
置のブロック構成図FIG. 1 is a block configuration diagram of a satellite broadcast receiving apparatus according to a first embodiment of the present invention.
【図２】本発明の第２の実施例における衛星放送受信装
置のブロック構成図FIG. 2 is a block configuration diagram of a satellite broadcast receiving device according to a second embodiment of the present invention.
【図３】本発明の第３の実施例における衛星放送受信装
置のブロック構成図FIG. 3 is a block configuration diagram of a satellite broadcast receiving device according to a third embodiment of the present invention.
【図４】本発明の第４の実施例における衛星放送受信装
置のブロック構成図FIG. 4 is a block configuration diagram of a satellite broadcast receiving device according to a fourth embodiment of the present invention.
１ マイクロコンピュータ ２ 入力検出回路 ３ 衛星放送受信チューナ ４ ビットストリーム出力端子 ５ 電源スイッチ回路 ６ 制御信号スイッチ回路 ７ 特定チャンネル記憶用メモリー 1 Microcomputer 2 Input detection circuit 3 Satellite broadcast receiving tuner 4 Bit stream output terminal 5 Power switch circuit 6 Control signal switch circuit 7 Memory for storing specific channel
Claims (4)
送受信用チューナのビットストリーム出力端子と、前記
ビットストリーム出力端子に入力ピンが挿入されたこと
を検出する入力検出手段と、前記入力検出手段の出力を
入力とする端子を有するマイクロコンピュータと、前記
マイクロコンピュータに制御され前記衛星放送受信用チ
ューナの電源を断続するスイッチ回路とを備え、前記入
力検出手段の出力に応じて、前記衛星放送受信用チュー
ナの電源を断続するスイッチ回路を制御する衛星放送受
信装置。1. A satellite broadcast receiving tuner, a bit stream output terminal of the satellite broadcast receiving tuner, an input detecting means for detecting that an input pin is inserted in the bit stream output terminal, and the input detecting means. And a switch circuit for connecting and disconnecting the power source of the satellite broadcast receiving tuner controlled by the microcomputer, the satellite broadcast receiving unit according to the output of the input detecting unit. Satellite receiver that controls the switch circuit that connects and disconnects the power of the tuner for use.
送受信用チューナのビットストリーム出力端子と、前記
ビットストリーム出力端子に入力ピンが挿入されたこと
を検出する入力検出手段と、前記入力検出手段の出力を
入力とする端子を有するマイクロコンピュータと、前記
マイクロコンピュータに制御され前記衛星放送受信用チ
ューナの電源を断続するスイッチ回路と、前記マイクロ
コンピュータに制御され前記衛星放送受信用チューナと
前記マイクロコンピュータとの制御線を断続するスイッ
チ回路とを備え、前記入力検出手段の出力に応じて、前
記衛星放送受信用チューナの電源を断続するスイッチ回
路及び前記衛星放送受信用チューナと前記マイクロコン
ピュータとの制御線を断続するスイッチ回路を制御する
衛星放送受信装置。2. A satellite broadcast receiving tuner, a bit stream output terminal of the satellite broadcast receiving tuner, an input detecting means for detecting that an input pin is inserted in the bit stream output terminal, and the input detecting means. , A switch circuit for connecting and disconnecting the power source of the satellite broadcast receiving tuner controlled by the microcomputer, and the satellite broadcast receiving tuner and the microcomputer controlled by the microcomputer. And a switch circuit for connecting and disconnecting a control line for controlling the satellite broadcast receiving tuner and the microcomputer according to the output of the input detection means. A satellite broadcast receiver that controls a switch circuit that connects and disconnects lines.
送受信用チューナのビットストリーム出力端子と、前記
ビットストリーム出力端子に入力ピンが挿入されたこと
を検出する入力検出手段と、前記入力検出手段の出力を
入力とする端子を有するマイクロコンピュータと、特定
チャンネル受信用の情報を記憶する手段と、前記マイク
ロコンピュータに制御され前記衛星放送受信用チューナ
の電源を断続するスイッチ回路とを備え、前記入力検出
手段の出力に応じて、前記衛星放送受信用チューナの電
源を断続するスイッチ回路を制御する衛星放送受信装
置。3. A satellite broadcast receiving tuner, a bit stream output terminal of the satellite broadcast receiving tuner, an input detecting means for detecting that an input pin is inserted in the bit stream output terminal, and the input detecting means. A microcomputer having a terminal for receiving the output of the input, means for storing information for receiving a specific channel, and a switch circuit controlled by the microcomputer for connecting and disconnecting the power supply of the satellite broadcast receiving tuner, A satellite broadcast receiving apparatus for controlling a switch circuit for connecting and disconnecting the power source of the satellite broadcast receiving tuner according to the output of the detecting means.
送受信用チューナのビットストリーム出力端子と、前記
ビットストリーム出力端子に入力ピンが挿入されたこと
を検出する入力検出手段と、前記入力検出手段の出力を
入力とする端子を有するマイクロコンピュータと、特定
チャンネル受信用の情報を記憶する手段と、前記マイク
ロコンピュータに制御され前記衛星放送受信用チューナ
の電源を断続するスイッチ回路と、前記マイクロコンピ
ュータに制御され前記衛星放送受信用チューナと前記マ
イクロコンピュータとの制御線を断続するスイッチ回路
とを備え、前記入力検出手段の出力に応じて、前記衛星
放送受信用チューナの電源を断続するスイッチ回路及び
前記衛星放送受信用チューナと前記マイクロコンピュー
タとの制御線を断続するスイッチ回路を制御する衛星放
送受信装置。4. A satellite broadcast receiving tuner, a bit stream output terminal of the satellite broadcast receiving tuner, an input detecting means for detecting that an input pin is inserted in the bit stream output terminal, and the input detecting means. , A means for storing information for receiving a specific channel, a switch circuit which is controlled by the microcomputer and connects and disconnects the power supply of the satellite broadcast receiving tuner, and the microcomputer. A switch circuit for connecting and disconnecting a control line between the satellite broadcast receiving tuner and the microcomputer which is controlled, and a switch circuit for connecting and disconnecting the power source of the satellite broadcast receiving tuner according to the output of the input detection means; and Intermittent control line between the satellite broadcasting tuner and the microcomputer A satellite broadcast receiving device that controls a switch circuit that operates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13646695A JP3387268B2 (en) | 1995-06-02 | 1995-06-02 | Satellite broadcast receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13646695A JP3387268B2 (en) | 1995-06-02 | 1995-06-02 | Satellite broadcast receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08330995A true JPH08330995A (en) | 1996-12-13 |
| JP3387268B2 JP3387268B2 (en) | 2003-03-17 |
Family
ID=15175777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13646695A Expired - Lifetime JP3387268B2 (en) | 1995-06-02 | 1995-06-02 | Satellite broadcast receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3387268B2 (en) |
-
1995
- 1995-06-02 JP JP13646695A patent/JP3387268B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP3387268B2 (en) | 2003-03-17 |
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