JPH08330944A - Semiconductor device - Google Patents

Abstract

PURPOSE: To facilitate a writing operation for a semiconductor device which attains a desired circuit operation by writing the prescribed data into the completed products such as so-called PLD, EPGA, etc. CONSTITUTION: An anti-fuse 31 is provided with a constant current circuit which can perform the free switching among a write mode where a write current is supplied to change the anti-fuse 31 into a write state from a cut-off state, a sense mode where a sense current is supplied to the anti-fuse 31 to sense its state and an additional write mode where an additional write current is supplied to the written anti-fuse 31 for the additional write. In a write mode, a current is supplied to the anti-fuse 31 via a Miller circuit consisting of the PMOS transistors 401 and 37. Then a large current is supplied to the anti-fuse 31 after the dielectric breakdown is detected by a comparator 42 and before a prescribed time elapses. The large current is switched to a small current after the prescribed time.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a so-called PLD,
The present invention relates to a semiconductor device called an FPGA or the like, which can realize a desired circuit operation by writing predetermined data in a completed product.

[0002]

2. Description of the Related Art In recent years, programmable semiconductor devices called PLD, FPGA, etc. have come into wide use. Such a programmable semiconductor device is particularly suitable for a small quantity and a wide variety of applications because a desired circuit wiring is completed and a desired circuit operation is realized by writing programming data after the product is completed.

There are various methods for realizing a circuit wiring according to write data in such a semiconductor device, and one of them is provided with a fuse in the middle of the circuit wiring and the fuse is provided. There is a method of realizing a desired circuit wiring depending on whether or not to blow. In recent years, a method using a so-called anti-fuse instead of the fuse has been receiving attention. When a voltage higher than the normal operating voltage is applied, an antifuse is one that was in an insulating state (hereinafter referred to as the "off state") until it becomes conductive (hereinafter referred to as "on state") due to dielectric breakdown. Element called "via state 1".
Since it can be built in a semiconductor integrated circuit with extremely small dimensions such as one, it is attracting attention as an element suitable for higher integration than a fuse.

One method of writing data to the antifuse is proposed in, for example, Japanese Patent Laid-Open No. 3-225864. This proposed writing method applies a predetermined voltage between a word line and a bit line provided in a PROM to change an antifuse formed on a diffusion layer of the PROM from an off state to an on state. It is a voltage writing method.

There is one proposal in EP-A-0626726 for the method of writing data to the antifuse. In this data writing method, for each wiring block provided with an antifuse, writing is performed by applying a constant voltage to the antifuse in the block, and then writing a sense current to the antifuse. Is checked, and if writing has been completed, additional writing is performed.

Further, PCT / US92 / 06206, USP52432426, USP53025
In Japanese Patent Laid-Open No. 46-46, a constant voltage writing method is also adopted, and a technique of precharging wiring elements connected to an antifuse to an intermediate potential before applying a writing voltage, and a method of applying a voltage after writing after writing A technique for reducing the on-resistance of an antifuse that has been turned on by applying a voltage in the direction opposite to the voltage direction is disclosed.
-506098, PCT / US92 / 01994
Japanese Patent Publication No. US Pat. No. 5,313,119 also discloses a technique in which a constant voltage writing method is adopted and a high write voltage is applied only to an antifuse to be written and an intermediate potential is applied to other antifuses.

Regarding the constant voltage writing method, in addition to the above, the document "IEEE 1994 CUSTOM IN
TEGRATED CIRCUITS CONFERE
NCE 9.3 Programming Antif
use in Crosspoint's FPGA "
Among the FPGA manufacturers (Actel, Quickl
The constant voltage writing method based on the "Original Cross Point" has been introduced.

One of the problems of the constant voltage writing method is that a constant voltage is applied to the antifuse to change the antifuse from the off state to the on state. When the antifuse that was in the off state transitions to the on state due to dielectric breakdown or the like, the resistance value decreases, so that an excessive current flows for a relatively long time (for example, 1 to 10 msec), and thus the resistance value of the antifuse due to excessive heat generation. May vary greatly, and further, there may be a case where fusing occurs and the state is turned off again. For example, according to the experiments by the present inventors,
In the case of the constant voltage writing method in which the current is clamped within the range of 1 to 20 mA, the resistance value of the antifuse is 40Ω.
PROM for high-speed drive because it varies in the range of up to 1 KΩ and delay time and timing skew increase.
It is difficult to apply to semiconductor devices such as PLDs and PLDs.

[0009]

In order to prevent the variation in ON resistance and the occurrence of fusing, it is conceivable to perform writing to the antifuse with a constant current. There is no example of adopting the constant current writing method for the antifuse, but there is an example of writing to the fuse at a constant current for a programmable read only memory (PROM) using the fuse as a storage element (see “NE
C Data Book IC Memory "1989/1990
Edited by Semiconductor Application Technology Headquarters, NEC Corporation. Published by Semiconductor Marketing Headquarters, NEC Corporation).

However, the constant current writing method proposed here creates a comparison voltage from a constant voltage source, while converting the current flowing into the fuse into a voltage, and comparing the voltage with the above comparison voltage. It is necessary to externally add a complicated control circuit that controls the current and clamps the inflow current so that it does not exceed a certain value. Only one bit can be written at a time, and it takes a long time to write. Since it is a writing method, there is a dedicated P
I need a ROM writer. If the conventional method of writing to the fuse of the PROM is applied to the writing of the anti-fuse of the semiconductor device such as the PLD as it is, a complicated control circuit is externally attached and the semiconductor device side is also written. In addition to the constant voltage power supply terminals for use, a constant current power supply terminal is required, and this constant current power supply terminal is required in the same number as the number of parallel writes.

Further, even if the method of writing to the antifuse with a constant current is adopted, for example, with a simple method of performing writing with a constant current pulse of a constant time width,
After all, a large variation in ON resistance cannot be avoided. In view of the above circumstances, the present invention is a programmable semiconductor device including an antifuse, and a semiconductor device capable of writing in the antifuse so that the on-resistance of the antifuse has a stable low resistance value. The purpose is to provide.

[0012]

A first semiconductor device of the present invention which achieves the above object, comprises a first signal line and a second signal line which intersect with each other, and these first signal line and second signal line.
An antifuse arranged at an intersection with the signal line of the above, and a write for supplying power to the antifuse in a cutoff state to make the antifuse transit to a fixed conductive state, regarding the antifuse arranged at the intersection In a semiconductor device in which different circuit operations are realized depending on whether or not to perform, a constant current for applying a voltage equal to or lower than a predetermined voltage to the antifuse, which changes depending on the resistance value of the antifuse to supply a constant current to the antifuse. A circuit and a detection circuit for detecting whether or not a current starts flowing through the antifuse, and the constant current circuit has passed a predetermined time after the detection circuit detects that a current starts flowing through the antifuse. Previously, the antifuse was supplied with a predetermined first constant current, and after a lapse of a predetermined time, the supply of current to the antifuse was stopped. Characterized in that it is intended to.

Further, a second semiconductor device of the present invention which achieves the above object, comprises a first signal line and a second signal line intersecting each other, and a first signal line and a second signal line. Whether or not the antifuse arranged at the intersection is provided with the antifuse arranged at the intersection, and power is supplied to the antifuse in the cutoff state to make the antifuse transit to a fixed conductive state. In semiconductor devices that realize different circuit operations according to
A constant current circuit that applies a voltage equal to or lower than a predetermined voltage to the antifuse, which changes according to the resistance value of the antifuse so as to supply a constant current to the antifuse, and a detection that detects whether or not a current has started to flow through the antifuse A constant current circuit, the constant current circuit supplies a predetermined first constant current to the antifuse before a predetermined time has elapsed after it has been detected by the detection circuit that a current has started flowing through the antifuse, and It is characterized in that when a predetermined time elapses, the second constant current smaller than the first constant current is switched to supply the second constant current to the antifuse.

Here, in the first semiconductor device or the second semiconductor device, the detection circuit is a comparator for comparing a voltage at one end of the antifuse or a voltage corresponding to the voltage with a predetermined reference voltage. It is preferable. When a voltage higher than the normal operating voltage is applied to the antifuse, the current density is reduced because the cross-sectional area of the filament immediately after the breakdown of the antifuse (the current flow path formed by the breakdown) is still small. It is large (for example, about 10 ⁹ A / cm ² ), and many metal atoms (for example, Al) of the electrode of the antifuse can be extruded into the filament, and the effect is that the power density of the current density (2
It is expected to be proportional to the third power (this is referred to as electromigration “Electro Migration”).
n ", and the current is called the EM current). The heat generated by the EM current melts the metal of the electrodes on both ends of the antifuse to form an alloy. However, if this EM current is kept flowing for a long time, stress may remain in the filament due to excessive heat generation, and the resistance value of the antifuse may vary greatly, and further, the fuse may be blown and the OFF state may occur again.

Therefore, after a lapse of a predetermined time, a constant current smaller than the EM current (MT (Melted) for the EM current)
(Referred to as electric current) or by shutting off without passing the MT electric current, a stable melting of the metal of the electrode takes place and an alloy is formed. On the other hand, even if a certain voltage is applied to the antifuse, the time from the start of the application of the voltage to the occurrence of dielectric breakdown varies greatly depending on the antifuse.

The above-mentioned first semiconductor device and second semiconductor device of the present invention are made based on the above viewpoint, and after the detection circuit detects that the current starts flowing through the antifuse. , Before the lapse of a predetermined time, a first constant current is applied to the antifuse by a constant current circuit,
When the predetermined time has elapsed, the supply of the first constant current is stopped (in the case of the first semiconductor device), or the second constant current lower than the first constant current is switched to the antifuse (the second constant current). In the case of semiconductor devices). Therefore, the first constant current causes a large amount of metal atoms of the electrode of the antifuse to be pushed out to the filament to obtain a small resistance value, and when a predetermined time has elapsed, the current supply is stopped or the first
Is switched to a second constant current lower than the constant current, and excessive heat generation is prevented, and the metal of the electrode is stably melted to form an alloy. Therefore, a small resistance value is obtained, variation in resistance value is reduced, and fusing is prevented.

Further, if a comparator which compares the voltage at one end of the antifuse with a predetermined reference voltage is used as the detection circuit, the circuit is simplified. Further, according to the first semiconductor device or the second semiconductor device of the present invention, since the constant current circuit has a simple circuit configuration, it can be built in the chip, and in that case, an external circuit and a write control circuit can be provided. The burden is reduced. In addition, when the chip is built in, the number of external terminals dedicated to writing is small, so the remaining terminals can be effectively utilized. Further, it is also possible to write to a plurality of antifuses at the same time, in which case the write time is shortened.

Further, a third semiconductor device of the present invention which achieves the above object, comprises a first signal line and a second signal line intersecting each other, and a first signal line and a second signal line. Whether or not the antifuse arranged at the intersection is programmed to supply power to the antifuse in the cut-off state and transition the antifuse to a fixed conductive state. In a semiconductor device in which different circuit operations are realized according to the above, a write mode for supplying a write current for changing the antifuse from a cut-off state to a conductive state to the antifuse, To the sense mode in which a sense current for sensing the state of the antifuse is supplied and the antifuse in which writing has been performed,
It is characterized in that it is provided with a constant current circuit which can be switched to an additional write mode for supplying an additional write current for performing additional writing.

A third semiconductor device of the present invention has a built-in constant current circuit, and the constant current circuit is in a write mode.
Since it can be switched between the sense mode and the additional write mode, only a constant voltage for writing is supplied from the outside, and after that, simply by inputting the address and data,
Constant current writing is performed, so when viewed from the outside,
Very easy writing is performed.

Further, in the third semiconductor device of the present invention, since writing is performed with a constant current, and the additional writing mode is performed and additional writing is also performed with a constant current, a small resistance value can be obtained and the resistance value Variation is reduced and fusing is also prevented. Here, in the above-mentioned third semiconductor device of the present invention, the constant current circuit, in the sense mode,
It is preferable to include a voltage clamp circuit that limits the voltage applied to the antifuse in the cutoff state to a voltage at a level at which the antifuse remains in the cutoff state.

The provision of the voltage clamp circuit prevents the antifuse that should not be turned on in the sense mode from being inadvertently turned on. Furthermore, it is preferable that the third semiconductor device of the present invention further includes a state detection circuit that detects the state of the antifuse based on the voltage generated when the sense current is supplied to the antifuse.

If this state detection circuit is provided, the on / off state of the antifuse is detected in the sense mode, and it is determined whether to write again or move to additional writing. Furthermore, the third aspect of the present invention described above.
And a second semiconductor device in which the first signal line includes a plurality of first signal lines extending in parallel with each other,
Is a semiconductor device having a plurality of second signal lines extending in parallel with each other, and the antifuse is arranged at each intersection of the plurality of first signal lines and the plurality of second signal lines. And a first switch circuit serially connected to each of the plurality of first signal lines, a second switch circuit serially connected to each of the plurality of second signal lines, and a first switch circuit A first decoder for switchably selecting a desired first signal line from among the plurality of first signal lines by controlling the second signal line and a plurality of second signal lines by controlling the second switch circuit. A second decoder for switchably selecting a desired second signal line of the lines, the constant current circuit being selected by the first decoder and the second decoder simultaneously for writing 1 One or more antifuses In parallel, it is also a preferred embodiment supplies a constant current that is controlled independently of each other.

In the third semiconductor device of the present invention,
As described above, each antifuse is provided at each intersection of the plurality of first signal lines and the plurality of second signal lines, and the write address is selected by the first decoder and the second decoder. The antifuses at the selected addresses may be configured to supply constant currents controlled in parallel and independently of each other. In such a configuration, high speed writing is possible.

In the third semiconductor device of the present invention, the first decoder and the second decoder are all the first signal lines selected by the first decoder and the second decoder, respectively. It is preferable to have a mode in which all the second signal lines are selected at the same time. At the time of writing, when applying a voltage for flowing a current for writing, an antifuse that is not trying to write between the potential of the signal line to which the voltage is applied and this signal line is used. If the potentials of the sandwiched signal lines are different from each other, a voltage is momentarily applied to the antifuse, and the antifuse that is not trying to write the data may inadvertently transition to the ON state. Therefore, it is preferable to precharge all the first signal lines and the second signal lines to a potential of, for example, one half of the write voltage before writing.
At this time, if the first decoder and the second decoder have a mode in which all of the first signal lines and all of the second signal lines are simultaneously selected, the first signal lines are written prior to writing. And all of the second signal lines can be precharged at the same time, and the preparation for the write operation can be completed in a short time.

Further, in the third semiconductor device of the present invention, the constant current circuit currents a reference current generating circuit for generating a reference current and a constant current corresponding to the reference current generated by the reference current generating circuit. It is preferable to have a constant current supply circuit which is generated by a mirror circuit and is supplied to the antifuse. As described above, when the constant current circuit is configured by the reference current generation circuit and the constant current supply circuit that supplies the constant current by the current mirror circuit, it is possible to construct a current with a simple configuration by making only one reference current. The reference current can be easily copied by the mirror circuit for the number of parallel writes, and a plurality of antifuses can simultaneously be supplied with constant currents controlled independently of each other.

It is also possible to combine the third semiconductor device of the present invention with the first semiconductor device of the present invention. That is, according to the present invention having such a configuration, in the third semiconductor device described above, a detection circuit for detecting whether or not a current starts to flow in the antifuse in the write mode, and the constant current circuit In the mode, a predetermined first constant current is supplied as a write current to the antifuse before a predetermined time has elapsed after it has been detected by the detection circuit that a current has started flowing,
It is characterized in that the supply of the write current to the antifuse is stopped when the predetermined time has elapsed. As a result, the antifuse can be more stably transitioned to the low resistance ON state.

Further, in the third semiconductor device of the present invention,
It is also possible to combine the second semiconductor device of the invention. That is, according to the present invention having such a configuration, in the third semiconductor device described above, a detection circuit for detecting whether or not a current has started to flow through the antifuse in the write mode is provided, and the constant current circuit is provided in the write mode. In the above, before a predetermined time elapses after it is detected by the detection circuit that a current starts flowing through the antifuse, a predetermined first constant current is supplied to the antifuse as a write current and the predetermined constant current is supplied to the antifuse. When the time elapses, the writing current is switched to the second constant current smaller than the first constant current, and
Is supplied to the antifuse as a write current. Also in this case, the antifuse can be more stably transitioned to the low resistance ON state.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of an anti-fuse write circuit of a PLD incorporating a first embodiment of a semiconductor device of the present invention. In FIG. 1, a constant current circuit 100 for supplying a constant current to the antifuse 1 and a detection circuit 200 for detecting whether or not a current starts flowing through the antifuse 1.
And an anti-fuse write circuit composed of a block 300 in which a plurality of anti-fuses 1 are arranged and a circuit for selecting each of the plurality of anti-fuses 1 is arranged.

The antifuse 1 in the block 300 is
A plurality of first signal lines 2_1 and 2_ extending in the vertical direction of the figure
2, ..., 2_m and a plurality of second signal lines 3_1, 3_2, ..., 3_n extending in the horizontal direction in the drawing are arranged at respective intersections, and the first signal lines 2_1, 2_2 ,. Inputs and outputs of a plurality of circuits (not shown) are connected to the second signal lines 3_1, 3_2, ..., 3_n. These circuits are connected by different wirings depending on whether the antifuse 1 stays in the off state or transitions to the on state, and different circuits are provided as a whole depending on the difference in the write data to the antifuse 1. Will be realized.

In the block 300, one end of each NMOS transistor 4_1, 4_2, ..., 4_m is connected to each first signal line 2_1, 2_2, ..., 2_m. Those NMOS transistors 4_1, 4_2, ...
The other ends of 4_m are commonly connected, connected to the positive phase input of the comparator 201, and also connected to the write power supply V _PP (9V) via the PMOS transistor 106. In addition, each NMOS transistor 4_1, 4_2, ..., 4_
The gate of m is a voltage conversion type inverter 6_1, which will be described later.
NAND gates 7_1 and 7 via 6_2, ..., 6_m
, ..., 7_m are connected to the outputs.

Each NAND gate 7_1, 7_2, ..., 7_
Each one input of m is connected to each output of the column decoder 11. The column decoder 11 has a first signal line 2
A column address for selecting any of _1, 2_2, ..., 2_m and a signal BLOCK0_ for enabling the column decoder 11 are input. Also,
The other inputs of the NAND gates 7_1, 7_2, ..., 7_m are commonly connected and connected to the output of the NAND gate 9. One input of NAND gate 9 is NAND gate 1
It is connected to the 0 output. In addition, the other input of the NAND gate 9 has a read signal READ for checking whether each antifuse 1 is properly in the ON state or the OFF state after the writing to the antifuse 1 is completed.
_ Is entered. However, a circuit (sense amplifier or the like) for reading is not shown. A program pulse signal PGM for writing to the antifuse 1 is input to one end of the NAND gate 10. The other end of the NAND gate 10 is supplied with a write data signal D that determines whether or not to write data in the antifuse 1.

Each of the second signal lines 3_1, 3_2, ..., 3_
n is each NMOS transistor 5_1, 5_2, ...,
One end of each of the 5_n is connected, and the other ends of the NMOS transistors 5_1, 5_2, ..., 5_n are connected to the ground V.
Commonly connected to _SS . The gates of the NMOS transistors 5_1, 5_2, ..., 5_n are connected to the outputs of the row decoder 12 via the voltage conversion type inverters 8_1, 8_2 ,.

The row decoder 12 has a second signal line 3_
A row address for selecting any one of 1, 3_2, ..., 3_n and the above-mentioned block signal BLOCK0_ for enabling the row decoder 12 are input. PMOS transistor 101 of constant current circuit 100
Has one end connected to the writing power supply V _PP and the other end connected to the PM.
It is connected to the gate of the OS transistor 101, the gate of the PMOS transistor 106, and one ends of the resistors 102 and 103. The other end of the resistor 102 is connected to the output of the voltage conversion inverter 104 to which the signal MT & EM held at the'H 'level is input while the antifuse 1 is being written. On the other hand, the other end of the resistor 103 is connected to the ground V _SS via the NMOS transistor 105. Also, the NMOS transistor 10
The gate of 5 is connected to the output of NOR gate 107.

A comparison voltage (8V) for comparison with the voltage of the node CI corresponding to the voltage at one end of the antifuse 1 is input to the negative phase input of the comparator 201 of the detection circuit 200. The output of the comparator 201 is connected to one input of the NOR gate 203 via the delay circuit 202. To the other input of the NOR gate 203, the program pulse signal PGM_ which is the inverted program pulse signal PGM described above is input. See also NOR Gate 2
The output of 03 is connected to one input of NOR gate 107. The other input of the NOR gate 107 is supplied with the signal EM_ which is held at the'L 'level while writing to the antifuse 1.

FIG. 2 is a diagram showing each example of the voltage conversion type inverter. The input side is the operating voltage V of the circuit shown in FIG.
'H' level, 'L' at the level of _DD (eg 3.3V)
When the level changes, the output side changes to the “L” level and the “HH” level at the level of the write voltage V _PP (for example, 9V). Although two circuit examples are illustrated here, the voltage conversion type inverter is not limited to these circuit examples.

FIG. 3 is a timing chart of the anti-fuse write circuit shown in FIG. Although the read signal READ_ is not shown in this timing chart, the read signal READ_ is set to the “H” level when writing to the antifuse 1. First, the “H” level signal MT & EM is input to the voltage conversion type inverter 104 shown in FIG. 1, and the “L” level signal EM_ is input to the NOR gate 107. Further, while the “L” level is being output as the program pulse signal PGM, the “L” level is input to each input of the NAND gates 7_1, 7_2, ..., 7_m via the NAND gate 10 and the NAND gate 9. At this time, the antifuse 1 has not been designated. Also, the NOR gate 203
Since the "H" level is input as the program pulse signal PGM_ to the NOR gate 203, the NOR gate 203 outputs the "L" level signal EMINH. This'L 'level signal EMINH is input to the NOR gate 107, and since the'L' level signal EM_ is input to the NOR gate 107, the NOR gate 107 outputs an'H 'level signal. NMOS transistor 10
5 is turned on.

Then, a current (hereinafter referred to as MT current) flows in the voltage conversion type inverter 104 along the path of the write power supply V _PP → PMOS transistor 101 → resistance 102, and the write power supply V _PP → PMOS transistor 101 → resistance. 10
3 → Ground V in the path of NMOS transistor 105
Current flows in _SS . At this time, the PMOS transistor 1
The current flowing through 01 is called the EM current. At this time PMO
The S-transistor 106 also tries to pass a current, but since the antifuse 1 is not specified here and no current is flowing in the antifuse 1, the node CI of the constant current source shown in FIG. The potential is the power supply voltage V _PP (9
V). The potential (9V) of this node CI and the comparison voltage (8V) are compared by the comparator 201, and the signal of the “H” level is output from the comparator 201 and input to the NOR gate 203 via the delay circuit 202. However, since the "H" level is input to the NOR gate 203 as the program pulse signal PGM_, the NOR gate 203 also outputs the "L" level signal EMINH.

Next, the column address and the row address are input to the column decoder 11 and the row decoder 12, and the "L" level is input as the enable signal BLOCK0_. Further, when writing to the antifuse 1 designated by the column address and the row address, the write data D becomes "H" level. Even if the antifuse 1 is designated by the column address and the row address, if the antifuse 1 is not written, the write data D remains at the'L 'level. Here, the description will be continued on the assumption that writing is performed to the designated antifuse 1. Further, subsequently to this, the program signal PGM changes to the “H” level. Then, in the column decoder 11, since the enable signal BLOCK0_ is at the “L” level, one of the outputs corresponding to the input column address becomes the “H” level, and both the program signal PGM and the write data D are set to “L”. Since it is at the H'level, the output of the NAND gate 9 goes to the'H 'level via the NAND gate 10. As a result, the output of any one of the NAND gates 7_1, 7_2, ..., 7_m becomes the “L” level and the voltage conversion type inverters 6_1, 6_.
2, ..., 6_m via NMOS transistor 4_
Any one of 1, 4_2, ..., 4_m is turned on.

On the other hand, since the enable signal BLOCK0_ of the row decoder 12 is also at the "L" level, any output corresponding to the input row address becomes the "L" level and the voltage conversion type inverters 8_1, 8_2, ... , 8_
n through NMOS transistors 5_1, 5_2,
, 5_n is turned on. Thus, the antifuse 1 at the intersection of the first signal lines 2_1, 2_2, ..., 2_m and the second signal lines 3_1, 3_2, ..., 3_n is designated. However, as described above, when the antifuse 1 at the intersection is left in the off state,
The write data D is set to the “L” level.

Here, the PMOS transistors 101 and P
The MOS transistor 106 constitutes a current mirror circuit. That is, the PMOS transistor 10
1 and the gate of the PMOS transistor 106 are connected to each other, and when an EM current (45 mA) flows through the PMOS transistor 101, the PMOS transistor 106 causes the antifuse 1 to receive the EM current (45 mA).
mA), and the PMOS transistor 101
When the MT current (5 mA) flows to the anti-fuse 1, the MT current (5 mA) flows to the anti-fuse 1.
Attempt to pass the current of A).

Further, the potential of the node CI and the comparison potential are compared by the comparator 201. In the initial state where an EM current is going to flow through the designated anti-fuse 1,
Since the resistance value of the antifuse 1 is still large, a current does not flow through the antifuse 1, and the potential of the node CI is larger than the comparison voltage. Therefore, the program pulse signal PGM_ input to the NOR gate 203 is'L '. Even if it is at the “level”, the “H” level is continuously output from the comparator 201 and is input to the NOR gate 203 via the delay circuit 202.
H is at'L 'level, and antifuse 1 has EM
A voltage for applying a current (45 mA) corresponding to the current to the antifuse 1 is applied.

Next, it is assumed that the antifuse 1 has a dielectric breakdown after the time QBD shown in FIG. 3 has elapsed. Then, at this time, the resistance value of the antifuse 1 suddenly decreases, and a large current (about 45 mA) flows through the antifuse 1 to lower the potential of the node CI to 6 V or less. Then, the comparator 201 outputs an “L” level signal.

This'L 'level signal is applied to the delay circuit 2
02, the signal of the “L” level is delayed by the delay circuit 202 for 2 μsec, and is input to the NOR gate 203. Here, since the'L 'level program signal PGM_ is input to the NOR gate 203, the NOR gate 203 outputs the'H' level signal EMINH and the NMOS transistor 105 is turned off via the NOR gate 107. . Therefore, antifuse 1
MT current (5 mA) flows through the device. Then, the potential of the node CI drops to 0.5 V or less, and the signal of the “L” level is continuously output from the comparator 201. In this way, after the dielectric breakdown occurs, E is maintained for a certain time (2 μsec).
Since the M current is passed and then the MT current (5 mA) lower than the EM current (45 mA) is switched to, a filament having a stable small resistance value is obtained, and variations in resistance value and fusing due to excessive heat generation are prevented.

Next, after TPGM time has elapsed from the time when the program pulse signal PGM changes to the'H 'level,
When the program pulse signal PGM becomes'L 'level,
Since the “L” level is input to the NAND gate 10, the “H” level is output from the NAND gate 10, the output of the NAND gate 9 becomes the “L” level, the designation of the antifuse 1 is canceled, and the current to the antifuse 1 is released. Is cut off. Therefore, the potential of the node CI rises to about 9V. Further, since the “H” level program pulse signal PGM_ is input to the NOR gate 203, the “L” level signal EMINH is output from the NOR gate 203, the NMOS transistor 105 is turned on via the NOR gate 107, and the PMOS Transistor 101
EM current flows to the. After a predetermined time, the column address, load address, and write data D are input,
The “H” level is input as the program pulse signal PGM, and the above-described operation is repeatedly executed. Here, as shown in FIG. 3, even if the insulation breakdown time of each anti-fuse 1 is different, the anti-fuse 1 is changed according to the different insulation breakdown time.
Since writing is performed to the filament, a filament having a uniform and stable resistance value can be obtained.

In the above embodiment, the constant current circuit 100 and the detection circuit 200 corresponding to the write circuit according to the present invention.
Is an example of being mounted on one chip together with the block 300, and it is preferable to mount it on one chip.
The writing circuit of the present invention is not limited to one mounted inside the chip, and may be an external one when writing.
FIG. 4 is a circuit diagram of a write circuit portion to the antifuse of the second embodiment of the semiconductor device of the present invention.

In FIG. 4, a reference current generating circuit 400 for generating a reference current corresponding to each of the write mode, the sense mode and the additional write mode, a comparison voltage generating circuit 500 for generating a comparison voltage in the sense mode, A plurality of blocks 600_1, 600_ in which a plurality of antifuses 31 are arranged
2, ..., 600_k, a pass / fail gate circuit 700 that outputs a determination result as to whether or not the data was correctly written in the sense mode,
Also shown is a precharge control circuit 800 that transmits a control signal when precharging is performed.

Here, the write mode is a mode in which a write current is passed through the antifuse 31 in the off state to make a transition to the on state, and the sense mode is whether or not the antifuse 31 is correctly written. The mode in which a sense current that senses whether or not the current flows through the antifuse 31 is the mode in which an additional write current is supplied to the antifuse 31 that has transitioned from the off state to the on state to ensure the on state. is there.

A series of operations for writing, including the writing mode, the sensing mode, and the additional writing mode, may be collectively called "writing". Since the circuits inside the blocks 600_1, 600_2, ..., 600_k are the same as each other, only the block 600_1 is illustrated, and only the block 600_1 will be described.

Antifuse 3 in block 600_1
1 denotes a plurality of first signal lines 32_1 extending in the vertical direction of the figure.
, 32_1_m and a plurality of second signal lines 33_1_1, 33_1_ extending in the horizontal direction in the figure.
2, ..., 33_1_n, and the first signal lines 32_1_1, 32_1_2 ,.
_M and the second signal lines 33_1_1, 33_1_2,
, 33_1_n are connected to inputs and outputs of a plurality of circuits (not shown). These circuits are connected by different wirings depending on whether the antifuse 31 stays in the off state or transits to the on state, and different circuits are provided as a whole depending on the difference in the write data to the antifuse 31. Will be realized.

In the block 600_1, the PMOS transistors 34_1_1 and 34_1_ are provided to the first signal lines 32_1_1, 32_1_2, ..., 32_1_m, respectively.
One end of each of 2, ..., 34_1_m is connected. Those PMOS transistors 34_1_1, 34_1_
The other ends of 2, ..., 34_1_m are commonly connected and connected to the write power supply V _PP via the constant current supply line 36 and the PMOS transistor 37. The gates of the PMOS transistors 34_1_1, 34_1_2, ..., 34_1_m are connected to a column decoder (see FIG. 5A) described later, and the gate of the PMOS transistor 37 is connected to the plurality of blocks 600_ from the reference current generation circuit 400.
1, 600_2, ..., 600_k are connected to a constant current level transmission line 40 that extends.

Further, each second signal line 33_1_1, 33
, 33_1_n is connected to one end of each of the NMOS transistors 35_1_1, 35_1_2, ..., 35_1_n, and the NMOS transistors 35_1
The other ends of _1_1, 35_1_2, ..., 35_1_n are commonly connected, connected to the ground V _SS via the NMOS transistor 38, and connected to the constant current supply line 36 via the PMOS transistor 39. Those NMOS transistors 35_1_1 and 35_1_
The gates of 2, ..., 35_1_n are connected to a row decoder (see FIG. 5B) described later. Also NMOS
The gates of the transistor 38 and the PMOS transistor 39 are connected to a plurality of blocks 600_1, 6 from the output of the voltage conversion type inverter 801 of the precharge control circuit 800.
00_2, ..., 600_k is connected to a first precharge control line 802. The voltage conversion type inverter 801 has a precharge control signal P
RCG is input.

In the comparison voltage generating circuit 500, a resistor 501, a resistor 502, and an NMOS transistor 503 are arranged in series between the write power supply voltage V _PP and the ground V _SS . NMOS transistor 503
ON / OFF is controlled by the sense signal SENSE. From the connection point of the resistors 501 and 502, the first comparison signal line 504 is connected to the plurality of blocks 600_1,
, 600_k, the first comparison voltage VSND is transmitted to the first comparison signal line 504 when the sense signal SENSE is at the “H” level. Here, the resistance values of the two resistors 501 and 502 are the same, and therefore VSND = about V _PP / 2. The NMOS transistor 503 is arranged for the purpose of preventing unnecessary power consumption, and is turned on in the sense mode that requires the comparison voltage.

In the comparison voltage generation circuit 500,
Power supply voltage for writing V_PPAnd ground V _SSAnd between each other
NMOS transistor 505, resistor 506, resistor in series
507 and an NMOS transistor 508 are arranged
And the gate of the NMOS transistor 505 is the first
It is connected to the comparison signal line 504. In addition,
The transistor 508 is activated by the sense signal SENSE.
ON / OFF is controlled.

The second comparison signal line 509 is connected to a plurality of blocks 600 from the connection point of the resistors 506 and 507.
_1, 600_2, ..., 600_k, and the second comparison signal line 509 has a sense signal SE.
When NSE is at'H 'level, the second comparison voltage V
SON is transmitted. This second comparison voltage VSON is
A voltage higher than the voltage generated on the constant current supply line 36 when a sense current is passed through the antifuse 31 after transition to the ON state, VSON> (ON resistance of the antifuse 31) × sense current. Here, the NMOS transistor 505
Is the source follower, and NM is better than VSND.
A voltage lower than the threshold voltage V _TN of the OS transistor is a resistor 506 (assuming a resistance value R ₅₀₆ ) and a resistor 507 (a resistance value R).
₅₀₇ ) and the voltage divided by resistance becomes VSON.
_{That, VSON = (VSND-V TN} ) · R 507 / (R 506 + R
₅₀₇ ) Note that the NMOS transistor 508 is arranged for the purpose of preventing unnecessary power consumption, and is turned on in the sense mode which requires the comparison voltage.

The reference current generating circuit 400 is provided with a PMOS transistor 401, and the gate of the PMOS transistor 401 is connected to the constant current level transmission line 40. Therefore, the PMOS transistor 401 and the PMOS transistor 3 of the block 600_1 are
7 constitutes a current mirror circuit, and when the reference current I _SN flows through the PMOS transistor 401, the block 600_
1 through the PMOS transistor 37, the reference current I
A constant current corresponding to _SN is supplied to the antifuse 31 side.

The PMOS transistor 401 of the reference current generating circuit 400 has three resistors 402, 403 and 404.
Are connected, and the output of the voltage conversion type inverter 405 is connected to the other end of the resistor 402. The other ends of the resistors 403 and 404 are connected to the NMOS transistors 40, respectively.
Connected to ground V _SS via 6,407.

Incidentally, these three resistors 402, 403, 4
04 and each resistor 5 in the comparison voltage generation circuit 500
As 01, 502, 506 and 507, a polysilicon resistance, a well resistance, a diffusion resistance or a FET resistance is used. The voltage conversion type inverter 405 receives the pulse signal S / P / A at the'H 'level in any of the write mode, the sense mode, and the additional write mode. In the other modes, that is, in the normal operation mode in which the writing to the anti-fuse 31 is completed and this semiconductor device performs the intended circuit operation, it is held at the “L” level.

The program signal PROG is input to the gate of the NMOS transistor 406. The program signal PROG is a pulse signal which is at the “H” level during writing to the antifuse 31 and during additional writing. Also, the NMOS transistor 40
The additional write signal ADDP is input to the gate of 7.
The additional write signal ADDP is a pulse signal which becomes the “H” level only during the additional writing to the antifuse 31.

Thus, in the sense mode, S /
The P / A signal becomes “H” level, and the reference current I _SN of, for example, 3 mA flows through the PMOS transistor 401, and in the write mode, the S / P / A signal and the PPOG signal become “H” level. A reference current I _SN of, for example, 10 mA flows through 401, and in the additional write mode, the S / P / A signal, PROG signal, and ADD are added.
The P signal becomes'H 'level and the PMOS transistor 4
A reference current I _SN of, for example, 20 mA flows through 01.

In the sense mode, the pulse signal S / P / A is input to the voltage conversion type inverter 405, and the sense signal SENSE is input to the gates of the NMOS transistors 503 and 508 of the comparison voltage generation circuit 500. Then, the reference current for sensing flows in the reference current generating circuit 400, and accordingly, the PMOS transistor 37
A sense current flows through the constant current supply line 36 via the. Further, the comparison voltage generation circuit 500 outputs two comparison voltages VS.
ND and VSON are generated to generate the comparators 41 and 42.
Is input to A voltage clamping PMOS transistor 43 is arranged between the constant current supply line 36 and the ground V _SS, and the comparison voltage VSND is also applied to the gate of the PMOS transistor 43. Therefore, in the sense mode, the maximum voltage applied to the antifuse 31 via the constant current supply line 36 is VSND when the threshold voltage of the PMOS transistor 43 is V _TP.
It is clamped to + V _TP . This voltage is set to a voltage level at which the antifuse 31 in the off state does not transit to the on state even if the voltage is applied to the antifuse in the off state. This is a measure for preventing the antifuse 31 in the off state from inadvertently transitioning to the on state in the sense mode that senses whether the antifuse 31 is in the on state or the off state. is there. When the sense current is supplied to the antifuse 31 that is already in the ON state,
The voltage of the constant current supply line 36 becomes a voltage much lower than its clamp voltage.

Comparison voltage V of each comparator 41, 42
The other terminal, which is different from the one terminal to which SND and VSON are supplied, is connected to the constant current supply line 36. The output of the comparator 41 is input to the NAND gate 44, and the output of the comparator 42 is input to the OR gate 45. Further, the expected value PDATA (“L” level in the on state) of the on-state and the off-state of the currently sensed antifuse 31 is input to the NAND gate 44 and the OR gate 45. The output of NAND gate 44 and the output of OR gate 45 are both input to NAND gate 46, and the output of NAND gate 46 is the output of all blocks 600.
NAND gate 46 of _1, 600_2, ..., 600_k
Is input to the NAND gate 701 of the pass / fail gate circuit 700.

When the anti-fuse 31 which is going to flow the sense current as the object of the sense at present is in the off state, the potential of the constant current supply line 36 becomes the clamp voltage, which is higher than the comparison voltage VSND. Therefore, the comparator 41
Output becomes'H 'level and if it matches the expected value PDATA, the output of NAND gate 44 becomes'L' level and the output of NAND gate 46 becomes'H 'level.

On the other hand, when the antifuse 31 which has supplied the sense current is in the ON state, the potential of the constant current supply line 36 becomes lower than the comparison voltage VSON, and the output of the comparator 42 becomes the “L” level, Expected value PDAT
If it matches with A, the output of the OR gate circuit 45 becomes "L" level, and the output of the NAND gate 46 becomes "H" level.

When the sense current flows through the antifuse 31, and the current of the constant current supply line 36 is lower than the comparison voltage VSND and higher than the comparison voltage VSON, the output of the NAND gate 46 becomes "L" level. . When the output of the NAND gate 46 is at the'H 'level, the currently sensed antifuse 3 of the block 600_1 is
The on / off state of 1 is normal, and when it is at the'L 'level, it indicates that the antifuse is defective or the writing is incomplete.

All blocks 600_1, 600_2,
, 600_k, if the output of the NAND gate 46 is at the'H 'level, the output signal PASS_ of the NAND gate 701 is the current sensed block 600_.
All of the antifuses of 1,600_2, ..., 600_k are at the “L” level indicating that they are normal. Figure 5
FIG. 6 is a diagram showing input / output signals of a column decoder and a row decoder.

The column decoder 50_1 and the row decoder 60_1 shown in FIG. 5 correspond to the block 600_1 shown in FIG. 4, and the blocks 600_1 and 600_1 shown in FIG.
The column decoder 50_1 and the row decoder 60 shown in FIG. 5 corresponding to 600_2, ..., 600_k, respectively.
The same column decoder and row decoder as _1 are formed.

The column decoder 50_1 outputs all output signals C when the enable signal CSEL_ is at the "H" level.
OL11_, COL12 _, ..., COL1m_ is'H '
And the PMOS transistor 34_ shown in FIG.
All of 1_1, 34_1_2, ..., 34_1_m are turned off. When the enable signal CSEL_ is at the'L 'level and the CALL signal is at the'L' level, any output corresponding to the input column address CADDDR becomes the'L 'level, and the PMOS transistor shown in FIG. 34_1_1, 34_1_2, ..., 34_1_m
Any one of them is turned on. CSEL_ signal is'L '
Level and the CALL signal is at'H 'level,
All output signals COL11_, COL12 _, ..., CO
L1m_ becomes'L 'level and the PMOS transistors 34_1_1, 34_1_2, ..., 34_1_ shown in FIG.
All m are turned on.

The row decoder 60_1 outputs all output signals RO when the enable signal RSEL_ is at the "H" level.
W11, ROW12, ..., ROW1n are set to the “L” level, and the NMOS transistors 35_1_1 and 35-1_1 shown in FIG.
All of 35_1_2, ..., 35_1_n are turned off.
When the enable signal RSEL_ is at the'L 'level and the RALL signal is at the'L' level, any output according to the input row address RADDR becomes the'H 'level, and the NMOS transistor shown in FIG. Any one of 35_1_1, 35_1_2, ..., 35_1_n is turned on. When RSEL_ is at the'L 'level and the RALL signal is at the'H' level, all the output signals ROW11, ROW12, ..., ROW1n are at the'H 'level, and the NMOS transistor 35_1 shown in FIG.
All of _1, 35_1_2, ..., 35_1_n are turned on.

When writing to the antifuse 31,
First, before writing, the CALL signal and the RALL signal are set to the “H” level to set all the PMOS transistors 34_1_1, 34_1_2, 34_1_m and the NMOS transistors 35_1_1, 35_1_ shown in FIG.
2, ..., 35_1_n all turned on, and PRCG
The signal is set to'H 'level. In this way, S / P /
The A signal and the SENSE signal are set to the “H” level. Then, a current having the same level as the sense current has a plurality of first signal lines 32_1_1, 32_1_2, ..., 32_1_m.
All and a plurality of second signal lines 33_1_1, 33_
1_2, ..., it flows into all 33_1_N, the first signal line and all of the second signal lines all of which are both precharged to the same voltage VSND + V _TP. When precharge is completed, CSEL_ signal and RSEL_
The signal is set to the “H” level and the PRCG signal is returned to the “L” level. After that, writing to the antifuse 31 is performed.

As described above, by precharging before writing, an excessive voltage is not applied to the antifuses other than the antifuse that is about to be written, and the data is written carelessly during writing. Is prevented. FIG.
S / P / A signal when writing to antifuse,
6 is a timing chart showing changes in a PROG signal, an ADDP signal, and a SENSE signal.

First, the column decoder 50_ shown in FIG.
1. By the row decoder 60_1, m PMOS transistors 34_1_1, 34_1_2, ..., 34_1_
One of n and n NMOS transistors 35
1 of _1_1, 35_1_2, ..., 35_1_n
A signal is output so that the individual pieces are turned on, and the antifuses 31 at their intersections are designated.

However, when the antifuse 31 at the intersection is left in the off state, the C input to the column decoder 50_1 and the row decoder 60_1 shown in FIG.
At least one of the SEL_ signal and the RSEL_ signal is set to the'H 'level. By doing this, the PMOS transistors 34_1_1, 34_1_2, ..., 34_1
_M or NMOS transistor 35_1_
1, 35_1_2, ..., 35_1_n are all turned off, and the column address CADDDR and the load address R
Writing to the antifuse, which should be designated by ADDR, is not performed.

The operation of designating the antifuse is performed in parallel in each of the blocks 600_1, 600_2, ..., 600_k. Note that, here, it is assumed that the antifuse 31 at a certain intersection inside the block 600_1 is designated to write to the antifuse 31.

Next, as shown in FIG. 6, the S / P / A signal and the PROG signal are pulsed to the'H 'level (pulse a in FIG. 6). As a result, the first writing is performed. Next, the S / P / A signal and the SENSE signal are pulsed to the “H” level (pulse b). As a result, it is sensed whether or not the antifuse that is about to be programmed has transited to the ON state. When it is still in the off state, the S / P / A signal and the PROG signal again become “H” level in a pulse shape (pulse c), writing is tried again, and then the S / P / A signal and the SENSE signal are output. It becomes the "H" level (pulse d), and it is sensed whether or not it has transited to the ON state. This is repeated as needed, and at the timing of the pulse x shown in FIG.
00_1, 600_2, ..., 600_k are expected values PDA
When it is in the state as TA, it is detected that the PASS_ signal becomes the “L” level and the writing is normally performed. Then, this time, the S / P / A signal, the PROG signal, and the ADDP signal become the “H” level for the same time width as the total pulse width of the writing pulses a, c, ... Additional writing is performed for the same time as the total time. As a result, the written antifuse is surely turned on. The above is repeated while sequentially changing the addresses CADDDR and RADDR input to the column decoder 50_1 and the row decoder 60_1.

The write voltage V _PP (eg, 10 V) is input from the terminal supplying the write power supply voltage V _PP during the above-described writing, and the unwritten test described below is performed. In the mode, an intermediate voltage (for example, 6.5V) that does not cause the antifuse in the off state to transition to the on state is input, and in the normal operation mode, the voltage for logic of the internal circuit (for example, 3.3V) is input. To be done.

The unwritten test mode is a test performed to detect a process defect of the antifuses, and even if the above-mentioned medium voltage (eg 6.5 V) is applied to all the antifuses. The anti-fuse is a mode in which a non-writing test is performed to confirm that the anti-fuse also remains in the off state, and is used for determining the quality of the product.
At this time, the column decoder 50_1 and the row decoder 6
The CALL signal and the RALL signal of the “H” level are input to 0_1, and the PMOS transistors 34_1_1 and 34_1
34_1_m and all NMOS transistors 35_1_1, 35_1_2, ..., 35_1_n are turned on. However, unlike the case of precharge, the PROG signal remains at the “L” level and the NMO
S transistors 35_1_1, 35_1_2, ..., 35
The commonly connected side of _1_n is connected to the ground V _SS . In this way, the write current is supplied. However, the write voltage V _PP is a medium voltage (for example, 6.5 V). When all the antifuses remain in the off state, the constant current supply line 36 has a medium voltage, and when one of the antifuses turns on, a defect occurs, and the constant current supply line 36 is much more than that. It becomes a low voltage. Whether or not there is a defective anti-fuse is the expected value PDATA.
To "H" level and the SENSE signal to "H" level for sensing.

Next, a modification of the above-described second embodiment will be described. First, it has been described that the reference current generation circuit 400 generates different reference currents I _SN in the write mode, the sense mode, and the additional write mode. However, in the additional write mode, the current value is the current value of the write mode. Alternatively, additional writing may be performed by extending the pulse width. That is, the current value may be set to 10 mA instead of 20 mA, and the pulse width of the additional writing may be doubled instead. In this case, the circuit of the resistor 404 and the NMOS transistor 407 shown in FIG. 4 can be eliminated.

Further, the reference current in the write mode and the reference current in the sense mode may be the same. In that case, the circuit of the resistor 403 and the NMOS transistor 406 can be eliminated. The distinction between the write mode and the sense mode depends on the pulse width and whether the SENSE signal is set to the “H” level to activate the voltage clamp (sense mode).

In the comparison voltage generation circuit 500, the resistors 501 and 502 may be replaced with FETs, and in that case, the resistor 502 and the NMOS transistor 503 can be integrated. FIG. 7 is a circuit diagram of the circuit configured as described above for generating the comparison voltage VSND. Also,
Similarly, the resistors 506 and 507 may be replaced by FETs, in which case the resistor 507 and the NMOS transistor 508 can be integrated. FIG. 8 is a circuit diagram of a circuit configured to generate the comparison voltage VSON as described above.

Further, in FIG. 4, the reference current generating circuit 400 is set by setting the S / P / A signal to the “H” level.
In FIG. 9, the reference current in the sense mode is generated, and the current mirror circuit generates the sense current at the same level as that. However, as shown in FIG. 9, a constant current is generated from the comparison voltage VSND via the NMOS transistor 505 and the resistor 510. The sense current may be supplied to the supply line 36. At this time, when the antifuse is in the off state, the comparison voltage V
Threshold voltage V of NMOS transistor 505 from SND
_Since the voltage is lowered by _{TN, the} clamp circuit by the PMOS transistor 43 shown in FIG. 4 is not necessary, but the comparator 4 uses the voltage VSOFF lowered by the threshold voltage V _TN of the NMOS transistor 511 as the comparison voltage.
Feed to 1.

FIG. 10 shows a third semiconductor device of the present invention.
It is a circuit diagram of a writing circuit portion to the antifuse of the embodiment. The same elements as those of the second embodiment shown in FIG. 4 are designated by the same reference numerals as those of FIG. 4, and the differences will be described. The circuit shown in FIG. 10 is different from the circuit shown in FIG. 4 in that the comparison voltage generation circuit 500 is provided with a comparison voltage generation circuit 520 for dielectric breakdown detection.
Delay circuit 4 connected to the output of comparator 42
8, and the output of the delay circuit 48 and the program signal PROG are input and the output is the NMOS transistor 4
An AND gate 49 connected to the gate of 06 is added. In addition, the reference current generation circuit 400 includes each block 6
00_1, 600_2, ..., 600_K, respectively.

Comparison voltage generation circuit 520 for dielectric breakdown detection
Is a circuit for generating a comparison voltage for detecting whether or not the antifuse 31 has caused a dielectric breakdown in the write mode, and is connected in series between the second comparison signal 509 and the ground V _SS. Resistor 512, and NMO
The S transistor 513 is arranged. That NMOS
The program signal PRO is applied to the gate of the transistor 513.
G is input.

In the write mode, the program signal PR
Since the OG is at the “H” level and the sense signal SENSE is at the “L” level, the second comparison signal line 509 has a resistance lower than the write power supply voltage V _PP by the threshold voltage V _TN of the NMOS transistor 505. The insulation breakdown detection comparison voltage divided by 506 and the resistor 512 is output, and the insulation breakdown detection comparison voltage is input to the comparator 42. In the write mode, the constant current supply line 36 is at the write power supply voltage V _PP before the antifuse 31 causes the dielectric breakdown.
Therefore, the output of the comparator 42 is at the'H 'level. When dielectric breakdown occurs in the antifuse 31, the voltage of the constant current supply line 36 becomes lower than the dielectric breakdown detecting comparison voltage, and the output of the comparator 42 is inverted to the “L” level. This'L 'level signal is delayed by, for example, 2 μsec by the delay circuit 48 and transmitted to one input of the AND gate 49. At that time, the'H' level program signal PROG is cut off by the AND gate 49 and NMO.
The S transistor 406 is turned off and the current flowing through the resistor 403 is cut off. That is, at that point,
The write current is limited only to the current flowing through the resistor 402.

In the case of the embodiment shown in FIG. 10, as in the case of the embodiment shown in FIG. 1, even if the time until the dielectric breakdown of each antifuse 31 is different, writing according to the different dielectric breakdown time is performed. Therefore, a filament having a more uniform and stable resistance value can be obtained.

[0085]

As described above, according to the present invention,
A stable filament with a small resistance value and little variation is formed, and high-speed operation of PLDs and PROMs is possible. Also, since the timing skews of these PLDs and PROMs are small, malfunctions do not occur easily, and it is possible to switch off during operation. And reliable chips are manufactured.

Further, according to the present invention, a programmable semiconductor device which has a constant voltage power supply terminal for writing and which can be easily written by a method similar to the case of writing to a normal RAM etc. Is configured.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an anti-fuse write circuit of a PLD that incorporates a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing each example of a voltage conversion type inverter.

3 is a timing chart of the anti-fuse write circuit shown in FIG.

FIG. 4 is a circuit diagram of a write circuit portion to an antifuse of a second embodiment of a semiconductor device of the present invention.

FIG. 5 is a diagram showing input / output signals of a column decoder and a row decoder.

FIG. 6 S / P when writing to an antifuse
/ A signal, PROG signal, ADDP signal, and SEN
It is a timing chart which shows change of SE signal.

FIG. 7 is a circuit diagram showing a modified example of a comparison voltage generation circuit.

FIG. 8 is a circuit diagram showing a modified example of a comparison voltage generation circuit.

FIG. 9 is a circuit diagram showing a modified example of a sense current generation circuit.

FIG. 10 is a circuit diagram of a write circuit portion to an antifuse of a third embodiment of a semiconductor device of the present invention.

[Explanation of symbols]

1,31 antifuses 2_1, 2_2, ..., 2_m; 32_1_1, 32_1
_2, ..., 32_1_m First signal lines 3_1, 3_2, ..., 3_n; 33_1_1, 33_1
_2, ..., 33_1_n Second signal line 4_1, 4_2, ..., 4_m; 5_1, 5_2, ..., 5
_N; 35_1_1, 35_1_2, ..., 35_1_
n, 38, 52, 105, 406, 407, 503, 5
08, 511, 513 NMOS transistors 6_1, 6_2, ..., 6_m; 8_1, 8_2, ..., 8
_N, 104,405,801 Voltage conversion type inverters 7_1,7_2, ..., 7_m, 9,10 NAND gate 11,50_1 Column decoder 12,60_1 Row decoder 34_1_1,34_1_2, ..., 34_1_m, 3
7, 39, 43, 101, 106, 401 PMOS transistor 36 constant current level transmission line 40 constant current level transmission line 41, 42, 201 comparator 44, 46, 701 NAND gate 45 OR gate 48, 202 delay circuit 49 AND gate 100 constant current Circuits 102, 103, 402, 403, 404, 501, 5
02, 506, 507, 510, 512 resistance 107, 203 NOR gate 200 detection circuit 300, 600_1, 600_2, ..., 600_k block 400 reference current generation circuit 500 comparison voltage generation circuit 504 first comparison signal line 509 second comparison signal Line 520 Dielectric breakdown detection comparison voltage generation circuit 700 Pass / fail gate circuit 800 Write control circuit 802 Write control line

Claims (11)

[Claims] 1. A first signal line and a second signal line intersecting each other.
Signal line and an anti-fuse arranged at the intersection of the first signal line and the second signal line, and power is supplied to the anti-fuse in the cutoff state to make the anti-fuse fixedly conductive. In a semiconductor device in which a different circuit operation is realized depending on whether or not writing to make a transition to a state is performed with respect to the antifuse arranged at the intersection, a resistance value of the antifuse is used to supply a constant current to the antifuse. A constant current circuit that changes and applies a voltage equal to or lower than a predetermined voltage to the antifuse, and a detection circuit that detects whether or not a current has started to flow through the antifuse, and the constant current circuit is configured by the detection circuit. A predetermined first constant current is supplied to the antifuse for a predetermined period of time after it is detected that a current starts flowing through the antifuse. Semiconductor devices, wherein upon lapse between is to stop the supply of current to the anti-fuse. 2. A first signal line and a second signal line intersecting each other
Signal line and an anti-fuse arranged at the intersection of the first signal line and the second signal line, and power is supplied to the anti-fuse in the cutoff state to make the anti-fuse fixedly conductive. In a semiconductor device in which a different circuit operation is realized depending on whether or not writing to make a transition to a state is performed with respect to the antifuse arranged at the intersection, a resistance value of the antifuse is used to supply a constant current to the antifuse. A constant current circuit that changes and applies a voltage equal to or lower than a predetermined voltage to the antifuse, and a detection circuit that detects whether or not a current has started to flow through the antifuse, and the constant current circuit is configured by the detection circuit. A predetermined first constant current is supplied to the antifuse before a predetermined time has elapsed after it is detected that a current has started to flow in the antifuse. A semiconductor device which is characterized in that supplies a constant current of said second to said antifuse is switched to the smaller second constant current than the first constant current when said predetermined time has elapsed. 3. The semiconductor device according to claim 1, wherein the detection circuit is a comparator that compares a voltage at one end of the antifuse or a voltage corresponding to the voltage with a predetermined reference voltage. . 4. A first signal line and a second signal line intersecting each other.
Signal line and an anti-fuse arranged at the intersection of the first signal line and the second signal line, and power is supplied to the anti-fuse in the cutoff state to make the anti-fuse fixedly conductive. In a semiconductor device in which a different circuit operation is realized depending on whether or not writing to make a transition to a state is performed with respect to an antifuse arranged at the intersection, the antifuse is changed from a cutoff state to a conductive state. A write mode for supplying a write current to the antifuse, a sense mode for supplying a sense current to the antifuse to sense the state of the antifuse, and an additional write to the antifuse in which writing has been performed. A semiconductor device having a constant current circuit that can be switched to an additional write mode for supplying an additional write current for chair. 5. The constant current circuit includes a voltage clamp circuit that limits the voltage applied to the antifuse in the cutoff state to a voltage at a level at which the antifuse remains in the cutoff state in the sense mode. The semiconductor device according to claim 4, wherein the semiconductor device is a semiconductor device. 6. The semiconductor device according to claim 4, further comprising a state detection circuit that detects a state of the antifuse based on a voltage generated when the sense current is supplied to the antifuse. . 7. The first signal line includes a plurality of first signal lines extending in parallel with each other, and the second signal line includes a plurality of second signal lines extending in parallel with each other,
A semiconductor device in which the antifuse is arranged at each intersection of the plurality of first signal lines and the plurality of second signal lines, and the antifuse is connected in series to each of the plurality of first signal lines. First switch circuit, a second switch circuit serially connected to each of the plurality of second signal lines, and a plurality of first signal lines by controlling the first switch circuit A first decoder for switchably selecting a desired first signal line of the plurality of second signal lines, and a desired second signal of the plurality of second signal lines by controlling the second switch circuit. A second decoder for switchably selecting a line, wherein the constant current circuit includes the first decoder and the second decoder.
5. A semiconductor device according to claim 4, wherein one or more antifuses simultaneously selected for writing by the decoder of the above are supplied in parallel with constant currents controlled independently of each other. . 8. The first decoder and the second decoder respectively select all the first signal lines and all the second signal lines selected by the first decoder and the second decoder, respectively. 8. The semiconductor device according to claim 7, wherein the semiconductor device has a mode for simultaneously selecting. 9. The constant current circuit generates a reference current by a reference current generation circuit for generating a reference current, and a constant current according to the reference current generated by the reference current generation circuit by a current mirror circuit, and supplies it to the antifuse. 5. A semiconductor device according to claim 4, further comprising a constant current supply circuit for supplying the constant current. 10. A detection circuit for detecting whether or not a current has started to flow through the antifuse in the write mode, wherein the constant current circuit causes a current to flow through the antifuse by the detection circuit in the write mode. To the antifuse before a predetermined time has elapsed after it was detected that
The first constant current is supplied as the write current, and the supply of the write current to the antifuse is stopped when the predetermined time has elapsed. Semiconductor device. 11. A detection circuit for detecting whether or not a current has started flowing through the antifuse in the write mode, wherein the constant current circuit causes a current to flow through the antifuse by the detection circuit in the write mode. To the antifuse before a predetermined time has elapsed after it was detected that
A predetermined first constant current is supplied as the write current, and when the predetermined time elapses, the write current is changed to the first constant current.
The second constant current smaller than the constant current of
5. The semiconductor device according to claim 4, wherein the constant current is supplied to the antifuse as the write current.