JPH08330304A - Preparation of oxide film, fabrication of semiconductor device and preparation of superconducting thin film - Google Patents

Abstract

PURPOSE: To provide a method for preparing an oxide film by CVD using a material gas having melting point lower than that of triphenyl bismuth. CONSTITUTION: An oxide containing bismuth as a constitutive element is prepared by CVD using triphenyl bismuth having a meta position substituted with an alkyl group, which may be substituted with a halogen, as a material gas. For example, an oxide of Bi2 SrTa2 O9 is prepared by MOCVD using Tris (m- methyl phenyl) bismuth as a material gas.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an oxide film, a method for manufacturing a semiconductor device, to which a metalorganic chemical vapor deposition method using a novel triphenylbismuth-based source gas is applied,
And a method for forming a superconductor thin film. Here, the semiconductor device is composed of a nonvolatile memory cell (so-called FERAM) using a ferroelectric thin film or a DRAM.

[0002]

2. Description of the Related Art An oxide film containing bismuth (Bi) as a constituent element is represented by the so-called Y1 material system (Bi ₂ AB ₂ O ₉₎ , where A is 1 selected from the group consisting of Sr, Ba and Ca.
B is a single element selected from the group consisting of Ta and Nb, and examples thereof include Bi ₂ SrTa ₂ O ₉ ) and bismuth titanate (Bi ₄ Ti ₃
O _{1 2} , sometimes abbreviated as BTO hereinafter), Bi-Sr-C
The a-Cu-O system and the like are known, and these oxide films have unique properties such as ferroelectricity or superconductivity. These oxide films are formed by metalorganic chemical vapor deposition (Me
tal Organic Chemical Vapor Deposition method. Below, M
When forming a film by the OCVD method), triphenylbismuth represented by the following chemical formula is usually used as a source gas (for example, Document 1, "Ferroelectric b").
ismuth titanate films by hot wall metalorganic che
mical vapor deposition ", J. Si, et al., J. Appl. P
hys. 73 (11), 1 June 1993, pp7910-7913).

[0003]

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Generally, when an organometallic material is used as a raw material in the MOCVD method, it is necessary to supply the organometallic material in a gaseous state to the MOCVD reaction chamber. Therefore, the organometallic material is required to have a sufficiently high vapor pressure at a temperature as low as possible. Triphenylbismuth is a solid at room temperature and pressure and has a melting point of 78 to 80 ° C.
Therefore, when using triphenylbismuth as a raw material in the MOCVD method, it is necessary to maintain the raw material container (cylinder) filled with triphenylbismuth and the piping from the raw material container to the MOCVD reaction chamber at a high temperature equal to or higher than the melting point. For example, according to the above-mentioned Document 1, in order to obtain a sufficient vapor pressure of triphenylbismuth, it is necessary to maintain the temperature of the raw material container at 165 to 170 ° C.

[0005]

Problems to be Solved by the Invention For example, Bi ₂ SrTa ₂
When forming a film of O ₉ or bismuth titanate (BTO) by the MOCVD method, if the temperature of the raw material container is kept at 165 to 170 ° C. in order to obtain a sufficient vapor pressure of triphenylbismuth, the following problems will occur. Occurs. That is, since triphenylbismuth is kept at a high temperature for a long time, triphenylbismuth in the raw material container is gradually decomposed, and it becomes difficult to maintain a stable supply of raw material gas. In addition, in order to effectively supply the raw material gas and also to prevent re-aggregation of triphenylbismuth in the pipe in the process of supplying the raw material gas to the MOCVD reaction chamber, the pipe is provided at 180 to 200 ° C.
Need to be heated. However, such temperature control is difficult and it is difficult to maintain the entire MOCVD apparatus.

Because of such a problem, generally, when an oxide film containing bismuth as a constituent element is formed by the MOCVD method using triphenylbismuth as a source gas,
It is difficult to obtain good film formation controllability and film formation reproducibility.

Therefore, an object of the present invention is to provide an oxide film forming method, a semiconductor device manufacturing method, and a superconductor thin film of a MOCVD method using a material having a melting point lower than that of triphenylbismuth as a source gas. It is to provide a film forming method.

[0008]

Means for Solving the Problems In order to achieve the above object, the method of forming an oxide film according to the present invention uses triphenylbismuth whose meta position is substituted with an alkyl group which may be substituted with halogen as a source gas. It is characterized in that an oxide film containing bismuth as a constituent element is formed by the metal organic chemical vapor deposition method used as.

In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention is a metal organic chemical reaction using triphenylbismuth substituted at the meta position with an alkyl group which may be substituted by halogen as a source gas. It is characterized in that an oxide film containing bismuth as a constituent element is formed on a substrate by a vapor phase growth method.

In the method of manufacturing a semiconductor device of the present invention, the semiconductor device has a capacitor structure in which a lower electrode layer, a bismuth layer structure perovskite type ferroelectric layer and an upper electrode layer are laminated, and the ferroelectric layer Is formed of the oxide film. In this case, the lower electrode layer corresponds to the base. Alternatively, the semiconductor device has a capacitor structure in which a lower electrode layer, a bismuth layered structure perovskite type ferroelectric layer and an upper electrode layer are stacked, and a bismuth layered structure perovskite type buffer formed under the lower electrode layer. And a buffer layer formed of the oxide film. In this case, the insulating layer formed under the buffer layer corresponds to the base. The ferroelectric layer may be composed of the oxide film. In these cases, the oxide film is formed of, for example, bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ) or so-called Y1 material system Bi ₂ AB ₂ O ₉ (where A is S
R is one element selected from the group consisting of r, Ba and Ca, and B is one element selected from the group consisting of Ta and Nb). When the oxide film is composed of so-called Y1 material system Bi ₂ AB ₂ O ₉ ,
The film formation of the oxide film containing bismuth as a constituent element in the metal organic chemical vapor deposition method is 1.0 × 10 ² Pa to 1.
Under a pressure of 4 × 10 ³ Pa, more preferably 6.7 × 1
0 ² Pa (5 Torr) to 1.3 × 10 ³ Pa (10 Torr)
It is preferable to carry out under pressure. As Y1 material system,
Bi ₂ SrTa ₂ O ₉ can be exemplified.

In order to achieve the above object, a method for forming a superconductor thin film according to the present invention is an organic method using triphenylbismuth substituted at the meta position with an alkyl group which may be substituted with halogen as a source gas. With metal chemical vapor deposition,
A feature is that a superconductor thin film made of an oxide film containing bismuth as a constituent element is formed on a substrate. The superconductor thin film may be made of Bi-Sr-Ca-Cu-O system.

Triphenylbismuth substituted in the meta position with an alkyl group in the present invention is represented by the following chemical formula. As at least one of R ₁ and R ₂ , for example, CH ₃ , C ₂ H ₅ , CH (CH ₃ ) ₂ and C (CH ₃ ) ₃ can be exemplified, and among them, tris (m-methylphenyl). Bismuth is preferably used as a source gas in the MOCVD method. Moreover, the hydrogen atom which comprises an alkyl group may be substituted by halogen. In this case, R
CF ₃ can be exemplified as at least one of ₁ and R ₂ , and an alkyl group including such a case is referred to as an alkyl group which may be substituted with halogen.

[0013]

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[0014]

In the present invention, triphenylbismuth whose meta position is substituted with an alkyl group which may be substituted with halogen is used as the source gas in the MOCVD method.
The melting point of the source gas is lower than that of triphenylbismuth. For example, the melting point of tris (m-methylphenyl) bismuth measured by differential thermal analysis is 67 ° C, and the melting point of triphenylbismuth is 78 ° C. Therefore, the temperature of the raw material container and the piping in the MOCVD apparatus can be lowered, and when forming an oxide film containing bismuth as a constituent element by the MOCVD method, good film formation controllability and film formation reproducibility can be obtained. It will be possible.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings.

(Example 1) In Example 1, tris (m-methylphenyl) bismuth (R ₁ = CH ₃ , R ₂ = H) represented by the following chemical formula, and tris (m-tolyl) bismuth was used. (Also called) as the source gas
The present invention relates to an oxide film forming method for forming an oxide film containing bismuth as a constituent element by the OCVD method. The oxide film is made of Bi ₂ SrTa ₂ O ₉ which is a Y1 material system.

[0017]

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As shown in the conceptual diagram of FIG. 1, the MOCVD apparatus comprises stainless steel raw material containers 10, 12 and M.
OCVD reaction chamber 20, raw material containers 10 and 12 and MOCVD
Stainless steel piping 14,1 connecting the reaction chamber 20
It is composed of 5. In addition, the raw material containers 10 and 12 are
It is housed in the constant temperature baths 11 and 13 and has a structure capable of holding the raw materials in the raw material containers 10 and 12 at a desired temperature. A heating means (not shown) such as a heater is arranged in the pipes 14 and 15 to keep the raw material gas flowing in the pipes at a desired temperature. The raw material gas introduced into the MOCVD reaction chamber 20 is passed through the gas spray nozzle 21 and the substrate stage 2
It is sprayed onto the substrate 30 placed on the substrate 2. As a result, a thin film is formed on the surface of the substrate 30. A heater (not shown) is incorporated in the substrate stage 22 to heat the substrate 30 to a desired temperature. MOCV
The inside of the D reaction chamber 20 is evacuated by the vacuum pump 23.

In carrying out the MOCVD method, tris (m-methylphenyl) bismuth is filled in the raw material container 10 and the tris (m-methylphenyl) bismuth in the raw material container 10 is heated to about 100 ° C. Argon gas having a flow rate of 50 cc is introduced into the raw material container 10 and bubbling of tris (m-methylphenyl) bismuth which is liquid under heating and reduced pressure. Then, the vaporized tris (m-methylphenyl) bismuth is introduced into the pipe 14 kept at about 140 ° C. and sent to the MOCVD reaction chamber 20. When conventional triphenylbismuth is used, the raw material container 10
And the temperature of the pipe 14 to 1
It is necessary to maintain the temperature at 80 to 200 ° C.

On the other hand, Sr (C ₁₁ H ₁₉ O ₂ ) ₂ [dis (tetramethylheptanedione) strontium], and Ta
(OC ₂ H ₅ ) ₅ [pentaethoxy tantalum] was filled in different raw material containers 12 (note that one raw material container 12 is shown in FIG. 1).
(Only shown), Sr (C ₁₁ H ₁₉ O in the raw material container 12
₂ ) ₂ and Ta (OC ₂ H ₅ ) ₅ are heated to about 210 ° C and about 120 ° C, respectively, and each raw material container 12
Then, an argon gas having a flow rate of 50 cc is introduced to bubbling these source materials which are liquid under heating and reduced pressure. Then, connect the pipe 15 for Sr (C ₁₁ H ₁₉ O ₂ ) ₂ to about 2
20 ° C, Ta (OC ₂ H ₅ ) ₅ piping is about 150 ° C
Then, these vaporized source materials are introduced into these pipes 15 and sent to the MOCVD reaction chamber 20 via the pipes 14.

The substrate 30 placed on the substrate stage in the MOCVD reaction chamber 20 is heated to about 650 to 750 ° C., and gaseous tris (m-
Methylphenyl) bismuth, gaseous Sr (C ₁₁ H ₁₉ O
₂ ) ₂ , Ta (OC ₂ H ₅ ) ₅ , oxygen gas and diluting argon gas are introduced, and the pressure in the MOCVD reaction chamber 20 is set to 1.
The oxide film made of Bi ₂ SrTa ₂ O _{9 is} formed on the substrate 30 while controlling the pressure to be 0 × 10 ^{2 to} 1.4 × 10 ³ Pa.

Sr (C ₁₁ H ₁₉ O ₂ ) ₂ [dis (tetramethylheptanedione) strontium] and Ba (C ₁₁ H ₁₉ O ₂ ) were used as the source materials for Sr, Ba and Ca.
₂ [dis (tetramethylheptanedione) barium] and Ca (C ₁₁ H ₁₉ O ₂ ) ₂ [dis (tetramethylheptanedione) calcium] were used as Ta (OC ₂ H ₅ ) source material for Ta and Nb. _{If 5} [pentaethoxy tantalum] and Nb (OC ₂ H ₅ ) ₅ [pentaethoxy niobium] are used, Bi ₂ AB ₂ O ₉ (where A is one selected from the group consisting of Sr, Ba and Ca) is used. , And B is one element selected from the group consisting of Ta and Nb) can be formed on the substrate by MOCVD. As a combination of elements A / B,
Not only Sr / Ta, but also Sr / Nb, Ba / Ta, Ba
/ Nb, Ca / Ta, Ca / Nb can be mentioned.

(Embodiment 2) In recent years, along with the progress of film forming technology, application research of a non-volatile memory cell using a ferroelectric thin film has been actively pursued. This non-volatile memory cell is a non-volatile memory cell in which high-speed reversal of the ferroelectric thin film and high-speed rewriting utilizing the residual polarization thereof are possible. The ferroelectric thin film non-volatile memory cell currently being researched has a method of detecting a change in the stored charge amount of the ferroelectric capacitor,
It can be classified into two methods of detecting a resistance change of a semiconductor due to spontaneous polarization of a ferroelectric substance. The semiconductor memory cell to which the method for manufacturing a semiconductor device of the present invention is applied belongs to the former.

An example of a non-volatile memory cell of the type that detects a change in the amount of charge stored in the ferroelectric capacitor is a non-volatile memory cell having a one-capacitor + 1-transistor structure in which a selection transistor is added to the ferroelectric capacitor. You can The ferroelectric capacitor is composed of, for example, a lower electrode, an upper electrode, and a ferroelectric thin film sandwiched between them. Data writing and reading in this type of non-volatile memory cell are performed by applying the PE hysteresis loop of the ferroelectric substance shown in FIG. When an external electric field is removed after applying an external electric field to the ferroelectric thin film, the ferroelectric thin film exhibits spontaneous polarization.
The remanent polarization of the ferroelectric thin film becomes + P _r when an external electric field in the positive direction is applied, and −P _r when an external electric field in the negative direction is applied. Where remanent polarization is +
It is assumed that the state of P _r (see “D” in FIG. 13) is “0”, and the state of remanent polarization is −P _r (see “A” of FIG. 13) is “1”.

In order to determine the state of "1" or "0", an external electric field in the positive direction, for example, is applied to the ferroelectric thin film. As a result, the polarization of the ferroelectric thin film becomes the state of "C" in FIG. At this time, if the data is "0", the polarization state of the ferroelectric thin film changes from "D" to "C". On the other hand, if the data is "1", the polarization state of the ferroelectric thin film changes from "A" to "C" via "B". If the data is "0",
The polarization reversal of the ferroelectric thin film does not occur. On the other hand, the data is "
In the case of 1 ", polarization inversion occurs in the ferroelectric thin film. As a result, there is a difference in the amount of charge stored in the ferroelectric capacitor. This storage is turned on by turning on the select transistor of the selected memory cell. The charge is detected as a signal current.
When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric thin film becomes the state of “D” in FIG. 13 regardless of whether the data is “0” or “1”. Therefore, when the data is "1", an external electric field in the negative direction is applied to bring the state of "A" through the paths "D" and "E", and the data "1" is written.

Example 2 is a MOCVD method using tris (m-methylphenyl) bismuth (R ₁ ═CH ₃ , R ₂ ═H) as a source gas, and an oxide film containing bismuth as a constituent element is formed on a substrate. The present invention relates to a method of manufacturing a semiconductor device which is formed into a film. The oxide film is made of Bi ₂ SrTa ₂ O ₉ . The semiconductor device includes the above-mentioned nonvolatile memory cell (so-called FERAM).

FIG. 2A is a schematic partial sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device of Example 2.
Shown in An equivalent circuit of the semiconductor device is shown in FIG. This semiconductor device has a capacitor structure in which a lower electrode layer 52, a bismuth layer structure perovskite type ferroelectric layer 53 and an upper electrode layer 54 are laminated. And
The ferroelectric layer 53 is composed of an oxide film made of Bi ₂ SrTa ₂ O ₉ and containing bismuth as a constituent element. In this case, the lower electrode layer 52 corresponds to the base.

More specifically, this semiconductor device has source / drain regions 44 and 45 and a channel region 46 formed on a semiconductor substrate 40 made of a silicon semiconductor substrate.
A gate electrode 43 formed above the channel region 46, and an element isolation region 41 having a LOCOS structure.
And a gate oxide film 42 formed under the gate electrode 43.
Consists of. These source / drain regions 44, 45,
The channel region 46 and the gate electrode 43 form a so-called select transistor. The gate electrode 43
Also serves as a word line, and is made of, for example, polysilicon, polycide, or metal silicide.
The source / drain regions 44 and 45 and the gate electrode 43 are covered with the insulating layer 50. The insulating layer 50 is made of BPSG, for example.

In the capacitor structure of this semiconductor device, the lower electrode layer 52 made of Pt (platinum) (corresponding to the substrate) is formed on the insulating layer 50 made of BPSG. Further, the bismuth layered structure perovskite type Bi
_A ferroelectric layer 53 made of ₂ SrTa ₂ O ₉ is formed on the lower electrode layer 52. Further, an upper electrode layer 54 made of Pt is formed on the ferroelectric layer 53.

An upper insulating layer 60 made of, for example, BPSG is formed on the insulating layer 50, the lower electrode layer 52 and the upper electrode layer 54.
Are formed. A contact plug 65 is formed in the insulating layer 50 and the upper insulating layer 60 above the one source / drain region 44 (for example, the source region), and the contact plug 65 has one source / drain at the bottom thereof. It is electrically connected to the region 44. A contact plug 66 is also formed on the upper insulating layer 60 above the lower electrode layer 52. The lower electrode layer 52 is electrically connected to one of the source / drain regions 44 via the contact plug 66, the first wiring layer 68, and the contact plug 65. The upper electrode layer 54 is electrically connected to the second wiring layer 69 via the contact plug 67 formed above the upper electrode layer 54. The second wiring layer 69 corresponds to a plate line.

The other source / drain region 45 (eg drain region) is electrically connected to a bit line (not shown) via a bit contact portion (not shown).

A method of manufacturing a semiconductor device according to the second embodiment will be described below with reference to FIGS. 3 to 5 which are schematic partial sectional views of a semiconductor substrate and the like.

[Step-200] First, the semiconductor substrate 40 made of a silicon semiconductor substrate is subjected to LO based on a known method.
An element isolation region 41 having a COS structure is formed. Next, the gate oxide film 42 is formed by oxidizing the surface of the semiconductor substrate 40.
To form. Then, after depositing a polysilicon layer on the entire surface by, for example, a CVD method, the polysilicon layer is patterned by a photolithography technique and an etching technique to form a gate electrode 43 made of polysilicon.
The gate electrode 43 also serves as a word line. Next, ion implantation of impurity ions and activation of the implanted impurities are performed to form the source / drain regions 44 and 45 and the channel region 46.

[Step-210] Next, the insulating layer 50 made of, for example, BPSG is formed on the semiconductor substrate 40 by the CVD method. Thus, the structure shown in FIG. 3A can be obtained. After forming the insulating layer 50 made of BPSG, for example, 900 ° C. × 20 minutes in a nitrogen gas atmosphere.
It is preferable to reflow the insulating layer 50. Furthermore,
If necessary, for example, a chemical mechanical polishing method (CMP method)
To planarize the insulating layer 50 by chemically and mechanically polishing the top surface of the insulating layer 50, or to etch the insulating layer 5 by an etch back method.
It is desirable to flatten 0. The film forming conditions of the insulating layer 50 are illustrated below. Gas used: SiH ₄ / PH ₃ / B ₂ H ₆ Film formation temperature: 400 ° C Reaction pressure: Normal pressure

[Step-220] Next, on the insulating layer 50,
A lower electrode layer 52 corresponding to the base is formed. That is, the lower electrode layer 52 made of Pt is deposited on the insulating layer 50 by the RF magnetron sputtering method. The thickness of the lower electrode layer 52 was set to 0.1 to 0.2 μm (see FIG. 3B).
After that, the lower electrode layer 52 is patterned into a desired shape by using, for example, an ion milling technique. The RF magnetron sputtering conditions are exemplified below. Anode voltage: 2.6 kV Input power: 1.1 to 1.6 W / cm ² Process gas: Ar / O ₂ = 90/10 Pressure: 0.7 Pa Film forming temperature: 600 to 750 ° C Deposition rate: 5 to 10 mm / Min

[Step-230] After that, an oxide film containing bismuth as a constituent element is formed as a substrate by the MOCVD method using triphenylbismuth whose meta position is substituted with an alkyl group which may be substituted with halogen as a source gas. A film is formed on top. Specifically, the lower electrode layer 52 corresponding to the substrate is formed by the MOCVD method using tris (m-methylphenyl) bismuth as a source gas under the same conditions as the oxide film forming method described in the first embodiment. A ferroelectric layer 53 made of Bi ₂ SrTa ₂ O ₉ of bismuth layer structure perovskite type is formed thereon (see FIG. 3C). The ferroelectric layer 53 made of bismuth titanate may be formed by the same method as in [Step-320] described later.

[Step-240] After that, the ferroelectric layer 53
An upper electrode layer 54 is formed on top. The upper electrode layer 54 is Pt
And can be formed by the same method as in [Step-220].

[Step-250] Next, the upper electrode layer 54 made of Pt is patterned into a desired shape by using, for example, an ion milling technique, and further, the ferroelectric layer 5 is formed by RIE.
3 is patterned. Thus, the capacitor structure shown in FIG. 4A can be obtained.

[Step-260] Next, for example, BPSG is formed on the insulating layer 50, the lower electrode layer 52 and the upper electrode layer 54.
An upper insulating layer 60 of is formed. The upper insulating layer 6
After forming 0, the upper insulating layer 60 is preferably flattened. Then, the opening 61 is formed in the insulating layer 50 and the upper insulating layer 60 above the one source / drain region 44 by using the photolithography technique and the etching technique. Further, openings 62 and 63 are formed in the upper insulating layer 60 above the lower electrode layer 52 and above the upper electrode layer 54 (see FIG. 4B).

[Step-270] Then, for example, Ti is formed on the upper insulating layer 60 including the insides of the openings 61, 62, 63.
Layer and TiN layer are formed by, for example, a sputtering method, and then T
Aluminum-based alloy (for example, Al-1% S on the iN layer)
The wiring material layer 64 made of i) is formed by the so-called high temperature aluminum sputtering method (see FIG. 5). The film forming conditions for the Ti layer, the TiN layer, and the wiring material layer made of an aluminum alloy are illustrated below. The reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, to prevent the semiconductor substrate 40 from being damaged by the wiring material layer made of an aluminum alloy, and to improve the wettability of the aluminum alloy. is there. Ti layer (thickness: 20 nm) Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Substrate heating: None TiN layer (thickness: 100 nm) Process gas: N ₂ / Ar = 100/35 sccm Pressure: 1 0.0Pa RF power: 6kW Substrate heating: None Wiring material layer made of aluminum alloy Process gas: Ar = 100sccm Pressure: 0.26Pa RF power: 15kW Substrate heating temperature: 475 ° C

Thus, in the openings 61, 62, 63,
Aluminum-based alloy embedded, contact plug 6
5, 66, 67 are formed (see FIG. 5). Also, FIG.
Also, in FIG. 5, the TiN layer and the Ti layer are not shown. After that, the wiring material layer 64 on the upper insulating layer 60,
By patterning the TiN layer and the Ti layer, the first wiring layer 6
8, the second wiring layer 69 is formed (see FIG. 2A).

The film formation of the wiring material layer made of an aluminum alloy was carried out by the so-called high temperature aluminum sputtering method, but it is not limited to such a film forming method, and the so-called high temperature reflow method or high pressure reflow method. It can also be done at. In the high temperature reflow method, a wiring material layer made of an aluminum alloy is used as the upper insulating layer 6 under the conditions exemplified below.
0 deposit. Process gas: Ar = 100 sccm DC power: 20 kW Sputtering pressure: 0.4 Pa Substrate heating temperature: 150 ° C.

After that, the semiconductor substrate 40 is heated to about 500.degree. As a result, the wiring material layer made of an aluminum-based alloy deposited on the upper insulating layer 60 is brought into a fluid state, flows into the openings 61, 62, 63, and the opening 6
1, 62 and 63 are surely filled with an aluminum alloy to form contact plugs 65, 66 and 67.
On the other hand, a wiring material layer made of an aluminum alloy is left on the upper insulating layer 60. The heating conditions can be set as follows, for example. Heating method: Substrate backside gas heating Heating temperature: 500 ° C Heating time: 2 minutes Process gas: Ar = 100 sccm Process gas pressure: 1.1 × 10 ³ Pa

Here, the substrate backside gas heating method is to heat a heater block arranged on the backside of the semiconductor substrate 40 to a predetermined temperature (heating temperature), and apply process gas between the heater block and the backside of the semiconductor substrate 40. This is a method of heating the semiconductor substrate 40 by introducing it. As the heating method, other than this method, a lamp heating method or the like can be used.

A high pressure reflow method can be used instead of the high temperature reflow method. In this case, the reflow process is performed under the conditions exemplified below. Substrate heating temperature: 400 ° C Heating time: 2 minutes Heating atmosphere: Argon gas Atmospheric pressure: 10 ⁶ Pa or more

In the second embodiment, instead of the lower electrode layer made of Pt, for example, La-Sr-Co-O (LSCO) having a perovskite structure is used alone or two layers of LSCO / Pt from the bottom are used. You can also L by the pulse laser ablation method in this case
The film forming conditions of SCO are illustrated below. Target: LSCO Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

(Embodiment 3) In a non-volatile memory cell of the type which detects a change in the amount of charge stored in a ferroelectric capacitor, how much the remanent polarization ± P _r of the ferroelectric layer is increased and the remanent polarization ± Maintaining P _r in a high state is a very important technical issue. By increasing the remanent polarization ± P _r of the ferroelectric layer, it is possible to more easily and surely detect which data, "0" or "1", the semiconductor memory cell holds. become. For that purpose, it is necessary to epitaxially grow the ferroelectric layer on the lower electrode layer.

When the lower electrode layer 52 is composed of Pt (100), the lattice plane spacing of Pt (100) is, for example, P
ZT, PLZT or Bi ₂ SrTa ₂ O ₉ , Bi ₄ Sr
It matches the lattice spacing of Ti ₄ O ₁₅ and Bi ₂ SrTi ₂ O ₉ . Therefore, these ferroelectric materials can be epitaxially grown on Pt (100),
It is possible to increase the remanent polarization ± P _r of these ferroelectric layers formed on (100). However,
Pt (100) cannot be formed on the insulating layer 50 made of an amorphous material such as PBSG. Therefore,
There is a problem that the remanent polarization ± P _r of these ferroelectric layers cannot be increased.

For example, the reference "Ferroelectric La-Sr-Co-O"
/ Pb-Zr-Ti-O / La-Sr-Co-O heterostructure on silicon
via template growth ", R. Ramesh, et al., Appl. Phy
s. Lett. 63 (26), 27 December 1993, pp. 3592-3594
(Hereinafter referred to as Reference 2), reference "Template Approaches"
to Growth of Oriented Oxide Heterostructures on SiO
₂ / Si ", Journal Of Electronic Materials, Vol. 23, N
o. 1, 1994, pp. 19-23 (hereinafter referred to as reference 3),
Yttrium (Y) -added stabilized zirconia (hereinafter abbreviated as YSZ) on a silicon substrate or SiO ₂ formed on the silicon substrate, and bismuth titanate (BTO) having a perovskite structure oriented along the c-axis. )
Disclosed is a ferroelectric capacitor composed of a template layer made of, a lower electrode layer made of La-Sr-Co-O (LSCO) having a perovskite structure, a ferroelectric layer made of PLZT, and an upper electrode layer made of LSCO. ing. When the template layer made of BTO is not provided, that is, LSCO / directly on YSZ or SiO _2.
When PLZT / LSCO is formed, LSCO / PLZ
T / LSCO has a [110] orientation, and in this state P
LZT exhibits low remanent polarization. However, when a template layer made of BTO is formed, LSCO / PL
ZT / LSCO has a [001] orientation, and in this state PLZT exhibits a high remanent polarization.

The resistivity of LSCO, which is the material forming the lower electrode shown in Documents 2 and 3, is as high as 90 to 200 μΩcm at room temperature, and a material having a resistivity as low as possible, for example, Pt. It is preferable to form the lower electrode from {100}. The lattice constant of BTO is
a = 5.41 angstrom, b = 5.43 angstrom, and c = 32.82 angstrom. Further, platinum Pt has a face-centered cubic structure, and the lattice constant is a =
b = c = 3.92 angstrom. That is, BT
The (110) lattice spacing of O is almost equal to the lattice spacing of Pt {100}. Therefore, P is formed on the template layer (hereinafter referred to as a buffer layer) made of BTO oriented in the c-axis.
If a lower electrode layer made of t is formed, the lower electrode layer is Pt.
It may be composed of {100}.

Further, PZ having a perovskite structure
The lattice constant of T is a = b = 3.93 angstrom. That is, the lattice plane spacing of Pt {100} substantially matches the lattice plane spacing of, for example, the (100) plane of PZT. On the other hand, the a-axis and b-axis lattice constants of the bismuth layered perovskite type ferroelectric material (unit: angstrom)
The (110) lattice spacing (unit: angstrom) is illustrated below. Ferroelectric material name Lattice constant Lattice spacing Bi ₂ SrTa ₂ O ₉ 5.512 3.898 Bi ₂ SrNb ₂ O ₉ 5.500 3.889 Bi ₂ BaTa ₂ O ₉ 5.556 3.929 Bi ₄ SrTi ₄ O ₁₅ 5.420 3.833

Generally, if the difference between the lattice plane spacing of the lower electrode layer made of Pt {100} and the lattice plane spacing of the material forming the ferroelectric layer is within 3%, the ferroelectric layer is formed on the lower electrode layer. Can be epitaxially grown. Therefore, P
A ferroelectric layer made of a PZT compound or a bismuth layer structure perovskite type ferroelectric material can be epitaxially grown on the lower electrode layer made of t {100}. As a result, a high remanent polarization ± P _r can be imparted to the ferroelectric layer formed on the lower electrode layer, and a semiconductor element having excellent performance can be manufactured.

The resistivity of platinum is 15 to 20 μΩc.
m, which has a lower resistance than LSCO, and is a preferable material for semiconductor devices.

In the semiconductor device described in Example 2, the lower electrode layer 52 made of Pt was formed on the insulating layer 50. On the other hand, in the third embodiment, the semiconductor device has a capacitor structure in which the lower electrode layer 52, the bismuth layer structure perovskite type ferroelectric layer 53 and the upper electrode layer 54 are stacked, and the lower electrode layer 52. And a bismuth layered structure perovskite type buffer layer 51 formed in the above. The buffer layer 51 is composed of an oxide film containing bismuth as a constituent element. A schematic partial cross-sectional view of a semiconductor device manufactured by the method for manufacturing a semiconductor device of Example 3 is shown in FIG.

In the capacitor structure of the semiconductor device of the third embodiment, more specifically, the buffer layer 51 is made of BPS.
It is formed on the insulating layer 50 made of G (corresponding to the base). The buffer layer 51 is composed of a bismuth layer structure perovskite type Bi ₄ Ti ₃ O ₁₂ (BTO) oriented in the c-axis. Further, the lower electrode layer 52 made of Pt {100}
Are formed on the buffer layer 51. In addition, the ferroelectric layer 53 formed on the lower electrode layer 52 by epitaxial growth also has the Bi ₂ SrTa ₂ O ₉ layer in the third embodiment.
Consists of. Furthermore, the upper electrode layer 5 made of Pt {100}
4 is formed on the ferroelectric layer 53. Except for these points, the structure of the semiconductor device of Example 3 is substantially the same as the structure of the semiconductor device of Example 2. A method for manufacturing a semiconductor device of Example 3 will be described below with reference to FIGS. 6 and 7 which are schematic partial cross-sectional views of a semiconductor substrate and the like.

[Step-300] First, as in the case of [Step-200] of the second embodiment, a semiconductor substrate 40 made of a silicon semiconductor substrate is formed on a semiconductor substrate 40 by a known method.
A gate oxide film 42, a gate electrode 43, source / drain regions 44 and 45, and a channel region 46 are formed.

[Step-310] Next, as in [Step-210] of the second embodiment, the insulating layer 50 made of an amorphous material is formed on the semiconductor substrate 40. That is, for example, an insulating layer 50 (corresponding to a substrate) made of BPSG which is an amorphous material is deposited on the entire surface by, for example, the CVD method.
Thus, the structure shown in FIG. 6A can be obtained.

[Step-320] Next, the buffer layer 51, which is an oxide film, is formed on the insulating layer 50 corresponding to the base. That is, an oxide film containing bismuth as a constituent element is formed on a substrate by the MOCVD method using triphenylbismuth whose meta position is substituted with an alkyl group which may be substituted with halogen as a source gas. Specifically, according to the oxide film forming method described below, bismuth titanate Bi ₄ Ti _{3 is used.}
A buffer layer 51 made of O ₁₂ and having a high orientation (that is, oriented in the c-axis) is formed on the insulating layer 50 corresponding to the substrate (see FIG. 6B). The thickness of the buffer layer 51 was 0.01 to 0.02 μm.

As shown in FIG. 1, when forming the buffer layer 51, tris (m-methylphenyl) bismuth is filled in the raw material container 10 and the tris (m-
Heat the methylphenyl) bismuth to about 100 ° C.
Argon gas having a flow rate of 50 cc is introduced into the raw material container 10 and bubbling of tris (m-methylphenyl) bismuth which is liquid under heating and reduced pressure. And about 14
The vaporized tris (m-methylphenyl) bismuth was introduced into the pipe 14 kept at 0 ° C., and the MOCVD reaction chamber 2
Send to 0.

On the other hand, tetraisopropoxy titanium is filled in the raw material container 12, and the tetraisopropoxy titanium in the raw material container 12 is heated to about 40 ° C. Argon gas having a flow rate of 50 cc is introduced into the raw material container 12, and tetraisopropoxytitanium, which is liquid under heating and reduced pressure, is bubbled. Then, vaporized tetraisopropoxy titanium is introduced into the pipe 15 kept at about 80 ° C.
To the MOCVD reaction chamber 20 via.

The substrate 30 placed on the substrate stage in the MOCVD reaction chamber 20 is heated to about 700 ° C.
When gaseous tris (m-methylphenyl) bismuth, gaseous tetraisopropoxytitanium gas, oxygen gas and diluting argon gas are introduced into the VD reaction chamber 20,
An oxide film made of bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ) is formed on the substrate 30. That is, it is made of bismuth titanate (Bi ₄ Ti ₃ O ₁₂ ) and has a high orientation (that is,
A buffer layer 51 (oriented to the c-axis) can be deposited on the insulating layer 50 corresponding to the substrate.

The buffer layer 51 may be made of Bi ₂ SrTa ₂ O ₉ formed by the same method as in Example 1.

[Step-330] After that, the buffer layer 51
A lower electrode layer 52 is formed on top. That is, the buffer layer 51
A lower electrode layer 52 made of Pt and having a high orientation is deposited thereon by RF magnetron sputtering. The thickness of the lower electrode layer 52 was set to 0.1 to 0.2 μm. The RF magnetron sputtering conditions can be the same as in [Step-220] of the second embodiment. The lower electrode layer 52 made of Pt has a {100} plane. In other words, the {100} plane of platinum Pt forming the lower electrode layer 52 is formed parallel to the surface of the buffer layer 51.

Thereafter, the lower electrode layer 52 is patterned into a desired shape by using, for example, an ion milling technique, and further, the buffer layer 51 which is an oxide film made of BTO is patterned into a desired shape by, for example, the RIE method ( Figure 6
(See (C)).

The lower electrode layer made of Pt {100} can be formed by the pulse laser deposition method. The film forming conditions of Pt {100} by the pulse laser deposition method are illustrated below. Film forming conditions by pulsed laser deposition method Target: Pt Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz, 1.1 J / cm ² ) Film formation temperature: 500 to 600 ° C

[Step-340] Next, the lower electrode layer 52.
A ferroelectric layer 53 made of Bi ₂ SrTa ₂ O ₉ is epitaxially grown thereon by the same method as in the first embodiment.
The orientation of the ferroelectric layer 53 made of Bi ₂ SrTa ₂ O ₉ epitaxially grown on the surface of the lower electrode layer 52 is [110].

In the same manner as in [Step-320], the bismuth layer structure perovskite type is formed on the lower electrode layer 52 corresponding to the substrate by the MOCVD method using tris (m-methylphenyl) bismuth as a source gas. Bi ₄ Ti ₃ O
It is also possible to deposit a ferroelectric layer made of ₁₂ (BTO).

Further, the ferroelectric layer made of PZT can be epitaxially grown on the lower electrode layer 52 by the magnetron sputtering method. The film forming conditions are exemplified below. The ferroelectric layer made of PZT has a (100) plane. In other words, the orientation of the ferroelectric layer of epitaxially grown PZT with respect to the surface of the lower electrode layer 52 is [100]. If the target is replaced with PLZT, the ferroelectric layer made of PLZT is replaced with the lower electrode layer 52.
It can be epitaxially grown on. Target: PZT process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Film formation temperature: 500 ° C Thickness of ferroelectric layer: 0.1-0.3 μm

Alternatively, the ferroelectric layer made of PZT or PLZT can be formed by the pulse laser ablation method. The film forming conditions in this case are exemplified below. Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

Alternatively, the ferroelectric layer is made of Bi ₂ SrTa ₂
It can also be formed of O ₉ and formed by a pulse laser ablation method. The film forming conditions for the ferroelectric layer made of Bi ₂ SrTa ₂ O ₉ will be illustrated below. In addition, Bi ₂ SrT
After the a ₂ O ₉ film is formed, it is desirable to perform post baking in an oxygen atmosphere at 800 ° C. for 1 hour. Target: Bi ₂ SrTa ₂ O ₉ Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25nsec, 5Hz) Film formation temperature: 500 ° C Oxygen concentration: 3Pa

[Step-350] Then, the ferroelectric layer 53.
An upper electrode layer 54 is formed on top. The upper electrode layer 54 is Pt
It is made of {100} and can be formed by the same method as in [Step-220] of the second embodiment.

[Step-360] Next, the upper electrode layer 54 made of Pt is patterned into a desired shape by using, for example, an ion milling technique, and further, the ferroelectric layer 53 is formed by RIE.
Pattern. Thus, the capacitor structure of the semiconductor device having the structure shown in FIG. 7A can be obtained.

[Step-370] Next, through the steps similar to [Step-260] and [Step-270] of Example 2,
A semiconductor device having the structure shown in FIG. 7B can be manufactured.

In the third embodiment, the substrate is replaced by the insulating layer 5
Instead of being composed of 0, for example, yttrium oxide Y
It can also be composed of an underlayer made of stabilized zirconia (YSZ) which is zirconium oxide ZrO ₂ added with ₂ O ₃ . Such an underlayer can be formed by, for example, the MOCVD method or the pulse laser deposition method whose film forming conditions are exemplified below. In this case, before forming the base layer made of stabilized zirconia, an interlayer insulating layer made of, for example, SiO ₂ is formed on the select transistor. Deposition conditions source material by _{MOCVD: Zr (C 4 H 9 O} ) 4 Y (C 11 H 19 O 2) 3 deposition temperature: 550 to 650 ° C deposition pressure: 27～400Pa oxygen concentration: 50% Pulse Film forming conditions by laser deposition method Target: ZrO ₂ / Y Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz, 1.1 J / cm ² ) Film formation temperature: 500 ° C Oxygen concentration: 3 Pa

Example 4 Example 4 is an MOCVD method using triphenylbismuth substituted in the meta position with an alkyl group which may be substituted with halogen as a source gas, and an oxide containing bismuth as a constituent element. The present invention relates to a method for forming a superconductor thin film, which comprises forming a superconductor thin film made of a film on a substrate. The oxide film is of Bi-Sr-Ca-Cu-O system.

In the fourth embodiment, the MOCVD apparatus described in the first embodiment is used and Si (100) is used as the substrate. Raw material gases in the MOCVD method are shown below. Bi source: tris (m-methylphenyl) bismuth Sr source: Sr (C ₁₁ H ₁₉ O ₂ ) ₂ [Sr (tmh
d) ₂ ] Ca source: Ca (C ₁₁ H ₁₉ O ₂ ) ₂ [Ca (tmh
d) ₂ ] Cu source: Cu (C ₅ H ₇ O ₂ ) ₂ [Cu (acac) ₂ ]

Each raw material is heated to a proper temperature in the raw material container, placed on the substrate stage 22 in the MOCVD reaction chamber 20 and heated to a proper temperature on the substrate 30 made of Si (100). By introducing the Ar carrier gas, the oxygen gas, and the above-mentioned source gases, a superconductor thin film made of a Bi—Sr—Ca—Cu—O-based oxide film can be formed on the substrate 30.

For reference, the outline of the method for synthesizing tris (m-methylphenyl) bismuth will be described below.

First, the well-dried metallic magnesium was mixed with 5
With heating at 0 to 60 ° C, m-chlorotoluene dissolved in tetrahydrofuran (THF) is added dropwise to metallic magnesium to produce m-magnesium toluene. Next, BiCl ₃ dissolved in THF was cooled with m-.
Add dropwise to magnesium toluene and heat to reflux. Then, a saturated NH ₄ Cl aqueous solution is added dropwise, decantation is performed, and dehydration is performed using anhydrous MgSO ₄ . Then, vacuum distillation is performed to obtain tris (m-methylphenyl) bismuth. In addition, 2-chloro-4-methyltoluene is m-
If used in place of chlorotoluene, tris (3,5-
Dimethylphenyl) bismuth can be synthesized.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments. The structure of the semiconductor device described in the method for manufacturing a semiconductor device of the present invention is an example, and the design can be changed as appropriate.

For example, the upper electrode layer may also serve as a plate line. That is, in the capacitor structure of the semiconductor device having such a structure, after forming the ferroelectric layer 53 in [Process-230] of the second embodiment, the ferroelectric layer 53 is patterned into a desired shape.
Next, after forming the upper insulating layer 60 on the entire surface, the insulating layer 5 is formed.
0 and the upper insulating layer 60, an opening 61 is formed, and an opening 62 is formed in the upper insulating layer 60 above the lower electrode layer 52. Next, the upper insulating layer 60 including the inside of the openings 61 and 62
A Ti material layer, a TiN layer, and a wiring material layer 64 made of an aluminum-based alloy are sequentially formed thereon. Then, the wiring material layer 64, the TiN layer, and the Ti layer on the upper insulating layer 60 are patterned to form a first wiring layer 68 made of a wiring material layer made of an aluminum alloy ((A in FIG. 8). )reference). After that, the second insulating layer 70 made of, for example, BPSG is formed on the entire surface. Then, an opening 71 is formed in the upper insulating layer 60 and the second insulating layer 70 above the ferroelectric layer 53, and then, as in [Step-240] of the second embodiment, the opening 71 including the inside of the opening 71 is formed. A Pt film is formed on the second insulating layer 70. After that, the Pt film is left in the opening 71, and the Pt film on the second insulating layer 70 is patterned. As a result, the upper electrode layer 54 made of Pt is formed on the ferroelectric layer 53.
A is formed. Moreover, the upper electrode layer 54A extends over the second insulating layer 70 through the opening 71 to form the second wiring layer 69A and also functions as a plate line (see FIG. 8B). . The upper electrode layer 54A and the second wiring layer 69A may be made of an aluminum alloy.

Element isolation region 41 having LOCOS structure
Alternatively, the element isolation region may have a trench structure. The gate electrode 43 and the bit line may be made of polycide or metal silicide instead of being made of a polysilicon layer. As an insulating layer, instead of BPSG, SiO ₂ , PSG, BSG, AsSG, PbS
G, SbSG, SOG, SiON, SiN, NSG, L
A known insulating material such as TO or a laminated material of these insulating materials can be given. The insulating layer may be smoothed by, for example, a resist etch back method. The ferroelectric layer may have a structure in which a plurality of ferroelectric materials are laminated.

In the [process-260] of the second embodiment and the [process-370] of the third embodiment, the contact plug 65 is formed by embedding an aluminum-based alloy in the openings 61 formed in the insulating layer 50 and the upper insulating layer 60. Instead of forming the contact plug 65A, the contact plug 65A can be formed by a so-called blanket tungsten CVD method. For that purpose, after forming the openings 61 in the insulating layer 50 and the upper insulating layer 60, Ti is formed in the same manner as in [Step-260] of the second embodiment.
The layer and the TiN layer are formed by the sputtering method. Then Ti
A wiring material layer 64A made of tungsten is formed on the N layer,
It is deposited by the CVD method under the conditions exemplified below (see FIG. 9A). Gas used: WF ₆ / H ₂ / Ar = 40/400/2250
sccm pressure: 10.7kPa film formation temperature: 450 ° C

After that, the wiring material layer 64A made of tungsten, the TiN layer and the Ti layer on the insulating layer 50 are removed by etching (see FIG. 9B). The etching conditions can be set as follows, for example. First stage etching: Etching of tungsten layer Gas used: SF ₆ / Ar / He = 110/90 / 5scc
m pressure: 46 Pa RF power: 275 W Second stage etching: TiN layer / Ti layer etching Working gas: Ar / Cl ₂ = 75/5 sccm Pressure: 6.5 Pa RF power: 250 W

In this way, the contact plug 65A in which tungsten is embedded in the opening 61 is formed. After that, openings 62 and 63 are formed in the upper insulating layer 60 above the lower electrode layer 52 and above the upper electrode layer 54, and then a Ti layer and a T layer are formed in the same manner as in [Step-260] of the second embodiment.
After the iN layer and the wiring material layer 64 made of an aluminum alloy are formed by the sputtering method, these layers are patterned to form the first wiring layer 68 and the second wiring layer 69 (see FIG. 10).

The contact plug 6 is formed by filling the opening 61 with polysilicon doped with impurities.
5 may be formed. Further, the top surface of the contact plug 65 may be substantially in the same plane as the surface of the insulating layer 50, or the top surface of the contact plug 65 may be projected or recessed from the surface of the insulating layer 50. . Alternatively,
The top of the contact plug 65 may extend on the upper insulating layer 60. In this case, the polysilicon layer or the wiring material layer 64A and the TiN layer are formed by photolithography so that the polysilicon layer or the wiring material layer 64A made of tungsten remains on the upper insulating layer 60 near the opening 61. The layer / Ti layer may be etched.

Alternatively, the insulating layer 50 and the upper insulating layer 6
An opening 61 is formed at 0, and an opening 62 is formed in the upper insulating layer 60 above the lower electrode layer 52. Then the opening 6
1, 62 on the upper insulating layer 60 including the inside,
A wiring material layer 64A made of a TiN layer and tungsten is formed. Then, the wiring material layer 64A made of tungsten, the TiN layer, and the Ti layer on the upper insulating layer 60 are patterned to form the first wiring layer 6 made of the wiring material layer 64A and the like.
8A is formed and, in addition, contact plugs 65A and 66 are formed.
A may be formed. After that, an opening 63 is formed in the upper insulating layer 60 above the upper electrode layer 54, and then a wiring material layer made of a Ti layer, a TiN layer, and an aluminum-based alloy as in [Step-260] of the second embodiment. Is formed by sputtering, and then these layers are patterned in order to form the second wiring layer 69. In this way, the structure shown in FIG. 11 can be obtained.

Further, after the contact plug 65A is formed on the insulating layer 50 by, for example, the blanket tungsten CVD method, the contact plug 65A is formed on the insulating layer 50 by the same method as in [Step-220] of the second embodiment. The connected lower electrode layer 52 may be formed. Then, Example 2
[Process-230], [Process-240], and [Process-25]
0] is executed. Next, the insulating layer 50 and the upper electrode layer 5
An upper insulating layer 60 made of, for example, BPSG is formed on the upper surface of the insulating layer 4. Then, the upper insulating layer 6 above the upper electrode layer 54.
After forming the opening at 0, [Process-270] of Example 2
A contact plug 67 is formed in the opening and a wiring layer 69B is formed on the upper insulating layer 60 by the same method as described above. Thus, the semiconductor device having the structure shown in FIG. 12 can be obtained.

Examples of aluminum alloys include pure aluminum, Al-Si, Al-Cu, and Al-Si-C.
It can be composed of various aluminum alloys such as u, Al-Ge and Al-Si-Ge. Alternatively, instead of the aluminum alloy, polysilicon, titanium, titanium alloy, copper, copper alloy, tungsten, or tungsten alloy can be used to form the first or second wiring layer. In the embodiment, the base of the contact plug has a two-layer structure of Ti / TiN.
It is also possible to have a single layer structure of N. The contact plug can also be made of TiW, TiNW, WSi ₂ , MoSi _2, or the like.

Further, instead of the ferroelectric layer electrically connected to one source / drain region via the contact plug and the first wiring layer, it is electrically connected to one source / drain region. A wiring electrically connected to the contact plug is provided, another connection hole (for example, a via hole) electrically connected to the wiring is formed, and the ferroelectric layer is electrically connected to the connection hole. It may be connected. Alternatively, a capacitor structure in a semiconductor device can be formed by forming a lower electrode layer or a buffer layer on the element isolation region. In this case, the element isolation region corresponds to the base.

The bit line can be formed, for example, by the following method. That is, a lower insulating layer is formed between [Step-200] and [Step-210] of Example 2,
An opening is formed in the lower insulating layer above the other source / drain region 45 by using a photolithography technique and an etching technique. Then, a polysilicon layer is deposited on the lower insulating layer including the inside of the opening by, for example, the CVD method.
As a result, a bit contact portion in which polysilicon is embedded in the opening is formed. Then, the polysilicon layer on the lower insulating layer is patterned. Thus, a bit line made of polysilicon electrically connected to the other source / drain region 45 via the bit contact portion is formed. After that, the insulating layer 50 is formed on the lower insulating layer including the bit line. The procedure for forming the bit line is arbitrary. For example, the bit line can be formed after forming the second wiring layer.

From the semiconductor device, not only the non-volatile memory cell using the ferroelectric thin film (so-called FERAM) but also D
A RAM can also be configured. In this case, only the polarization of the ferroelectric thin film is used. That is, the characteristic that the difference (P _max −P _r ) between the maximum (saturation) polarization P _{max due} to the external electrode and the remnant polarization P _r when the external electrode is 0 has a constant proportional relationship with the power supply voltage is used. To do. The polarization state of the ferroelectric thin film is always between the saturation polarization (P _max ) and the remanent polarization (P _r ) and is not inverted. Data is retained by refresh.

[0093]

INDUSTRIAL APPLICABILITY In the present invention, since triphenylbismuth whose meta position is substituted with an alkyl group which may be substituted with halogen is used as a source gas in the MOCVD method, compared with conventional triphenylbismuth, A vapor pressure equal to or higher than that of triphenylbismuth can be obtained at a lower temperature, and the vaporization temperature for obtaining the source gas can be set to a lower temperature. Therefore, MO
In the CVD method, the raw material container 1 in the MOCVD apparatus
The heating temperature of 0 can be set to a low temperature, and the raw material container 1
It is possible to reduce decomposition of the raw material within 0 due to heating for a long time, and the reproducibility of the oxide film formation is improved.
Further, since the heating temperature of the raw material container 10 and the heating temperature of the pipe 14 can be lowered, the temperature control in the MOCVD apparatus becomes easy and the MOCVD apparatus can be maintained easily.

In the method of manufacturing a semiconductor device of the present invention, if the lower electrode layer is made of Pt {100}, the lattice spacing of the lower electrode layer is such that the PZT-based compound having a perovskite type structure or the bismuth layer structure. It is almost equal to the lattice spacing of the perovskite type ferroelectric material. Therefore, since the ferroelectric layer can be epitaxially grown on the lower electrode layer, a high remanent polarization ± P _r can be imparted to the ferroelectric layer formed on the lower electrode layer.
A semiconductor element having excellent operating performance can be manufactured. On the other hand, if a lower electrode layer made of Pt {100} is formed on a so-called Y1 material system represented by Bi ₂ AB ₂ O ₉ or a bismuth layer structure perovskite type buffer layer such as bismuth titanate, (11
0) Since the lattice plane spacing is substantially equal to the lattice plane spacing of Pt {100}, it is possible to form a lower electrode layer having high orientation on the buffer layer. The resistivity of platinum is L
It has a resistance of 15 to 20 μΩcm, which is lower than that of SCO, and is a preferable material for use in a semiconductor device.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an MOCVD apparatus suitable for carrying out the method of the present invention.

2A and 2B are a schematic partial cross-sectional view and an equivalent circuit diagram of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to a second embodiment.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor device according to a second embodiment.

FIG. 4 is a schematic partial cross-sectional view of the semiconductor substrate etc. for explaining the method for manufacturing the semiconductor device of the second embodiment, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining the manufacturing method of the semiconductor device according to the second embodiment, following FIG. 4;

FIG. 6 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a method for manufacturing a semiconductor device according to a third embodiment.

FIG. 7 is a schematic partial cross-sectional view of the semiconductor substrate etc. for explaining the method for manufacturing the semiconductor device of the third embodiment, following FIG. 6;

FIG. 8 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a modified method for manufacturing a semiconductor device of the present invention.

FIG. 9 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a modified method of manufacturing a semiconductor device of the present invention.

FIG. 10 is a schematic partial cross-sectional view of the semiconductor substrate or the like for explaining the manufacturing method of the modified semiconductor device of the present invention, following FIG. 9;

FIG. 11 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a modified method of manufacturing a semiconductor device of the present invention.

FIG. 12 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a modified method for manufacturing a semiconductor device of the present invention.

FIG. 13 is a PE hysteresis loop diagram of a ferroelectric substance.

[Explanation of symbols]

 10, 12 Raw material container 11, 13 Constant temperature bath 14, 15 Piping 20 MOCVD reaction chamber 22 Substrate stage 30 Substrate 40 Semiconductor substrate 41 Element isolation region 42 Gate oxide film 43 Gate electrode 44, 45 Source / drain region 46 Channel region 50 Insulation layer 51 buffer layer 52 lower electrode layer 53 ferroelectric layer 54, 54A upper electrode layer 60 upper insulating layer 61, 62, 63, 71 opening 64, 64A wiring material layer 65, 65A, 66, 66A, 67 contact plug 68, 68A First wiring layer 69, 69A Second wiring layer 70 Second insulating layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location C30B 29/22 501 7202-4G C30B 29/22 501E H01L 39/24 ZAA H01L 39/24 ZAAB

Claims (12)

[Claims] 1. An oxide film containing bismuth as a constituent element is obtained by a metalorganic chemical vapor deposition method using triphenylbismuth substituted at a meta position with an alkyl group which may be substituted with halogen as a source gas. A method for forming an oxide film, which comprises forming a film. 2. The oxide film according to claim 1, wherein the triphenylbismuth substituted at the meta position with an alkyl group which may be substituted with halogen is tris (m-methylphenyl) bismuth. Deposition method. 3. An oxide film containing bismuth as a constituent element is obtained by a metal organic chemical vapor deposition method using triphenylbismuth substituted in the meta position with an alkyl group which may be substituted with halogen as a source gas. A method of manufacturing a semiconductor device, which comprises forming a film on a substrate. 4. A semiconductor device has a capacitor structure in which a lower electrode layer, a bismuth layer structure perovskite type ferroelectric layer and an upper electrode layer are laminated, and the ferroelectric layer is composed of the oxide film. The method for manufacturing a semiconductor device according to claim 3, wherein 5. A semiconductor device comprising a capacitor structure in which a lower electrode layer, a bismuth layered structure perovskite type ferroelectric layer and an upper electrode layer are stacked, and a bismuth layered structure perovskite type formed below the lower electrode layer. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the buffer layer is formed of the oxide film. 6. The triphenylbismuth substituted at the meta position with an alkyl group which may be substituted with halogen comprises tris (m-methylphenyl) bismuth. 2. A method of manufacturing a semiconductor device according to item 1. 7. The oxide film is formed of Bi ₂ AB ₂ O ₉ (where A 2
Is an element selected from the group consisting of Sr, Ba and Ca, and B is 1 selected from the group consisting of Ta and Nb.
7. The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor device is a seed element). 8. An oxide film containing bismuth as a constituent element in metalorganic chemical vapor deposition is 1.0 × 10 ²
The method for manufacturing a semiconductor device according to claim 7, wherein the method is performed under a pressure of Pa to 1.4 × 10 ³ Pa. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the oxide film is made of Bi ₂ SrTa ₂ O ₉ . 10. An organic metal chemical vapor deposition method using triphenylbismuth substituted in the meta position with an alkyl group which may be substituted with halogen as a source gas, and from an oxide film containing bismuth as a constituent element. A method for forming a superconductor thin film, comprising: forming a superconductor thin film on a substrate. 11. The superconductor according to claim 10, wherein the triphenylbismuth substituted in the meta position with an alkyl group which may be substituted with halogen is tris (m-methylphenyl) bismuth. Thin film forming method. 12. The superconductor thin film is made of Bi-Sr-Ca-C.
It is u-O type | system | group, The film-forming method of the superconductor thin film of Claim 10 or Claim 11 characterized by the above-mentioned.