JPH08328758A - Disk array device - Google Patents

Abstract

PURPOSE: To provide a more highly reliable disk array device. CONSTITUTION: This disk array device 1 is provided with five disks 4a 4e and two disk array controllers 3a and 3b. Data transferred from a host computer 2 to one of the disk array controllers are transferred through an inter-controller interface 7 to the other disk array controller and multiplexed and stored tentatively in the disk caches 11a and 11b of both disk array controllers 3a and 3b. When a fault is generated in one of the disk array controllers, the data stored in the disk cache of the other disk array controller are written back to the disks 4a-4e.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk array device equipped with a disk array controller for controlling data input / output between a host computer and a plurality of disks.

[0002]

2. Description of the Related Art In order to construct a highly reliable client / server system, a core file server is required to have high performance. At the same time, high performance is required for an external storage device of a file server such as a magnetic disk device that holds data. This is because the performance of the storage device often becomes a bottleneck in improving the performance of the entire system.

In order to improve the performance of the storage device, U.S.A. C. RAID (Redundant Arra) by Patternson of Berkeley
There has been proposed a disk array device including a plurality of disk array devices called y of Inexpensive Disks. By providing a disk array controller that can access multiple disk devices at the same time, it is possible to simultaneously perform data write-back processing and data read processing for multiple disk devices. This is intended to speed up output. For example, from the host computer
When the write back of data to the disk device is instructed, the disk array controller divides the data transferred from the host computer. Then, the divided data is simultaneously distributed to a plurality of disk devices and written back. As a result, the time required to write back the data is shortened. At this time, an error correction code corresponding to the data group distributed and stored in the plurality of disk devices is calculated, and this is stored in a specific disk device among the plurality of disk devices. I did this
Even if some failure occurs in one disk device and some data in the data group is lost, this error correction code and the data stored in another disk device in the data group This is because it is possible to reproduce the lost data and improve the reliability. In addition, such a disk array device is
It is classified into five methods called "level".

[0004]

In the disk array device as described above, a failure occurs in the disk array device due to the error correction code stored in a specific disk array device among the plurality of disk array devices. However, the safety of data when a disk array controller fails is not considered. That is, the safety of the data once stored in the disk cache of the disk controller cannot be guaranteed between the time when the data is transferred from the host computer and the time when this data is completely stored in the disk array device. Even if it is a failure that does not affect the disk cache of the disk controller, there is a possibility that data input / output to / from the disk array device is completely impossible.

Therefore, an object of the present invention is to provide a more reliable disk array device. Another object is to speed up the data input / output processing of such a disk array device.

[0006]

In order to achieve the above object, the present invention provides a plurality of disks and two disk array controllers for controlling input / output of data between a host computer and the plurality of disks. And each of the two disk array controllers has a transfer means for transferring the data transferred from the host computer to the other disk array controller, and a first storage area for storing the data transferred from the host computer. A disk cache having a second storage area for storing data transferred from the other disk array controller; and a control means for instructing write back of data stored in the first storage area of the disk cache, According to an instruction given by the control means, the first storage of the disk cache. Data that has not been written back to the plurality of disks of the area data, or data that has not been written back to the plurality of disks by the other disk array controller of the data stored in the second storage area. The write-back means for writing back to the plurality of disks, and the control means, when the write-back of the data stored in the first storage area of the disk cache fails, the control means of the other disk array controller Data for writing back data stored in the second storage area of the disk cache of the other disk array controller, and data stored in the second storage area of the disk cache from the control means of the other disk array controller Is instructed to write back the To provide a disk array system, wherein the second storage area of the click cache instructs the write back of data to be stored.

[0007]

According to the disk array device of the present invention, 2
One disk array controller controls data input / output between the host computer and the plurality of disks. That is, of the two disk array controllers, the data is stored in the first storage area of the disk cache of the disk array controller to which the data is transferred from the host computer, and the data is stored in the first storage area of the disk cache of the other disk array controller. The data transferred by the transfer means of the disk array controller to which the data has been transferred from the host computer is stored in the second storage area storage. Then, when the control means gives an instruction to write back the data stored in the first storage area of the disk cache, the write back means follows the instruction and outputs the data stored in the first storage area of the disk cache. Data that has not been written back to the plurality of disks is written back to data that has not been written back to the plurality of disks. However, when a failure occurs in the write back of the data stored in the first storage area of the disk cache, the control means causes the control means of the other disk array controller to control the disk cache of the other disk array controller. Instruct write-back of the data stored in the second storage area. On the other hand, when the control means is instructed by the control means of the other disk array controller to write back the data stored in the second storage area of the disk cache, the control means instructs the write back means to follow the instruction. An instruction is given to write back the data stored in the second storage area of the disk cache. Then, according to the instruction, the write-back unit writes the data not written back to the plurality of disks by the other disk array controller of the data stored in the second storage area of the disk cache. Write back to the disc.

With this configuration, the data transferred from the host computer is multiplexed into the first area of the disk cache of one disk array controller and the second area of the disk cache of the other disk array controller. Therefore, even if the write back of the data stored in the first storage area of the disk cache fails, the second storage area of the disk cache of the other disk array controller stores the data. Data can be written back to multiple discs. That is, the safety of data from the time when the data is transferred from the host computer to the time when the data is completely stored in the disk array device is guaranteed. Also, by providing multiple disk controllers in this way,
Even if one of the disk controllers fails, data input / output to / from the disk array device is not completely disabled.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, the basic configuration of the disk array device 1 according to this embodiment will be described with reference to FIG. It should be noted that the disk array device 1 according to the present embodiment employs RAID5 corresponding to level 5 of RAID described in the section of the prior art, and here, for example, a method of creating an error correction code and an input Descriptions of processes generally known as processes performed in RAID5, such as the divided data division method, are omitted.

As shown in FIG. 1, this disk array device 1 includes five disks 4a, 4b, 4c, 4d, 4e and 2 disks.
And a disk array controller 3a, 3b.

The disk array controller 3a,
The details of the configuration of 3b will be described later. First, the data transfer path between the blocks will be described.

As shown in FIG. 1, each disk 4a, 4b,
The disks 4c, 4d and 4e are connected by a disk interface 6 so that data can be transferred to each other.

Similarly, the disk array controllers 3a and 3b are mutually connected by the inter-controller interface 7. Further, the inter-controller interface 13 other than the inter-controller interface 7 is provided between the disk array controllers 3a and 3b.
It is mainly connected to disk 4 though it is connected by
It is provided for the purpose of avoiding a failure that has occurred in the connection between a and 4e and the disk array controllers 3a and 3b. For example, when the disk array controller 3a reads data from the disks 4a, 4b, 4c, 4d, and 4e, if some failure occurs in the connection A between the disk 4a and the disk array controller 3a, the disk 4e and the disk array controller Three
By using the connection B between the disk array controller 3b and the disk array controller 3b, an auxiliary data transfer path is provided in which the disk array controller 3b side transfers the data read from the disks 4a, 4b, 4c, 4d, 4e to the disk array controller 3a side. It is a thing.

Further, each disk array controller 3
a and 3b are host interfaces 5a and 5b, respectively, so that data can be transferred to and from the host computer 2.
It is connected to the host computer 2 by 5b.

Now, as described above, the basic configuration of the two disk array controllers 3a and 3b included in the disk array device 1 according to this embodiment will be described.

The disk array controller 3a shown in FIG.
As shown in FIG. 2, 3b includes host interface control circuits 8a and 8b for controlling data transfer with the host computer 2 and disks 4a, 4b, 4c, and 4b, respectively.
Disk interface control circuits 9a and 9b for controlling data transfer between the disk array controllers 4d and 4e, and inter-controller interface control circuit 10a for controlling data transfer between the other disk array controllers 3b and 3a.
10b, disk caches 11a, 11b for storing data transferred from the host computer 2, transfer control circuits 501a, 501b for controlling data storage in the disk caches 11a, 11b, and control of each block. Microprocessors 502a, 502
b, redundant data generation circuits 503a and 503b that generate redundant data of a predetermined data format from the data stored in the disk caches 11a and 11b, and identifiers (such as serial numbers) unique to the disk array controllers 3a and 3b. Stored ROM and microprocessor 5
02a and 502b, and microprocessor memories 505a and 505b each having a RAM used as a cache or the like when executing a process, and the microprocessor 50
2a and 502b, and microprocessor control circuits 504a and 504b that control the transmission of control signals from the microprocessors 502a and 502b to the microprocessor memories 505a and 505b.

Microprocessor memory 505a, 5
The identifier stored in the ROM of 05b is assigned to each of the disk array controllers 3a and 3b at the time of manufacture without being duplicated and set, and the disks controlled by the microprocessors 502a and 502b are controlled by the identifiers. It is referred to when identifying the array controllers 3a and 3b. The identifier may be set on the host computer 2 side when the disk array device 1 is connected to the host computer 2. However, in this case, each disk array controller 3
Since the identifiers a and 3b are managed by the host computer 2, the microprocessors 502a and 502b of the respective disk array controllers 3a and 3b are required to identify the disk array controllers 3a and 3b controlled by themselves by the host computer. It is necessary to ask 2 for the identifier.

Each disk array controller 3a, 3b
As shown in FIG. 3, the disk caches 11a and 11b of the respective disk caches 11a and 11b are data storage areas 403a and 403b for storing the data transferred from the host computer 2, respectively.
And a multiplexed data storage area 40 for storing data transferred from the other disk array controller 3b, 3a.
1 and management information storage areas 402a and 402b for storing management information (described later) for managing the data stored in the multiplexed data storage areas 401a and 401b.
In this embodiment, since the uninterruptible power supply devices ensure the continuity of the load powers of the two disk array controllers 3a and 3b, the data in the disk caches 11a and 11b can be saved even when the power is suddenly cut. No content is lost.

Further, the multiplexed data storage areas 401a, 4a
01b and the data storage areas 403a and 403b are respectively
16 with the same data capacity, which is the unit of data input / output
It is divided into logical blocks. The data storage areas 403a and 403b are used for the disks 4a, 4b, 4c and 4
This is a data buffer generally provided in RAID 5 in order to solve the overhead that occurs when data is written back to d and 4e, so a description thereof will be omitted here.

Now, the management information storage area 402a of FIG.
The management information stored in 402b will be described with reference to FIG. The management information is stored in the multiplexed data storage areas 401a and 401b and the data storage area 403.
It is created for each of the logical blocks a and 403b.

Now, the multiplexed data storage areas 401a, 4a
01b and the management information A ₁ ... A ₃₂ created for each logical block of the data storage areas 403a and 403b are the identifiers 41 stored in the ROM as shown in FIG.
A head address 42 of an area on the disks 4a, 4b, 4c, 4d, 4e for writing back the data stored in the corresponding logical block, and a capacity 44 of the data stored in the corresponding logical block, It holds the start address 43 of the corresponding logical block, the logical block number 45 associated with the logical block, the tag 46 attached to the data recorded in the logical block, and the status information 47 indicating the state of the logical block. And status information 47
Is 2-byte data representing the state of the logical block by each bit in the data, as shown in FIG. That is, in the bit 51, the management information is multiplexed data storage areas 401a and 401b or data storage areas 403a and 4b.
03b indicates whether the data is stored in the corresponding logical block, bit 52 indicates whether data is stored in the corresponding logical block, and bit 53 is stored in the corresponding logical block. Data is disk 4
a, 4b, 4c, 4d, 4e indicates whether or not it has been written back, and bit 54 indicates whether or not the data stored in the corresponding logical block is also stored in the cache of the other disk array controller. Indicates. In this embodiment, if the bit 51 is set, it indicates that the management information corresponds to the logical block of the multiplexed data storage areas 401a and 401b. If the bit 51 is set, the management information is stored in the data. It shows whether or not it corresponds to the logical blocks of the areas 403a and 403b. If the bit 52 is set, it indicates that the data is stored in the corresponding logical block, and if the bit 53 is set, the data stored in the corresponding logical block is the disks 4a, 4b, 4c, 4d. , 4e, and if bit 54 is set, it indicates that the data stored in the corresponding logical block is also stored in the cache of the other disk array controller. Then, when the state is opposite to this, the corresponding bits 51, 52, 53, 54 are cleared.

Since the basic configuration of the disk array device 1 according to this embodiment has been described above, the request from the host computer 2 made in the disk array device 1 having such a configuration will be described below. The process at the time of responding to is explained.

First, the data transferred from the host computer 2 is transferred to each disk array controller 3a, 3b.
The data multiplexing process for storing the data in the disk caches 11a and 11b will be described with reference to FIG. However, hereinafter, it is assumed that the identifier of the disk array controller 3a is set to 0001 and the identifier of the disk array controller 3b is set to 0002.

When data is transferred from the host computer 2 to the disk array controller 3a side, the following processing is performed on the disk array controller 3a side according to an instruction from the microprocessor 502a (not shown).

First, the transfer control circuit 501a receives the data (arrow A) received by the host interface control circuit 8a.
Is stored in an unused logical block of the data storage area 403a (arrow B). Specifically, the microprocessor 50
2a refers to the management information stored in the management information storage area 402a, and is associated with the smallest logical block number 45 in the management information including the status information 47 in which the bit 51 and the bit 52 are down. When the start address 43 of the logical block is obtained, the transfer control circuit 501a stores the received data in the logical block of the multiplexed data storage area 401a starting from this start address. By the way, at this time, if all the logical blocks of the data storage area 403a are in use, the disks 4a, 4b,
The received data is stored in the logical blocks whose data has been stored in 4c, 4d, and 4e. More specifically, the microprocessor 502a refers to the management information stored in the management information storage area 402a of the disk cache 11a and refers to the status information 4 in which the bit 51 and the bit 54 are down.
Of the management information including 7, the smallest logical block number 45
When the start address 43 of the logical block associated with is obtained, the transfer control circuit 501a stores the received data in the logical block of the multiplexed data storage area 401a starting from this start address. It is assumed that the data is stored in the logical block whose logical block number 45 is 1.

At this time, the microprocessor 502a
Uniquely determines the tag to be attached to this data, and the value is 1
The management information including the logical block number 45 is updated. Then, the transfer control circuit 501a transfers the tag 0003 attached to this data together with the data stored in the data storage area 403a to the inter-controller interface control circuit 10a. Then, the inter-controller interface control circuit 10a transfers these to the other disk array controller 3b side via the inter-controller interface 7.

On the other hand, when the data and the tag 0003 are transferred from the disk array controller 3a side, the microprocessor 5 is transferred to the disk array controller 3b side.
02b (not shown) performs the following processing.

First, the transfer control circuit 501b stores the data received by the host interface control circuit 8b in an unused logical block of the multiplexed data storage area 401b (arrow C). Specifically, microprocessor 502b
Is referred to the management information stored in the management information storage area 402b, and is associated with the smallest logical block number 45 in the management information including the status information 47 in which the bit 51 is set and the bit 52 is set down. When the start address 43 of the logical block is obtained, the transfer control circuit 501b causes the multiplexed data storage area 401b starting from this start address.
The received data is stored in the logical block of. At this time, if all the logical blocks in the multiplexed data storage area 401b are in use, the received data is stored in the logical blocks whose data has already been stored in the disks 4a, 4b, 4c, 4d, 4e. . More specifically, the microprocessor 502b refers to the management information stored in the management information storage area 402b of the disk cache 11b and refers to the management information including the status information 47 in which the bit 51 is set and the bit 54 is set in the management information. , The smallest logical block number 4
When the start address 43 of the logical block associated with No. 5 is obtained, the transfer control circuit 501b stores the received data in the logical block of the multiplexed data storage area 401b starting from this start address. It is assumed here that data is stored in the logical block whose logical block number 45 is 17.

At this time, the microprocessor 502b
Updates the management information including the logical block number 45 whose value is 17. As the tag 46 held in the management information, the tag 0003 transferred from the disk array controller 3b side is used.

In the disk array device 1 according to the present embodiment, even if data is transferred from the host computer 2 to either of the two disk array controllers 3a and 3b, such data multiplexing is performed. Since the processing is performed in the same manner, common data is always stored in the data storage area of the disk cache of one disk array controller and the multiplexed data storage area of the disk cache of the other disk array controller. Become.

In this way, the data transferred from the host computer 2 is transferred to both disk array controllers 3
If the data is stored in the disk caches 11a, 11b of a, 3b in a multiplexed manner, the data is transferred from the host computer, and then the data is transferred to the disks 4a, 4b, 4c,
Even if one of the disk array controllers 3a and 3b fails before the data is stored in 4d and 4e, the data safety is guaranteed. Further, in this embodiment, a part of the disk caches 11a, 11b of the disk array controllers 3a, 3b is used as a storage area for multiplexing and storing data, and a dedicated memory or the like is additionally installed. However, the manufacturing cost of the disk array controllers 3a and 3b itself does not increase significantly.

As described above, the data transferred from the host computer 2 is transferred to each disk array controller 3a, 3
The description of the data multiplexing process for storing the data in the disk caches 11a, 11b of b has been completed, and then the request from the host computer 2 in the case where a failure occurs in one of the disk array controllers 3a, 3b. The response process will be described with reference to FIG.

Now, when some kind of failure is detected by the parity check (for example, the disk cache 11
a, some kind of failure occurs in the disk interface 6a, or some kind of failure occurs in the disk interface 6a).
When some access is being made to a, 4b, 4c, 4d, 4e, etc., the microprocessor 5
02a indicates to the microprocessor 502b of the disk array controller 3b from the data storage area 403a of the disk cache 11a to the disk 4a among the data stored in the multiplexed data storage area 401b of the disk cache 11b of the disk array controller 3b. , 4b, 4c, 4d, 4e is instructed to write back to the disks 4a, 4b, 4c, 4d, 4e the data having the same tag (for example, 0003) as the data to be written back.

When the microprocessor 502b of the disk array controller 3b receives such an instruction, the disk array controller 3b executes the following processing according to the instruction of the microprocessor 502b.

First, the microprocessor 502b of the disk array controller 3b determines that the disk cache 1
A multiplexed data storage area 401b corresponding to the management information including the tag (0003) designated by the microprocessor 502a of the disk array controller 3a among the management information stored in the management information storage area 402b of 1a.
Data stored in the logical block of the redundant data generation circuit 503b is divided according to the RAID5 algorithm.
Creates an error correction code having a predetermined data format based on this data. Then, the transfer control circuit 501b
Stores the data dispersedly on the disks 4a, 4b, 4c, 4d, 4e, and stores the error correction code in the disk 4
It is stored in a predetermined disk among a, 4b, 4c, 4d and 4e (arrow D in the figure). If this is normally completed, the microprocessor 502b has normally completed the write-back of the data to the disks 4a, 4a, 4b, 4c, 4d, 4e to the microprocessor 502a of the disk array controller 3a. Of the management information stored in the management information storage area 402b, the management information including the tag (0003) is updated. Specifically, the microprocessor 502b sets the bit 53 of the status information 47 included in the management information including the tag (0003) in the management information stored in the management information storage area 402b. In addition, when it is not completed normally, the disks 4a, 4a, 4b, 4c, 4d, 4e
Returns an end status indicating that writing back data to was not completed normally.

When the end status reporting the normal end of the data write-back to the disks 4a, 4a, 4b, 4c, 4d, 4e is received from the disk array controller 3b side, the microprocessor of the disk array controller 3a 502a is the disk cache 11a
Of the management information stored in the management information storage area 402a, the management information including the tag (0003) is updated. Specifically, the microprocessor 502a sets the bit 53 of the status information 47 included in the management information including the tag (0003) in the management information stored in the management information storage area 402a of the disk cache 11a. on the other hand,
From the disk array controller 3b side to the disks 4a,
When the end status reporting that the data write-back to 4a, 4b, 4c, 4d, 4e is not normally completed is received, the microprocessor 502a of the disk array controller 3a causes the disk array controller 3
Instructing the microprocessor 502b of b to write back the data stored in the multiplexed data storage area 401b of the disk cache 11b of the disk array controller 3b a predetermined number of times at a predetermined time. repeat.

As described above, according to the disk array system 1 of this embodiment, a failure may occur in the disk cache of one disk array controller, or one disk array controller cannot immediately execute processing. However, the data stored in the disk caches of both disk array controllers in common can be used to allow the other disk controller to perform control in place of this. In addition, even if one of the disk controllers itself fails and becomes inoperable,
The other disk controller can provide alternative control. Therefore, the disks 4a, 4a, 4b, 4c,
It is possible to avoid a situation in which data input / output to / from 4d and 4e is completely impossible. That is, by providing such a configuration, the reliability of the disk array device 1 can be improved. In this embodiment, two disk array controllers are provided in this way, but more disk array controllers may be added. However, in such a configuration, the reliability of the disk array device is improved, but the manufacturing cost is also increased. Therefore, how much reliability is required for the disk array device and the manufacturing cost is reduced. A reasonable number of disk array controllers needs to be decided considering how much it needs to be suppressed.

By the way, when the two disk array controllers 3a, 3b both operate normally, in the disk array device 1 according to this embodiment, the disk array controllers 3a, 3b can be operated in parallel. Therefore, by distributing the processing related to one data input / output to the two disk array controllers 3a and 3b, the processing speed can be increased. The details will be described below. However, here, as the processing related to such data input / output, the processing for storing the data transferred from the host computer 2 in the disks 4a, 4a, 4b, 4c, 4d, 4e in accordance with the RAID5 algorithm is described as the disk 4a. , 4b, 4c, 4d, 4
The process of storing data in e and the disks 4a, 4b, 4
An example will be given of a case where the process is separated from the process of storing the error correction code in a predetermined disk among c, 4d, and 4e.

In order to perform such processing, the status information included in the management information includes the bit 5 shown in FIG.
In addition to 2,52,53,54, the bit 91 shown in FIG. 8 needs to be included. This bit 91 indicates whether or not the error correction code created based on the data stored in the corresponding logical block has been stored in any one of the disks 4a, 4b, 4c, 4d, 4e. It is a thing. In this embodiment, if this bit 91 is set, the error correction code created based on the data stored in the corresponding logical block has already been written on the disks 4a, 4b, 4
It shows that it is already stored in any one of c, 4d and 4e, and if this bit 91 is down,
The opposite state shall be shown.

Two disk array controller 3 of FIG.
The data transferred from the host computer 2 is already stored in the disk caches 11a and 11b of a and 3b by the above-described multiplexing processing. Then, from the disk array controller 3a side to the disk cache 1
When the data stored in the data storage area 403a of the disk 1a is stored in the disks 4a, 4b, 4c, 4d, 4e (arrow E in the figure), the microprocessor 502a sends the data to the microprocessor 502b of the disk array controller 3b. , Instructing the generation of the error correction code.

On the disk array controller 3b side,
When such an instruction is received from the disk array controller 3a side, the following processing is executed by the instruction of the microprocessor 502b. First, in the redundant data generation circuit 503b, the multiplexed data storage area 4
An error correction code is created based on the data stored in 01b. Then, the created error correction code is transferred to the disk interface control circuit 9b by the transfer control circuit 501b, and the disks 4a, 4b, 4c, 4d,
It is stored in a predetermined disk of 4e (arrow F in the figure). When the storage in a predetermined disk among the disks 4a, 4b, 4c, 4d, 4e is completed, the microprocessor 5
02b reports to the disk array controller 3a a status indicating that the creation of the error correction code and the storage in the disk have been completed normally.

On the disk array controller 3a side,
Such status is received from the other disk array controller 3b side, and the disks 4a, 4b,
After storing the data in 4c, 4d, and 4e, the microprocessor 502a stores the data storage area 4 in the management information storage area 402a of the disk cache 11a.
The management information corresponding to the logical block 03a is updated.
Specifically, the bit 91 of the status information included in the management information corresponding to the logical block of the data storage area 403a is set, and the management information is updated in the same manner as in the case of the above-mentioned multiplexing process. Then, it instructs the microprocessor 502b of the disk array controller 3b to update the management information.

On the disk array controller 3b side,
When an instruction to update the management information is issued from the disk array controller 3a side, the microprocessor 502b causes the management information corresponding to the logical block of the multiplexed data storage area 401b stored in the management information storage area 402a of the disk cache 11b. To update. Specifically, the bit 91 of the status information included in the management information corresponding to the logical block of the multiplexed data storage area 401b is set, and the same management information as in the case of the above-described multiplexing processing is updated. In this way, the process of storing data on a disk by the RAID5 algorithm is separated into a process of distributing and storing the data on the disc and a process of generating an error correction code for the corresponding data and storing the data on the disc. ,
If these processes are distributed to a plurality of disk array controllers, it is possible to respond to requests from the host computer at high speed. Further, since each disk array controller stores common data in the disk cache, it is not necessary to transfer the data only for performing such processing. Therefore, since it is not necessary to transfer data, it is possible to respond to the host computer at high speed.

[0045]

According to the disk array device of the present invention, more reliable data input / output can be performed. In addition, it is possible to respond at high speed to a request from the host computer.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a disk array device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the disk array controllers 3a and 3b of FIG.
It is a basic block diagram of.

FIG. 3 is a conceptual diagram of a storage area of the disk cache 11 of FIG.

FIG. 4 is a diagram illustrating a data format of management information.

5 is a diagram illustrating an example of a data format of status information included in the management information of FIG.

FIG. 6 is a diagram illustrating the flow of data when the disk caches 11a and 11b of the disk array controllers 3a and 3b multiplex data.

FIG. 7 is a diagram illustrating a data flow when data is stored in a disk from the disk array controller 3b side.

FIG. 8 is a diagram illustrating an example of a data format of status information included in management information.

FIG. 9 is a diagram illustrating a data flow when the disk array controllers 3a and 3b distribute processing.

[Explanation of symbols]

1 ... Disk array device, 2 ... Host computer 3
a, 3b ... Disk array controller, 4a, 4b, 4
c, 4d, 4e ... Disk, 5a, 5b ... Host interface, 6 ... Disk interface, 7 ... Controller interface, 8a, 8b ... Host interface control circuit, 9a, 9b ... Disk interface control circuit, 10a , 10b ... Interface control circuit between controllers, 11a, 11b ... Disk cache, 50
1a, 501b ... Transfer control circuit, 502a, 502b ... Microprocessor, 503a, 503b ... Redundant data generation circuit, 504a, 504b ... Microprocessor control circuit, 505a, 505b ... Microprocessor memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Souichi Isono, 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Inside the Hitachi, Ltd. Systems Development Laboratory (72) Inventor Seiji Honda, 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi Systems Development Laboratory

Claims (3)

[Claims] 1. A plurality of disks, two disk array controllers for controlling input / output of data between the host computer and the plurality of disks, and the two disk array controllers are respectively transferred from the host computer. Transfer means for transferring the transferred data to the other disk array controller, a first storage area for storing the data transferred from the host computer, and a second storage area for storing the data transferred from the other disk array controller. A disk cache having a storage area; and control means for instructing write-back of data stored in the first storage area of the disk cache. According to an instruction instructed by the control means, the first Write back data from the storage area to the multiple disks Data, or write-back means for writing back data, which is not written back to the plurality of disks by the other disk array controller of the data stored in the second storage area, to the plurality of disks, When a failure occurs in writing back the data stored in the first storage area of the disk cache, the control means causes the control means of the other disk array controller to
A command is issued to write back the data stored in the second storage area of the disk cache of the other disk array controller, and the data stored in the second storage area of the disk cache is instructed from the control means of the other disk array controller. A disk array device, characterized in that, when instructed to write back, the writing back means is instructed to write back the data stored in the second storage area of the disk cache. 2. A plurality of disks, two disk array controllers for controlling input / output of data between the host computer and the plurality of disks, and the two disk array controllers are respectively transferred from the host computer. Transfer means for transferring the transferred data to the other disk array controller, a first storage area for storing the data transferred from the host computer, and the data transferred from the other disk array controller A disk cache having a second storage area; a write-back means for writing back the data stored in the first storage area of the disk cache to the plurality of disks; Command to write back the data stored in the other storage area, and Control means for requesting the array controller to write the error correction code of the data instructed to be written back, and second disk cache of the disk cache when the other disk array controller requests the error correction code to be written. And a write-back means for writing back the error-correction code generated by the generation means to a predetermined disk among the plurality of disks. Characteristic disk array device. 3. The disk array device according to claim 1, wherein in each of the disk array controllers, the write-back means is the first of the disk caches.
Means for notifying the other disk array controller of the identification of the data written back to the plurality of disks from that storage area, and the second storage area according to the identification of the data notified by the other disk array controller Of the data stored in the second storage area of the disk cache, and means for generating and holding information for identifying data that has not been written back to the plurality of disks by the other disk array controller. When instructed to write back the data, the data is written back to the plurality of disks by the other disk array controller of the data stored in the second storage area according to the information for identifying the held data. A disk array characterized by writing back unwritten data to the plurality of disks. A device.