JPH08328709A - Peripheral equipment - Google Patents

Abstract

PURPOSE: To provide a peripheral equipment capable of transmitting data to a host side without erroneous transmission at the time of a nibble mode and the deceleration of a communication speed. CONSTITUTION: The logic levels of status signals generated by a status signal origination part 101 and output signals from driver parts 103a-103d corresponding to the status signals are detected, and when the matching of all the levels is detected, output confirmation signals are supplied to the status signal origination part 101 and the status signals PtrClk are outputted. At the time of communication with a host device by the nibble mode, even when the change of the logic level of the output of the status signals other than the PtrClk signals is delayed, not only accurate communication is performed but also accurate data communication is made possible without lowering the speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral device, and more particularly to a host device such as a personal computer and a peripheral device such as a printer device having a parallel interface capable of data transmission in a nibble mode.

[0002]

2. Description of the Related Art A Centronics parallel interface, which is widely used for transmitting data between a host device such as a personal computer and a peripheral device such as a printer, uses unidirectional parallel data from the host device to the peripheral device. Since only communication is specified, IEEE
In E, a bidirectional parallel interface standard that is upwardly compatible with the parallel interface and is capable of transmitting parallel data from a peripheral device to a host device is being defined (IEEE 1284 Standard Signaling Met).
hod for a Bi-direction Parallel Peipherial Interfa
ce for Personal Computers).

Among the communication modes based on the IEEE P1284 standard, the nibble mode realizes parallel data transmission from the peripheral device to the host device by using the status signal line, and like the other communication modes, the data signal line. Therefore, since it is not necessary to provide an I / F circuit for bidirectionally transmitting and receiving data in the host device and the peripheral device, bidirectional communication is realized by using the same I / F circuit as the conventional parallel interface. can do.

[0004]

However, in a parallel interface of an existing host device such as a personal computer or a peripheral device such as a printer, existing electrical interface layers satisfy the requirements stipulated by IEEE 1284. There are many.

FIG. 7 shows a typical interface circuit of the status signal output from the peripheral device to the host device. In the figure, 701 is a status signal driver by an open collector circuit on the peripheral device side, and R1 is its pull-up. It is resistance. Reference numeral 702 denotes a status signal receiver on the side of a personal computer which is a host device, and generally a 74LS series TTL or the like is used.

Here, there is a receiver on the personal computer side in which resistors R2, R3 and a capacitor C1 are added as shown in the figure. The constant of each CR element is IEEE 1284D2.00 September 1
Although described in Table C4 of 0,1993, the values are various depending on the manufacturer and model, and elements other than the resistor R1 may not be added. In addition, the number of identified CR elements is not added to each status signal line.
Either the capacitor C1 is not added to the lk (= nAck) signal, or a small amount of capacitance C is added to the remaining status signal lines, nDataAvail (= nFault), XFlag (= Select), and AckDataReq.
Some (= PError) and PtrBusy (= Busy) have a large-capacity capacitor C1 added.

Among the status signals, PtrClk
The (= nAck) signal is used in the nibble mode to indicate to the host device that the data to be transferred is to be confirmed (the logic level of the other status signals is to be confirmed). In the conventional Centronics specification (name in parentheses), the host It is used to indicate the completion of data acquisition from the device.

Similarly, the nDataAvail (= nFault) signal is used in the nibble mode to indicate that the data to be transmitted is ready and a part of the data to be transmitted to the host (the other three status signals). 2 in combination with
It shows 1 byte of parallel data divided into times). It also indicates the occurrence of an error when using Centronics specifications.

The XFlag (= Select) signal indicates, in addition to indicating whether the nibble mode is compatible with the nibble mode, a part of parallel data. The Centronics specification also indicates that the device is online.

The AckDataReq (= PError) signal also indicates a part of parallel data in the nibble mode, and indicates that there is no paper in the Centronics specification.

Further, the PtrBusy (= Busy) signal indicates that the data from the host can be received in the nibble mode and also indicates a part of the parallel data to be transmitted. Is a signal indicating that reception is possible.

FIG. 6A shows an example of the timing of the status signal in the nibble mode, and the setup time Tp of the other status signals with respect to the PtrClk signal is specified in IEEE EEP1284 to be 0.5 μs or more. . However, in the case where C1 is added to the status signal other than the PtrClk signal (or C1 having a larger capacity is added) as described above, only the status signals other than the PtrClk signal are large as shown in FIG. PtrClk without delay and without substantial setup time
The level of the status signal when the signal falls may be erroneously read (as is clear from the circuit example of FIG. 7, such a delay of the status signal is from a low level due to the characteristics of the open collector circuit). Great when moving to a high level).

Therefore, even if the peripheral device supports the nibble mode, there is a possibility that normal communication cannot be performed when the peripheral device is connected to the host device.

In order to prevent such a situation, it is sufficient to sacrifice the communication speed and make the setup time Tp sufficiently large on the peripheral equipment side. However, in this case, even if the setup time Tp is small, the connection with the host device which can normally communicate is established. Sometimes, a new problem occurs that the communication speed becomes slow.

The present invention has been made to solve such a problem, and an object thereof is to provide a peripheral device capable of transmitting data to the host side without erroneous transmission in the nibble mode and a decrease in communication speed.

[0016]

In order to solve this problem, the present invention has a parallel interface circuit,
In a peripheral device capable of communicating with the host device in the nibble mode, a status signal transmitting unit that issues each status signal, and a driver unit that receives each status signal issued by the status signal transmitting unit and outputs the status signal to the host device, Among the status signals, for status signals other than the PtrClk signal, a detection unit for detecting whether the logic level before being input to the driver and the logic level of the output signal of the driver unit with respect to the signal match. The status signal transmitting unit changes the output timing of the PtrClk signal in response to the output confirmation signal generated by the detecting unit.

[0017]

With this structure, when data is transmitted to and from the host device in the nibble mode, an input signal to the driver of a status signal other than the PtrClk signal (first status signal) and an output signal from the driver for the status signal. It is detected whether the logic levels of are in agreement with each other.
When a match is detected, the setup time, that is, the output timing of the PtrClk signal is changed according to the detection. Preferably, after a match has been detected and a predetermined time has elapsed
The PtrClk signal is output. If no match is detected within a predetermined time from the output of all other status signals, error processing is performed.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the arrangement of a peripheral device according to this embodiment. In the figure, 101 indicates status signals (PtrClk signal, AckDat during nibble mode communication).
aReq signal, nDataAvail signal, Xflag signal, PtrBusy signal)
Shows the status signal transmitter that sends each driver 1
Reference numeral 02 denotes a driver that receives the PtrClk signal and outputs it to the host device among the status signals transmitted by the status signal transmitting unit 101, 103a to 103d denote drivers that output other status signals to the host device, and 104a to 104.
d is a logic gate (exclusive NOR gate) that generates a logic signal indicating whether the logic level of the input signal to the drivers 103a to 103d matches the logic level of the output signal to the driver 103a to 103d, and 105 is the logic gate 104a to When all of the outputs of the logic gates 104a to 104d indicate a match at the logic level with all of the outputs of the 104d as inputs, the status signal transmitting unit 1
Reference numeral 01 denotes a logic gate (AND gate) that outputs a signal indicating active.

FIG. 2 is a flow chart showing the operation of the status signal transmitter 101 of FIG. 1 when a status signal is output from the peripheral device to the host device in the nibble mode.

As shown in FIG. 2, the status signal transmitting section 101 first outputs status signals other than the PtrClk signal to the drivers 103a to 103d (step S20).
1). Then, in step S202, all of the output drivers 103a to 103d are monitored to see if their input signals and output signals are at the same logic level, and when such a state is reached, the output of the logic gate 105 is at a high level. And the output confirmation signal becomes active. If it is determined in step S202 that this output confirmation signal has become active, the minimum necessary setup time is allowed (step S203), and then PtrC is set.
The lk signal is output to the driver 102 (step S20).
4).

Here, FIG. 3 shows the signal timing at the time of outputting the status signal described above. 301 in the figure
Drivers 103a for status signals other than the PtrClk signal
The output signal from the driver 103d is shown.
It is confirmed in step S202 of FIG. 2 that the signal outputs of a to 103d become the same logic level as the respective input signals, and at that time, the output confirmation signal 302 which is the output of the logic gate 105 becomes active. (In this case, the high level is active), the minimum setup time Tp is secured from this time t1 in step S203, and the PtrClk signal is output (low level in the example of FIG. 3) at t2 after this time. After confirming the Low level of the PtrClk signal at t2, the host device
Since the output 301 of the other status signal is read,
Even if the signal change (especially the rising edge of the signal) of the output 301 is greatly delayed, accurate data reading can be performed.

As described above, by providing the peripheral device with a configuration for outputting the PtrClk signal after confirming that the logic level of the input signal of the driver and the output signal of the output of the status signal other than the PtrClk signal match. It is possible to solve the problems such as the erroneous transmission in the nibble mode and the decrease in the communication speed as described in the conventional problems.

[Second Embodiment] In the second embodiment, in addition to adjusting the setup time of the status signal in the first embodiment, the peripheral device cannot change the logic level of the output of the status signal to meet the standard. In the case where there is a large delay, an error determination is made immediately and error processing is performed.

FIG. 4 is a block diagram of the peripheral device of the second embodiment. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 4, the status signal generator 4
02 outputs a transmission start signal to the status signal output error unit 401 when all status signals other than the PtrClk signal are output to the drivers 103a to 103d. The status signal output error unit 401 is an output confirmation signal and status signal transmission unit 40 which is an output of the logic gate 105.
2 receives the transmission start signal, and performs error determination and error processing.

The operation of the apparatus shown in FIG. 4 will be described with reference to FIG. 5. First, the status signal transmission section 402 outputs a transmission start signal when all status signals other than the PtrClk signal are output. Whether or not it is output is step S501.
Is determined in. In step S502, the status signal error output error unit 401 detects this transmission start signal and starts counting elapsed time from this point. The output confirmation signal from the logic gate 105 becomes active before the elapsed time exceeds a predetermined error determination time (time when it is determined that the signal timing regulation of nibble mode communication defined in IEEE P1284 cannot be satisfied). If not (S503), it is determined that nibble mode communication is impossible, and error processing is performed below (S505). On the other hand, in step S504, it is determined whether the output confirmation signal has become active. If it becomes active, the process returns to step S501, and if not, the process returns to step S503.

With such a configuration, the peripheral device can judge that the status signal driver is abnormal, the connected host device receiver is abnormal, or the receiver cannot communicate in nibble mode, and immediately. It is possible to start the error handling.

[0029]

As described above, according to the present invention, the status signal generated by another status signal transmitting section and the logic level of the output signal from the driver section corresponding to the status signal are detected, and the predetermined status is detected. Since the signal output timing is changed, not only accurate communication can be performed even when the change in the logic level of the output of other status signals is delayed during communication with the host device in nibble mode. Accurate data communication is possible without reducing the speed.

If the change in the logic level of the output of the status signal is delayed to such an extent that communication in the nibble mode is impossible, or if there is an abnormality in the driver section or the receiver section of the status signal, this is detected. It is also possible to immediately perform appropriate error processing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a peripheral device of the present invention.

FIG. 2 is a flowchart showing an operation of a status signal transmission unit of the peripheral device according to the first embodiment.

FIG. 3 is a signal timing chart at the time of outputting a status signal in the peripheral device according to the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a second embodiment of a peripheral device of the present invention.

FIG. 5 is a flowchart showing an operation of a status signal output error processing unit of the peripheral device according to the second embodiment.

FIG. 6 is an explanatory diagram illustrating delay of a status signal in a conventional example.

FIG. 7 is a circuit diagram showing a typical interface circuit example in a conventional example.

[Explanation of symbols]

101, 402 Status signal transmission unit 102, 103a-103d, 701 Peripheral device driver 104a-104d, 105 Logic gate 401 Status signal output error processing unit 701 Peripheral device driver 702 Host device receiver

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yoshiaki Kanoki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Noriyuki Suzuki 3-30-2 Shimomaruko, Ota-ku, Tokyo Kya Non-Incorporated (72) Inventor Hiroshi Uemura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (4)

[Claims] 1. A parallel interface circuit is provided,
In a peripheral device capable of communicating with a host device in a nibble mode, a status signal transmitting unit, a driver unit that receives each status signal generated by the status signal transmitting unit, and outputs the status signal to the host device, respectively, and Among them, it detects whether or not the logic level of the status signal other than the first status signal and the logic level of the output signal of the driver unit corresponding to the signal are detected, and outputs the output signal to the status signal transmitting unit. A peripheral device comprising a detection unit, wherein the status signal transmission unit changes an output timing of the first status signal in accordance with an output signal from the detection unit. 2. The detection means outputs when a logic level of a status signal other than the first status signal and a logic level of an output signal of a driver section with respect to the status signal is detected to match in all pairs. The peripheral device according to claim 1, wherein the peripheral device generates a signal. 3. The peripheral device according to claim 1, wherein the first status signal is output after a lapse of a predetermined time after the detection means generates an output signal. 4. If the output signal is not obtained from the detection means within a predetermined time after the status signal transmission unit outputs another status signal, error processing is performed. Any one of items 1 to 3
Peripheral device according to paragraph.