JPH0832854A - Still image pickup device - Google Patents

Abstract

PURPOSE:To provide a still image pickup device by changing the read speed of a solid-state image pickup element depending on a luminous quantity of an object so as to change a storage time to store the charge subjected to photoelectric conversion thereby changing the sensitivity. CONSTITUTION:The device is made up of a lens 2, a solid-state image pickup element 52 converting an object image through the lens 2 into an electric signal, an A/D converter 53 converting a signal from the solid-state image pickup element 52, a 1st digital signal processing circuit 54, a storage circuit 55 storing the signal from the circuit 54, a 2nd digital signal processing circuit 57, a D/A converter 58 converging the digital signal into an analog signal, a 1st timing control circuit 56 implementing timing control to process the signal from the solid-state image pickup element 52 to the input of the storage circuit 55 at a low speed and a 2nd timing control circuit 59 implementing timing control to process the signal from an output of the storage circuit 55 to the D/A converter 58 at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image pickup device using a solid-state image pickup device.

[0002]

2. Description of the Related Art FIG. 13 shows, for example, JP-A-2-200086.
FIG. 1 is a block diagram showing a conventional still image pickup device disclosed in the publication, in which 1 is a shutter, 2 is a lens or lens group, 3 is a transmitted light wavelength selecting means, 4 is an image sensor,
Reference numeral 5 is a buffer amplifier, 6 is an A / D converter, 7 is a signal processing device, 8 is a storage device, 9 is a mechanical system drive device, 10 is a timing control device, and 11 is an external trigger terminal. Here, the transmitted light wavelength selection means 3 is a wavelength selection means corresponding to at least three different colors of light, for example, R (red) and G.
(Green), B (blue) or Cy (cyan), Ye
It is equipped with (yellow), G (green), and W (white) color filters.

FIG. 14 shows the structure of the transmitted light wavelength selecting means 3 of FIG. 13, the transmitted light wavelength selecting means 3, the lens 2 and the image pickup device 4.
It is a figure showing the relation with. In the figure, a light ray from a subject that has entered the lens or lens group 2 forms an image on the surface of the image sensor 4 arranged behind the focal point 23. The color filter 24 is arranged between the lens or the lens group 2 and the image sensor 4. The color filter 24 is, for example, R,
It is configured to transmit light of three colors of G and B. The color filter element 20 is configured to transmit R light, the color filter element 21 is configured to transmit G light, and the color filter element 22 is configured to transmit B light. The figure shows a color filter element 21.
2 shows a state in which only the light that has passed through, that is, the light having the green spectral component reaches the surface of the image sensor 4. The color filter 24 includes the color filter elements 20, 21, and 2.
2 is slidable in a direction indicated by an arrow 25 by a predetermined pitch P determined in correspondence with the arranged pitch.

FIG. 15 is a view showing the structure of the color filter 24 in the conventional transmitted light wavelength selecting means 3. This figure is a view of the color filter 32 seen from the light incident surface, and the color filter elements 26, 27, 28 are formed so as to transmit only the light having the spectral components of R, G, B, respectively. ing. For example, when only the light ray having the G spectral component is transmitted, the image pickup surface of the image pickup element is superposed on the position indicated by the frame 31. The color filter 32 is configured to be rotatable about the point 29 in the direction of the arrow 30 by a constant angle (120 degrees in this example).

Next, the operation will be described. It is assumed that a trigger signal such as 41 in FIG. 16 is applied to the external trigger terminal 11 shown in FIG. At this time, the timing control device 10 calculates the shutter speed based on the light amount of the subject, the sensitivity of the image pickup device, the image pickup condition set from the outside, and indicates the time for opening the shutter 1 as indicated by 42 in FIG. The signal is transmitted to the mechanical system drive device 9. Ts in FIG. 16 indicates a period in which the shutter 1 is opened. The mechanical system driving device 9 outputs the control signal 4
The opening / closing of the shutter 1 is controlled based on 2.

A more detailed operation will be described by taking as an example the case where the transmitted light wavelength selecting means 3 has a structure provided with filters corresponding to R, G and B colors as shown in FIG.
The color filter 32 is rotated in the direction of arrow 30,
At this time, Tr, Tg, and Tb in FIG. 16 show periods during which the color filters corresponding to R, G, and B operate. That is, the timing control device 10 divides the period Ts in which the shutter 1 is opened into three, Tr, Tg, and Tb, and transmits the control signals 43, 44, and 45 containing the information to the mechanical system drive device 9. The mechanical system driving device 9 receives the control signal 4
The transmitted light wavelength selection means 3 is controlled based on 3, 44, and 45, and light having a spectral component of R in the period Tr and G in the period Tg.
The light having the spectral component of B and the light having the spectral component of B are transmitted in the period Tb. The image sensor 4 includes the above-mentioned R, G, and B.
Lights having respective spectral components are received, they are sequentially converted into electric signals, and the electric signals are transmitted to the signal processing device 7 via the buffer amplifier 5 and the A / D converter 6. The signal processing device 7 receives the electrical signals corresponding to the respective lights having the R, G, and B spectral components, performs a predetermined process on the received electrical signals, and synthesizes them to generate a color image signal. The storage device 8 stores the color image signal.

[0007]

Since the conventional still image pickup device is constructed as described above, it has the following problems. First, if a certain television system image pickup device is installed, the signal processing circuit in the subsequent stage also needs to be compatible with the television system. For example, it would be difficult to implement the latter signal processing circuit without high-speed processing and expensive parts. Secondly, unless the shutter is controlled to open and close to limit the amount of incident light, an image with optimum brightness cannot always be obtained.

Claim 1 of the present invention has been made to solve the above-mentioned first problem, and a signal processing circuit is composed of inexpensive NTSC-compatible parts to obtain a high-definition still image. An object is to provide an image pickup device.

The second to eleventh aspects of the present invention have been made to solve the second problem, and the sensitivity of the solid-state image pickup device is changed according to the light quantity of the subject to display a still image. It is an object of the present invention to provide a still image pickup device that always displays with optimum brightness.

[0010]

A still image pickup device according to claim 1 of the present invention includes a lens, a solid-state image pickup device for converting a subject image formed by the lens into an electric signal, and the solid-state image pickup device. A / D converter for converting the analog signal from the digital signal into a digital signal, a first digital signal processing circuit for processing the digital signal from the A / D converter, and a signal processed by the first digital signal processing circuit. A storage circuit that stores the signal, a first timing control circuit that performs timing control for low-speed processing from the solid-state imaging device to the input of the storage circuit, and a digital signal read from the storage circuit. A second digital signal processing circuit for processing, and D / for converting a digital signal from the second digital signal processing circuit into an analog signal.
A second converter for performing timing control for high-speed processing from the output of the storage circuit to the D / A converter
And a timing control circuit of.

According to a second aspect of the present invention, there is provided a still image pickup device, a lens, a solid-state image pickup device for converting an object image formed by the lens into an electric signal, and an analog signal from the solid-state image pickup device. A to digital signal
/ D converter, a first digital signal processing circuit for processing the digital signal from the A / D converter, the first
A storage circuit for storing a signal processed by the digital signal processing circuit, a third timing control circuit for performing timing control from the solid-state imaging device to an input of the storage circuit, and a clock for the third timing control circuit. Clock frequency change instructing means for sending an instruction to change the frequency, a second digital signal processing circuit for processing the digital signal read from the storage circuit, and the second
A D / A converter for converting a digital signal from the digital signal processing circuit of the above into an analog signal, and a second timing control circuit for performing timing control from the output of the memory circuit to the D / A converter. It is a thing.

According to a still image pickup device of a third aspect of the present invention, the third timing control circuit includes a plurality of frequency dividing circuits having different frequency dividing ratios and outputs of the plurality of frequency dividing circuits. It is composed of a selector circuit for selecting one of them and a second timing generator for creating a timing pulse based on a clock output from the selector circuit.

In the still image pickup device according to claim 4 of the present invention, the third timing control circuit includes a first frequency dividing circuit for dividing the clock sent from the second timing control circuit. A second divider circuit for dividing the clock divided by the first divider circuit, and an Nth divider circuit for dividing the clock divided by the (N-1) th divider circuit And a clock selecting means for selecting any one of the outputs of the respective frequency dividing circuits, and a third timing generator for generating a timing pulse based on the clock output from the clock selecting means.

According to a fifth aspect of the present invention, in a still image pickup device, a lens, a solid-state image pickup element for converting a subject image formed by the lens into an electric signal, and an analog signal from the solid-state image pickup element is digitally supplied. A / D to convert to signal
A converter, a first digital signal processing circuit for processing the digital signal from the A / D converter, a storage circuit for storing the signal processed by the first digital signal processing circuit, and the solid-state imaging device Timing control circuit for controlling the timing from the input to the storage circuit, a second digital signal processing circuit for processing the digital signal read from the storage circuit, and the second digital signal processing circuit A D / A converter for converting a digital signal from the D / A converter into an analog signal, and a second control for controlling the timing from the output of the memory circuit to the D / A converter
The timing control circuit, the light amount detecting means for detecting the light amount of the object, and the frequency changing means for outputting a control signal for changing the frequency of the clock according to the output from the light amount detecting means. .

According to a sixth aspect of the present invention, in the still image pickup device, the frequency changing means has an averaging circuit for averaging the output signals from the light amount detecting means, and the output of the averaging circuit has a first reference level. A first comparison circuit for comparison and a second comparison circuit for comparing the output of the averaging circuit with a second reference level.

A still image pickup device according to a seventh aspect of the present invention includes: a plurality of frequency dividing circuits having different frequency dividing ratios; and a selector circuit for selecting any one of the outputs of the plurality of frequency dividing circuits. A third timing control circuit composed of a second timing generator that creates a timing pulse based on the clock output from the selector circuit, an averaging circuit that averages the outputs from the light amount detection means, and the averaging circuit A frequency changing means including a first comparing circuit for comparing the output of the circuit with a first reference level and a second comparing circuit for comparing the output of the averaging circuit with a second reference level. Is.

Further, in the still image pickup device according to claim 8 of the present invention, the first frequency dividing circuit for frequency-dividing the clock sent from the second timing control circuit, and the first frequency dividing circuit. A second frequency divider circuit that divides the clock output from the N-th frequency divider circuit, a Nth frequency divider circuit that divides the clock output from the (N−1) th frequency divider circuit, and a plurality of the frequency divider circuits. A third timing control circuit composed of a clock selecting means for selecting one of the outputs, a third timing generator for creating a timing pulse based on the clock output from the clock selecting means, and a light amount detecting means. An averaging circuit for averaging the outputs from the
The frequency changing means includes a first comparing circuit for comparing the output of the averaging circuit and a second comparing circuit for comparing the output of the averaging circuit with the second reference level.

A still image pickup device according to claim 9 of the present invention is a lens, a solid-state image pickup device for converting an object image formed by the lens into an electric signal, and a signal obtained from the solid-state image pickup device. To convert the digital signal to A /
A D converter, a first digital signal processing circuit for processing the digital signal converted by the A / D converter, a storage circuit for storing the signal processed by the first digital signal processing circuit, and A third timing control circuit for performing timing control from the solid-state imaging device to the input of the storage circuit, a second digital signal processing circuit for processing a digital signal read from the storage circuit, and the second digital A D / A converter that converts a digital signal from a signal processing circuit into an analog signal, a second timing control circuit that controls the timing from the output of the storage circuit to the D / A converter, and the solid-state imaging device And a frequency changing means for outputting a control signal for changing the frequency of the clock according to the amplitude level of the signal obtained from

Further, according to a tenth aspect of the present invention, in a still image pickup device, a plurality of frequency dividing circuits having different frequency dividing ratios and a selector circuit for selecting any one of the outputs of the plurality of frequency dividing circuits. A third timing control circuit configured with a second timing generator that creates a timing pulse based on the clock output from the selector circuit; an averaging circuit that averages signals obtained from the solid-state imaging device; There is provided a frequency changing means composed of a first comparing circuit for comparing the output of the averaging circuit with a first reference level and a second comparing circuit for comparing the output of the averaging circuit with a second reference level. It is a thing.

According to an eleventh aspect of the present invention, in a still image pickup device, a first frequency dividing circuit for frequency-dividing a clock sent from a second timing control circuit and the first frequency dividing circuit. A second frequency divider circuit that divides the clock output from the first frequency divider circuit, a Nth frequency divider circuit that divides the clock output from the (N−1) th frequency divider circuit, and the first, second, and Nth frequency divider circuits. A third timing control circuit comprising a clock selecting means for selecting one of the outputs of the frequency dividing circuit, and a third timing generator for generating a timing pulse based on the clock output from the clock selecting means. , An averaging circuit for averaging the signals obtained from the solid-state image pickup device, a first comparing circuit for comparing the output of the averaging circuit with a first reference level, and comparing the output of the averaging circuit with a second reference level. With the second comparison circuit It is provided with a and made frequency changing means.

In the still image pickup apparatus according to the first aspect of the present invention, the NTSC is provided from the solid-state image pickup element to the input of the memory circuit.
Processing is performed at almost the same speed as, and processing is performed at the high-definition speed after the output of the memory circuit.

In the still image pickup device according to the second aspect of the present invention, the solid-state image pickup is performed by changing the reference clock for timing control from the solid-state image pickup element to the input of the memory circuit according to the light quantity of the object. Change the reading speed from the element.

In the still image pickup device according to the third aspect of the present invention, the clocks divided by the plurality of dividing circuits having different dividing ratios are changed by the clock frequency changing instruction means according to the light quantity of the object. An instruction for selection is sent to the selector circuit.

In the still image pickup device according to claim 4 of the present invention, the clock sent from the second timing control circuit is divided by the first dividing circuit, and the divided clock is divided by the first dividing circuit. The frequency of the divided clock is divided by the second dividing circuit, the divided clock is divided by the Nth dividing circuit, and the output of each dividing circuit is selected by the clock frequency changing instruction means in accordance with the light quantity of the subject. An instruction to do so is sent to the clock selection means.

In the still image pickup device according to claim 5 of the present invention, the light amount detecting means detects the light amount of the object,
A control signal corresponding to the light amount is output from the frequency changing means, and a reference clock of the third timing control circuit is changed according to the control signal to change the reading speed of the signal from the solid-state image sensor.

In the still image pickup device according to claim 6 of the present invention, the outputs from the light amount detecting means are averaged by the averaging circuit, and the first and second preset circuits are set by the first and second comparing circuits. Compare with the reference level of.

In the still image pickup device according to claim 7 of the present invention, the outputs from the light amount detecting means are averaged by the averaging circuit, and the first and second preset values are preset by the first and second comparison circuits. Of the plurality of frequency division circuits having different frequency division ratios is selected according to the comparison result.

In the still image pickup device according to claim 8 of the present invention, the outputs from the light amount detecting means are averaged by the averaging circuit, and the first and second preset circuits are preset by the first and second comparing circuits. Of the first, second, and N frequency divider circuits is selected according to the comparison result.

In the still image pickup device according to claim 9 of the present invention, a control signal corresponding to the level of a signal obtained from the solid-state image pickup device is output from the frequency changing means, and the third control signal is output in accordance with the control signal. The clock serving as the reference of the timing control circuit changes and the reading speed of the signal from the solid-state image sensor changes.

In the still image pickup device according to claim 10 of the present invention, the signals obtained from the solid-state image pickup device are averaged by the averaging circuit, and the first and second preset circuits are set by the first and second comparison circuits. It is compared with the second reference level, and one of the outputs of the plurality of frequency dividing circuits having different frequency dividing ratios is selected according to the comparison result.

In the still image pickup device according to the eleventh aspect of the present invention, the signals obtained from the solid-state image pickup device are averaged by the averaging circuit, and the first and second preset circuits are set by the first and second comparison circuits. It is compared with the second reference level, and one of the outputs of the first, second and N frequency divider circuits is selected according to the comparison result.

[0031]

【Example】

Example 1. FIG. 1 is a block diagram showing a still image pickup device according to claim 1 of the present invention. In the figure, 2 is a lens, 52
Is a solid-state image sensor, 53 is an A / D converter that converts the signal from the solid-state image sensor 52 into a digital signal, and 54 is an A / D
First for processing the digital signal converted by the converter 53
Digital signal processing circuit, 55 is a storage circuit for storing the digital signal processed by the first digital signal processing circuit 54, and 56 is the solid-state imaging device 52 to the storage circuit 5
A first timing control circuit for performing timing control for processing up to 5 inputs at substantially the same speed as NTSC, a second digital signal processing circuit 57 for processing a digital signal read from the storage circuit 55, Reference numeral 58 is a D / A converter for converting the signal from the second digital signal processing circuit 57 into an analog signal, and 59 is a timing for processing from the output of the storage circuit 55 to the D / A converter 58 at a high-definition speed. It is a second timing control circuit for controlling.

FIG. 2 is a block diagram showing the first timing control circuit 56 and the second timing control circuit 59 in FIG. In the figure, reference numeral 60 denotes a frequency dividing circuit for frequency-dividing the clock sent from the second timing control circuit 59, and 6
Reference numeral 1 is a timing generator that creates a timing pulse based on the clock divided by the frequency dividing circuit 60, and 62 is an oscillator.

Next, the operation will be described. A clock (hereinafter, referred to as a clock having a frequency fs) is sent from the second timing control circuit 59 to the first timing control circuit 56. The clock of the frequency fs is the frequency dividing circuit 60.
The frequency is divided into a clock (hereinafter, referred to as frequency fh) close to the frequency handled by the NTSC system. The timing generator 61 creates a timing pulse based on the divided clock of the frequency fh. Solid-state image sensor 52
Is driven at almost the same speed as NTSC by the timing pulse generated from the timing generator 61.
The signal obtained from the solid-state imaging device 52 is sent to the A / D converter 53 with the clock having the frequency fh as a reference and converted into a digital signal. The digital signal is sent to the first digital signal processing circuit 54 and is sent to the timing generator 61.
Predetermined processing is performed by a timing pulse or the like. The digital signal processed by the first digital signal processing circuit 54 is written in the memory circuit 55 with reference to the clock and the timing pulse of the frequency fh from the timing generator 61.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing control circuit 59 controls the timing at the high-definition speed. From the memory circuit 55, a timing pulse created based on a clock generated from the oscillator 62 in the second timing control circuit 59 (hereinafter, referred to as a clock of frequency fs) and a digital signal at a high-definition speed by the clock. Is read. The read digital signal is sent to the second digital signal processing circuit 57. Second digital signal processing circuit 57
The digital signal sent to is processed at high-definition speed. The digital signal from the second digital signal processing circuit 57 is supplied to the D / A converter 58 at a high-definition speed by the clock from the second timing control circuit 59.
And converted to an analog signal.

Example 2. FIG. 3 is a configuration diagram showing a still image pickup device according to claim 2 of the present invention. In the figure, 2 is a lens, 52 is a solid-state image sensor, 53 is a solid-state image sensor 52.
A / D converter for converting the signal from the signal into a digital signal,
54 is a first for processing the A / D converted digital signal
, 55 is a storage circuit for storing the digital signal from the first digital signal processing circuit 54, and 63 is a third timing control circuit for performing timing control from the solid-state imaging device 52 to the input of the storage circuit 55. , 57 is a second digital signal processing circuit for processing the digital signal read from the storage circuit 55, 58 is a D / A converter for converting the digital signal from the second digital signal processing circuit 57 into an analog signal, Reference numeral 59 is a second timing control circuit that controls the timing from the output of the storage circuit 55 to the D / A converter 58, and 64 is a clock frequency that sends an instruction for changing the clock frequency to the third timing control circuit 63. It is a change instruction means.

Next, the operation will be described. A clock of frequency fs is sent from the second timing control circuit 59 to the third timing control circuit 63. The cycle of the clock is changed in the third timing control circuit. Then, the timing pulse is created based on the clock whose cycle is changed. When the power is turned on, this device operates in the standard condition. In the standard state, the third timing control circuit 63 divides the transmitted clock of frequency fs into a clock of frequency fc and outputs a timing pulse based on this clock. The solid-state imaging device 52 is driven by the timing pulse, and the signal is read. The signal read from the solid-state image sensor 52 is A
It is sent to the / D converter 53 and converted into a digital signal by the clock of frequency fc. The converted digital signal is sent to the first digital signal processing circuit 54 and subjected to predetermined processing by a timing pulse or the like. The signal from the first digital signal processing circuit 54 is sequentially written in the storage circuit 55 by the clock and timing pulse of the frequency fc.

The second stage after reading from the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal.

Next, the operation will be described by taking as an example the case where a bright (a large amount of light) subject is imaged. Frequency change instruction means 64
By this, an instruction for changing the clock cycle to a cycle shorter than the standard time is sent to the third timing control circuit 63.
In response to this instruction, the third timing control circuit 63 changes the clock to a faster clock than the clock of frequency fc and creates a timing pulse. The solid-state image sensor 52 is driven by the timing pulse, and the signal is read out at a speed faster than the standard time. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by a clock having a speed faster than the clock of the frequency fc. The converted digital signal is sent to the first digital signal processing circuit 54, and is subjected to predetermined processing by a timing pulse or the like. The signals from the first digital signal processing circuit 54 are sequentially written in the memory circuit 55 by timing pulses or the like based on a clock having a speed faster than the clock of the frequency fc.

The second stage from the reading of the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal.

Next, the operation will be described by taking a case where a dark (light amount is small) object is imaged as an example. Frequency change instruction means 64
Thus, an instruction for changing the clock cycle to a clock having a cycle longer than that of the frequency fc is sent to the third timing control circuit 63. Third timing control circuit 6
In response to this instruction, 3 changes to a clock having a slower speed than the clock of frequency fc and creates a timing pulse.
The solid-state image sensor 52 is driven by the timing pulse, and the signal is read out at a speed slower than the standard time. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by a clock having a speed slower than the clock of the frequency fc. The converted digital signal is sent to the first digital signal processing circuit 54, and is subjected to predetermined processing by a timing pulse or the like.
The signals from the first digital signal processing circuit 54 are sequentially written in the memory circuit 55 by timing pulses or the like based on a clock having a slower speed than the clock of the frequency fc.

The second stage after the reading of the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. In this way, when the amount of light of the subject is large, the reading operation of the solid-state image pickup element 52 is accelerated to shorten the accumulation time for accumulating the photoelectrically converted charges. When the amount of light is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be arbitrarily changed according to the light amount of the subject.

Example 3. FIG. 4 is a block diagram showing the configuration of the third timing control circuit 63 according to claim 3 of the present invention. Note that a case where three frequency dividing circuits are provided will be described as an example. In the figure, reference numerals 65, 66 and 67 are frequency dividing circuits having different frequency dividing ratios, 68 is a selector circuit, and 69 is a second timing generator which creates a timing pulse based on the clock selected by the selector circuit 68.

Next, the operation will be described. Frequency divider 6
A second clock of frequency fs is input to 5, 66, and 67.
Is sent from the timing control circuit 59. The frequency dividing circuits 65, 66 and 67 have different frequency division ratios and frequency fs.
Divide the clock of. The frequency dividing circuit 66 divides the clock into a clock of frequency fc, the frequency dividing circuit 65 into a clock having a shorter cycle than the clock of frequency fc, and the frequency dividing circuit 67 divides into a clock having a longer cycle than the clock of frequency fc. Frequency divider 6
The clock divided by 5, 66, and 67 is the selector circuit 6
Sent to 8. When the power is turned on, the clock frequency change instructing means 64 outputs a control signal having a negative logical value (hereinafter referred to as L level) and a positive logical value (hereinafter referred to as H level) from the lower order. The control signal from the clock frequency change instruction means 64 is sent to the selector circuit 68. In the selector circuit 68, the control signal sent from the lower order is L
In the case of the level and the H level, as shown in FIG. 5, the clock of the frequency fc divided by the frequency dividing circuit 66 is selected.
The second timing generator 69 is a selector circuit 68.
The timing pulse is generated with reference to the clock of the frequency fc output from.

The solid-state image pickup element 52 is driven by a timing pulse created based on a clock of frequency fc,
The signal is read. The electric signal obtained from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by the clock of the frequency fc. The digital signal is sent to the first digital signal processing circuit 54 and is subjected to predetermined processing by a timing pulse or the like. The signal-processed digital signal is written in the memory circuit 55 with reference to the clock and the timing pulse of the frequency fc.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal.

Next, the operation will be described by taking as an example the case of picking up an image of a bright subject (having a large amount of light). First, the clock frequency change instruction means 64 is operated to output the control signals of H level and H level from the lower order. The control signal is the selector circuit 6
8 is input. In the selector circuit 68, when the control signal is from the lower level to the H level and the H level, a clock having a cycle shorter than the frequency fc divided by the frequency dividing circuit 65 is selected as shown in FIG. The second timing generator 73 creates a timing pulse based on this clock.

The solid-state image pickup device 52 is driven by a timing pulse created on the basis of a clock having a speed higher than the frequency fc, and a signal is read out. The electric signal obtained from the solid-state image sensor 52 is A / based on the clock of frequency fc.
It is sent to the D converter 53 and converted into a digital signal. The digital signal is sent to the first digital signal processing circuit 54, where it is subjected to predetermined processing by a timing pulse or the like. The signal-processed digital signal is written in the memory circuit 55 with reference to the clock and the timing pulse of the frequency fc.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. When a dark (light amount) subject is imaged, the clock frequency change instructing means 64 is operated so as to output L level and L level control signals from the lower order. The control signal is input to the selector circuit 68, and as shown in FIG. 5, a clock having a cycle longer than the frequency fh divided by the divider circuit 67 is selected. When it is determined that the amount of light of the subject is large in this way, the reading operation of the solid-state imaging device 52 is accelerated to shorten the accumulation time for accumulating photoelectrically converted charges. Also,
When it is determined that the amount of light of the subject is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for storing the photoelectrically converted charges to be long. By doing so, the sensitivity can be arbitrarily changed according to the light amount of the subject.

Example 4. FIG. 6 is a configuration diagram showing a third timing control circuit 63 according to claim 4 of the present invention. Note that a case where three frequency dividing circuits are provided will be described as an example. In the figure, reference numeral 64 is a clock frequency change instruction means for sending a control signal for changing the frequency of the clock to the third timing control circuit 63, 85 is a first frequency dividing circuit for dividing a clock of frequency fs, and 86 is A second frequency divider circuit that divides the clock frequency-divided by the first frequency divider circuit 85, and a third frequency divider 87 that divides the clock frequency-divided by the second frequency divider circuit 86.
, 88 is a frequency dividing instruction means 6 for outputting each output from the first frequency dividing circuit 85 to the third frequency dividing circuit 87.
Clock selection means for selecting in accordance with the control signal from 4.
Reference numeral 89 is a third timing generator that creates a timing pulse based on the clock selected by the clock selection means 88.

Next, the operation will be described. When the power is turned on,
A clock of frequency fs is sent from the second timing control circuit 59 to the first frequency dividing circuit 85. The input clock is divided by a certain dividing ratio and sent to the second dividing circuit 86. The clock input to the second frequency dividing circuit 86 is frequency-divided by a certain frequency dividing ratio and sent to the third frequency dividing circuit 87.
Finally, the output of the third frequency dividing circuit 87 becomes the clock with the longest cycle. The clocks output from the frequency dividing circuits 85, 86 and 87 are sent to the clock selecting means 88. The clock selection means 88 selects the clock input according to the control signal from the clock frequency change instruction means 64.
The clock frequency changing instructing means 64 so that the clock selecting means 88 selects the output of the third frequency dividing circuit 87 when the light quantity of the object is small and the output of the first frequency dividing circuit 85 when the light quantity of the object is large. To operate. The third timing generator 89 creates a timing pulse based on the clock output from the clock selection means 88.

When the power is turned on, the clock frequency change instructing means 64 outputs the control signal in the standard state and the clock divided by the second frequency dividing circuit 86 (hereinafter, referred to as the clock of frequency fc) is selected. To be done. In this case, the solid-state image sensor 52 is driven by the timing pulse based on the clock of the frequency fc created by the third timing generator 89. The electric signal obtained from the solid-state imaging device 52 is sent to the A / D converter 53 based on the clock of the frequency fc from the third timing generator 89 and converted into a digital signal. The digital signal is sent to the first digital signal processing circuit 54, where it is subjected to predetermined processing by a timing pulse or the like. The signal-processed digital signal is stored in the storage circuit 5 by the timing pulse from the third timing generator 89 and its reference clock.
Written to 5.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. When the amount of light of the subject is large, the clock frequency change instructing means 64 selects a clock faster than the standard time divided by the first frequency dividing circuit 85, and the solid-state image pickup element 52 is generated by the timing pulse created based on this clock. Is driven and the signal is read out quickly. By increasing the read operation, the accumulation time for accumulating the photoelectrically converted charges becomes shorter. Also,
When the amount of light of the subject is small, the clock frequency change instructing means 64 selects a clock that is slower than the standard time and is divided by the third frequency dividing circuit 87, and the solid-state image pickup element 52 is generated by the timing pulse created based on this clock. Is driven and the signal is read out late. By slowing the read operation, the storage time for storing photoelectrically converted charges becomes longer. In this way, the sensitivity can be arbitrarily changed according to the light amount of the subject.

Example 5. FIG. 7 is a block diagram showing a still image pickup device according to claim 5 of the present invention. In the figure, 2 is a lens, 52 is a solid-state image sensor, 53 is a solid-state image sensor 52.
A / D converter for converting the signal from the signal into a digital signal,
54 is a first for processing the A / D converted digital signal
Digital signal processing circuit, 55 is a storage circuit for storing the signal from the first digital signal processing circuit 54, 63 is a third timing control circuit for performing timing control from the solid-state imaging device 52 to the input of the storage circuit 55, 57 is a second digital signal processing circuit for processing the digital signal read from the storage circuit 55, 58 is a D / A converter for converting the digital signal from the second digital signal processing circuit 57 into an analog signal, 59 Is a second timing control circuit for controlling the timing from the output of the storage circuit 55 to the D / A converter 58, 78 is a light amount detecting means for detecting the light amount of the object, and 79 is a clock frequency according to the detected light amount. Is a frequency changing means for outputting a control signal for changing. The light amount detecting means 78 is assumed to be composed of, for example, a photodiode that converts light into an electric signal.

Next, the operation will be described. The light amount detecting means 78 detects the light amount of the object and sends the photoelectrically converted electric signal to the frequency changing means 79. The third timing control circuit 63 outputs the frequency fs from the second timing control circuit 59.
Clock is sent. The cycle of the clock is changed in the third timing control circuit 63. The third timing control circuit 63 creates a timing pulse based on the clock whose period has been changed. Frequency changing means 79
When it is determined that the electric signal input to is a standard level, for example, a control signal corresponding to the standard state is output.
The control signal is sent to the third timing control circuit 63. When the standard time control signal is sent, the third timing control circuit 63 divides the clock of the frequency fs into the clock of the frequency fc, and creates a timing pulse based on this clock. The solid-state image pickup device 52 is driven by a timing pulse based on the clock of the frequency fc, and the signal is read out. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53, and the frequency f
It is converted into a digital signal by the clock of c. The converted digital signal is sent to the first digital signal processing circuit 54 and subjected to predetermined processing by a timing pulse or the like. The signal from the first digital signal processing circuit 54 is sequentially written in the memory circuit 55 by the clock and timing pulse of the frequency fc.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal.

Next, an example will be described in which the frequency changing means 79 determines that the light quantity of the object detected by the light quantity detecting means 78 is large. The frequency changing means 79 outputs a control signal corresponding to the state in which it is determined that the amount of light is large. The control signal is sent to the third timing control circuit 63. Third
The timing control circuit 63 changes the clock to a speed faster than the standard time by this control signal and creates a timing pulse. The solid-state image sensor 52 is driven by timing pulses based on a clock having a speed higher than that of standard time, and a signal is read out. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by a clock having a speed faster than the standard time. The converted digital signal is sent to the first digital signal processing circuit 54 and subjected to predetermined processing by a timing pulse or the like. The signal from the first digital signal processing circuit 54 is sequentially written in the memory circuit 55 by a clock and a timing pulse that are faster than the standard time.

The second stage after the reading of the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal.

Next, the case where the light quantity of the object detected by the light quantity detecting means 78 is judged by the frequency changing means 79 to be small will be described as an example. The frequency changing means 79 outputs a control signal corresponding to the state in which it is determined that the amount of light is small. The control signal is sent to the third timing control circuit 63.
The third timing control circuit 63 uses this control signal to change the clock to a slower speed than the standard time to create a timing pulse. The solid-state image sensor 52 is driven by timing pulses based on a clock having a speed slower than standard time, and a signal is read out. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by a clock having a speed slower than the standard time.
The converted digital signal is sent to the first digital signal processing circuit 54, and is subjected to predetermined processing by a timing pulse or the like. The signal from the first digital signal processing circuit 54 is sequentially written in the memory circuit 55 by the clock and timing pulse having a slower speed than the standard time.

The second stage from the reading of the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. In this way, when the amount of light of the subject is large, the reading operation from the solid-state image pickup element 52 is accelerated, and the accumulation time for accumulating the photoelectrically converted charges is shortened. When the amount of light is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be automatically changed according to the light amount of the subject.

Example 6. FIG. 8 is a block diagram showing a frequency changing means 79 according to claim 6 of the present invention. In the figure,
Reference numeral 80 is an averaging circuit for averaging the output signals from the light amount detecting means 78, 81 is a first comparing circuit for comparing the averaged signal with a preset first reference level, and 82 is a preset averaged signal. It is a 2nd comparison circuit which compares with a 2nd reference level.

Next, the operation will be described. FIG. 9 is a state diagram for explaining the operation of the frequency changing means 79. The light amount detecting means 78 detects the light amount of the subject and photoelectrically converts it. When the photoelectrically converted electric signal is, for example, as shown in (a) in the figure, the electric signal is averaged by the averaging circuit 80 and becomes as shown in (b) in the figure. The signal (b) averaged by the averaging circuit 80 is sent to the first and second comparing circuits 81 and 82, respectively. The first and second comparison circuits 81 and 82 compare the signal levels of the transmitted signals near the center of the object with the first and second reference levels, respectively. Then, if it exceeds the first and second reference levels, an H level control signal is output, and if it does not reach the first and second reference levels, an L level control signal is output. The signal averaged by the averaging circuit 80 shown in (b) of the drawing is the first signal as shown in (c) of the drawing.
Since the signal level is lower than the reference level and higher than the second reference level, the first comparison circuit 81 outputs an L level signal and the second comparison circuit 82 outputs an H level signal. When the control signal is from the lower level to the L level and the H level, it is determined that the light amount of the subject is in the standard state.

Of the control signals output from the first and second comparison circuits 81 and 82, the output from the first comparison circuit 81 is the lower bit of the control signal. The control signal is sent to the third timing control circuit 63. When the L-level and H-level control signals are sent from the lower order, the third timing control circuit 63 divides the clock of frequency fs into the clock of standard frequency fc, and uses this clock as a reference to generate timing pulses. create. Solid-state image sensor 52
Is driven by the timing pulse based on the clock of the frequency fc, and the signal is read. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by the clock of frequency fc. The converted digital signal is sent to the first digital signal processing circuit 54 and subjected to predetermined processing by a timing pulse or the like. First digital signal processing circuit 5
The signals from 4 are sequentially written in the memory circuit 55 by the clock and the timing pulse of the frequency fc.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. If the output from the light amount detection means 78 is the first and second comparison circuits 8
When both the first and second reference levels in Nos. 1 and 82 are exceeded, the timing pulse created with reference to the clock having a speed higher than the standard time does not exceed both the first and second reference levels. Is output from the third timing control circuit 63 as a timing pulse generated with reference to a clock having a slower speed than the standard time. The timing pulse output according to the light quantity of the subject accelerates the reading operation of the solid-state image sensor 52 when the light quantity is large,
The storage time for storing photoelectrically converted charges is shortened. When the amount of light is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be automatically changed according to the light amount of the subject.

Example 7. FIG. 9 is a configuration diagram showing a combination of the third embodiment and the sixth embodiment according to claim 7 of the present invention. Note that a case where three frequency dividing circuits are provided will be described as an example. In the figure, reference numerals 65, 66 and 67 are frequency dividing circuits having different frequency dividing ratios, 68 is a selector circuit, and 69 is a selector circuit 6.
A second timing generator that creates a timing pulse based on the clock selected in 8, 80 is an averaging circuit that averages the output signals from the light amount detecting means 78, and 81 is a first reference that presets the averaged signal. Reference numeral 82 is a first comparison circuit for comparing with the level, and reference numeral 82 is a second comparison circuit for comparing the averaged signal with a preset second reference level.

Next, the operation will be described. The light quantity of the subject detected by the light quantity detecting means 78 is converted into an electric signal and averaged by the averaging circuit 80 of the frequency changing means 79. The signals averaged by the averaging circuit 80 are input to the first and second comparing circuits 81 and 82, respectively, and are compared with the first and second reference levels. When the level of the input signal is higher than the first and second reference levels, it means that the light amount of the subject is large, and the first and second comparison circuits 81 and 82 output the H level control signal. To be done. Further, when it is lower than the first and second reference levels, it indicates that the amount of light of the subject is small, and the first and second comparison circuits 81 and 82.
Outputs an L level control signal. And the first
When the value is lower than the reference level of and higher than the second reference level, it indicates that the light amount of the subject is in the standard state,
The first comparison circuit 81 outputs an L level control signal, and the second comparison circuit 82 outputs an H level control signal.

A clock of frequency fs is sent from the second timing control circuit 59 to the inputs of the frequency dividing circuits 65, 66 and 67 in the third timing control circuit 63. The frequency dividing circuits 65, 66, 67 divide the clock of the frequency fs with different frequency dividing ratios. The frequency divider circuit 66 has a frequency fc
, The frequency dividing circuit 65 divides the clock into a clock having a shorter cycle than the frequency fc, and the frequency dividing circuit 67 divides into a clock having a longer cycle than the frequency fc. The clock frequency-divided by the frequency dividing circuits 65, 66, 67 is sent to the selector circuit 68. The control signal from the frequency changing means 79 is sent to the selector circuit 68. For example, when L-level and H-level control signals are input from the lower order, the selector circuit 68 selects the clock of the frequency fc divided by the frequency dividing circuit 66 as shown in FIG. When L-level and L-level control signals are input from the lower order, the selector circuit 68 inputs a clock whose period is longer than the frequency fc divided by the frequency divider 67 as H-level and H-level control signals. If so, the selector circuit 68 selects a clock having a cycle shorter than the frequency fc divided by the divider circuit 65.
The second timing generator 69 is a selector circuit 68.
A timing pulse is generated with reference to any clock output from.

When the frequency changing means 79 determines that the light quantity of the subject is in the standard state, the solid-state image pickup device 52 operates at the frequency f.
The signal is read out by being driven by a timing pulse based on the clock of c. The electric signal obtained from the solid-state imaging device 52 is sent to the A / D converter 53 and converted into a digital signal by the clock of the frequency fc. The digital signal is sent to the first digital signal processing circuit 54 and is subjected to predetermined processing by a timing pulse or the like. The signal-processed digital signal is written in the memory circuit 55 with reference to the clock and the timing pulse of the frequency fc.

The second stage after reading from the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. By the timing pulse output from the third timing control circuit 63 according to the light quantity of the subject, the read operation of the solid-state image sensor 52 is accelerated when the light quantity is large, and the accumulation time for accumulating the photoelectrically converted charges is shortened. To do. When the amount of light is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be automatically changed according to the light amount of the subject.

Example 8. FIG. 10 is a block diagram showing a combination of the fourth embodiment and the sixth embodiment according to the invention of claim 8. The case where three frequency dividing circuits are provided will be described as an example. In the figure, 85 is a first frequency dividing circuit for dividing a clock of frequency fs, 86 is a second frequency dividing circuit for dividing a clock divided by the first frequency dividing circuit 85, and 87 is a second frequency dividing circuit. A third frequency dividing circuit for frequency-dividing the clock frequency-divided by the frequency dividing circuit 86, and 88 is a clock for selecting one of the outputs from the first frequency dividing circuit 85 to the third frequency dividing circuit 87. Selector 89 is a third timing generator that creates a timing pulse based on the clock selected by the clock selector 88, 80 is an averaging circuit that averages the output signals from the light amount detector 78, and 81 is an averaged signal. A first comparing circuit 82 for comparing
Is a second comparison circuit for comparing the averaged signal with a preset second reference level.

Next, the operation will be described. The light quantity of the object detected by the light quantity detecting means 78 is photoelectrically converted into an electric signal and averaged by the averaging circuit 80 of the frequency changing means 79.
The signals averaged by the averaging circuit 80 are input to the first and second comparing circuits 81 and 82, respectively, and are compared with the first and second reference levels. The level of the input signal is first
And the second reference level is higher, it means that the light quantity of the subject is large, and the first and second comparison circuits 81 and 8
A control signal of H level is output from 2. Further, the level of the input signal is such that the first and second comparison circuits 81, 8
When it is lower than 2, it indicates that the light amount of the subject is small, and the first and second comparison circuits 81 and 82 output an L level control signal. Then, when it is lower than the first reference level and higher than the second reference level, it indicates that the light quantity of the subject is in the standard state, and the first comparison circuit 8
The control signal of L level is output from 1 and the control signal of H level is output from the second comparison circuit 82.

A clock of frequency fs is sent from the second timing control circuit 59 to the first frequency dividing circuit 85 of the third timing control circuit 63. The input clock is divided by a certain dividing ratio and sent to the second dividing circuit 86. The clock input to the second frequency dividing circuit 86 is frequency-divided by a certain frequency dividing ratio and sent to the third frequency dividing circuit 87. Finally, the output of the third frequency dividing circuit 87 becomes the clock with the longest cycle. The clocks output from the frequency dividing circuits 85, 86 and 87 are sent to the clock selecting means 88. The control signal from the frequency changing means 79 is sent to the clock selecting means 88. For example, when the L-level and H-level control signals are input from the lower order, the clock selection unit 88 divides the clock divided by the second frequency dividing circuit 86, and the L-level and L-level control signals from the lower level. Is inputted, the clock selecting means 88 divides the clock frequency-divided by the third frequency dividing circuit 87 into the first frequency-dividing circuit when the H-level and H-level control signals are inputted. The clock divided by the circuit 85 is selected. The third timing generator 89 creates a timing pulse with reference to any clock output from the clock selection means 88.

When the frequency changing means 79 determines that the amount of light of the subject is in the standard state, the solid-state image pickup device 52 uses the frequency f
The signal is read out by being driven by a timing pulse based on the clock of c. The electric signal obtained from the solid-state imaging device 52 is sent to the A / D converter 53 and converted into a digital signal by the clock of the frequency fc. The digital signal is sent to the first digital signal processing circuit 54 and is subjected to predetermined processing by a timing pulse or the like. The signal-processed digital signal is written in the memory circuit 55 based on the clock and timing pulse of frequency fh.

The second stage from the reading of the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. By the timing pulse output from the third timing control circuit 63 according to the light quantity of the subject, the read operation of the solid-state image sensor 52 is accelerated when the light quantity is large, and the accumulation time for accumulating the photoelectrically converted charges is shortened. To do. When the amount of light is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be automatically changed according to the light amount of the subject.

Example 9. FIG. 11 is a block diagram showing a still image pickup device according to claim 9 of the present invention. In the figure, 2
Is a lens, 52 is a solid-state image sensor, 53 is a solid-state image sensor 5
A / D converter for converting the signal from 2 into a digital signal, 54 is a first digital signal processing circuit for processing the A / D converted digital signal, 55 is a signal from the first digital signal processing circuit 54 A memory circuit for storing 6
Reference numeral 3 denotes a third timing control circuit for performing timing control from the solid-state image sensor 52 to the input of the storage circuit 55, 57
Is a second digital signal processing circuit for processing the digital signal read from the memory circuit 55, 58 is a D / A converter for converting the digital signal from the second digital signal processing circuit 57 into an analog signal, and 59 is A second timing control circuit for performing timing control from the output of the storage circuit 55 to the D / A converter 58, and 79 is a solid-state image sensor 52.
It is a frequency changing means for outputting a control signal for changing the frequency of the clock according to the amplitude level of the signal obtained from.

Next, the operation will be described. The electric signal obtained from the solid-state imaging device 52 is sent to the A / D converter 54 and the frequency changing means 79. Third timing control circuit 6
A clock of frequency fs is sent from the second timing control circuit 59. The cycle of the clock is changed in the third timing control circuit 63. The third timing control circuit 63 creates a timing pulse based on the clock whose period has been changed. When it is determined that the electric signal input to the frequency changing unit 79 has a standard level, for example, a control signal corresponding to the standard state is output. The control signal is sent to the third timing control circuit 63. When the standard time control signal is sent, the third timing control circuit 63 changes the clock of frequency fs to the frequency fc.
It divides into the clock of and the timing pulse is created based on this clock. The solid-state image sensor 52 has this frequency fc
The signal is read out by being driven by the timing pulse based on the clock. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by the clock of frequency fc. The converted digital signal is sent to the first digital signal processing circuit 54, where it is subjected to predetermined processing by a timing pulse or the like. The signal from the first digital signal processing circuit 54 is sequentially written in the memory circuit 55 by the clock and timing pulse of the frequency fc.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal.

Next, a case where the signal from the solid-state image pickup device 52 input to the frequency changing means 79 is at a level where it is determined that the light amount is large will be described as an example. Frequency changing means 79
Outputs a control signal corresponding to the state in which it is determined that the amount of light is large. The control signal is sent to the third timing control circuit 63. In the third timing control circuit 63, the control signal is used to change the clock to a speed faster than the standard time to generate a timing pulse. The solid-state image sensor 52 is driven by timing pulses based on a clock having a speed higher than that of standard time, and a signal is read out. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by a clock having a speed faster than the standard time. The converted digital signal is sent to the first digital signal processing circuit 54, and is subjected to predetermined processing by a timing pulse or the like. The signal from the first digital signal processing circuit 54 is sequentially written in the memory circuit 55 by a clock and a timing pulse that are faster than the standard time.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal.

Next, the case where the signal from the solid-state image pickup device 52 input to the frequency changing means 79 is at a level at which it is judged that the light quantity of the subject is small will be described as an example. The frequency changing means 79 outputs a control signal corresponding to the state in which it is determined that the amount of light is small. The control signal is sent to the third timing control circuit 63. The third timing control circuit 63 uses this control signal to change the clock to a slower speed than the standard time to create a timing pulse. The solid-state image sensor 52 is driven by timing pulses based on a clock having a speed slower than standard time, and a signal is read out. The signal read from the solid-state image sensor 52 is sent to the A / D converter 53 and converted into a digital signal by a clock having a speed slower than the standard time. The converted digital signal is sent to the first digital signal processing circuit 54, and is subjected to predetermined processing by a timing pulse or the like. The signal from the first digital signal processing circuit 54 is sequentially written in the memory circuit 55 by the clock and timing pulse having a slower speed than the standard time.

The second stage from the reading of the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. In this way, when the amount of light of the subject is large, the reading operation of the solid-state image pickup element 52 is accelerated to shorten the accumulation time for accumulating the photoelectrically converted charges. When the amount of light is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be automatically changed according to the light amount of the subject.

Example 10. A still image pickup device according to claim 10 of the present invention is a combination of the third and ninth embodiments. Note that a case where three frequency dividing circuits are provided will be described as an example. The electric signal obtained from the solid-state imaging device 52 is sent to the frequency changing means 79 and averaged by the averaging circuit 80. The signals averaged by the averaging circuit 80 are input to the first and second comparing circuits 81 and 82, respectively, and are compared with the first and second reference levels. When the level of the input signal is higher than the first and second reference levels, it means that the light amount of the subject is large, and the first and second comparison circuits 81 and 82 are shown.
Outputs an H level control signal. Further, when it is lower than the first and second reference levels, it means that the light amount of the subject is small, and the first and second comparison circuits 81 and 8 are shown.
A control signal of L level is output from 2. Then, when it is lower than the first reference level and higher than the second reference level, it indicates that the light amount of the subject is in the standard state,
The first comparison circuit 81 outputs an L level control signal, and the second comparison circuit 82 outputs an H level control signal.

A clock of frequency fs is sent from the second timing control circuit 59 to the inputs of the frequency dividing circuits 65, 66 and 67 in the third timing control circuit 63. The frequency dividing circuits 65, 66, 67 divide the clock of the frequency fs with different frequency dividing ratios. The frequency divider circuit 66 has a frequency fc
, The frequency dividing circuit 65 divides the clock into a clock having a shorter cycle than the frequency fc, and the frequency dividing circuit 67 divides into a clock having a longer cycle than the frequency fc. The clock frequency-divided by the frequency dividing circuits 65, 66, 67 is sent to the selector circuit 68. The control signal from the frequency changing means 79 is sent to the selector circuit 68. For example, when L-level and H-level control signals are input from the lower order, the selector circuit 68 selects the clock of the frequency fc divided by the frequency dividing circuit 66 as shown in FIG. When L-level and L-level control signals are input from the lower order, the selector circuit 68 inputs a clock whose period is longer than the frequency fc divided by the frequency divider 67 as H-level and H-level control signals. If so, the selector circuit 68 selects a clock having a cycle shorter than the frequency fc divided by the divider circuit 65.
The second timing generator 69 is a selector circuit 68.
A timing pulse is generated with reference to any clock output from.

When the frequency changing means 79 determines that the light quantity of the subject is in the standard state, the solid-state image pickup device 52 operates at the frequency f.
The signal is read out by being driven by a timing pulse based on the clock of c. The electric signal obtained from the solid-state imaging device 52 is sent to the A / D converter 53 and converted into a digital signal by the clock of the frequency fc. The digital signal is sent to the first digital signal processing circuit 54 and is subjected to predetermined processing by a timing pulse or the like. The signal-processed digital signal is written in the memory circuit 55 with reference to the clock and the timing pulse of the frequency fc.

The second stage from the reading of the memory circuit 55 is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. By the timing pulse output from the third timing control circuit 63 according to the light quantity of the subject, the read operation of the solid-state image sensor 52 is accelerated when the light quantity is large, and the accumulation time for accumulating the photoelectrically converted charges is shortened. To do. When the amount of light is small, the reading operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be automatically changed according to the light amount of the subject.

Example 11. The still image pickup device according to claim 11 of the present invention is a combination of the fourth and ninth embodiments. Note that a case where three frequency dividing circuits are provided will be described as an example. The electric signal obtained from the solid-state imaging device 52 is input to the frequency changing means 79 and averaged by the averaging circuit 80.
The signals averaged by the averaging circuit 80 are input to the first and second comparing circuits 81 and 82, respectively, and are compared with the first and second reference levels. The level of the input signal is first
And the second reference level is higher, it means that the light quantity of the subject is large, and the first and second comparison circuits 81 and 8
A control signal of H level is output from 2. Also, the first
And the second reference level, the light quantity of the subject is small, and the first and second comparison circuits 81,
A control signal of L level is output from 82. And
When it is lower than the first reference level and higher than the second reference level, it indicates that the light amount of the subject is in the standard state, and the first comparison circuit 81 outputs the L level output from the second comparison circuit 82. Outputs an H level control signal.

A clock of frequency fs is sent from the second timing control circuit 59 to the first frequency dividing circuit 85 of the third timing control circuit 63. The input clock is divided by a certain dividing ratio and sent to the second dividing circuit 86. The clock input to the second frequency dividing circuit 86 is frequency-divided by a certain frequency dividing ratio and sent to the third frequency dividing circuit 87. Finally, the output of the third frequency dividing circuit 87 becomes the clock with the longest cycle. The clocks output from the frequency dividing circuits 85, 86 and 87 are sent to the clock selecting means 88. The control signal from the frequency changing means 79 is sent to the clock selecting means 88. For example, when L-level and H-level control signals are input from the lower order, the clock selecting means 88 uses the clock of frequency fc indicating the standard time divided by the second frequency dividing circuit 86, and from the lower order to the L level. When the control signals of L level and L level are input, the clock selection means 88 outputs the clock divided by the third frequency dividing circuit 87, and when the control signals of H level and H level is input, the clock selection means 88 operates. , The clock divided by the first frequency dividing circuit 85 is selected. The second timing generator 69 is the clock selection means 8
A timing pulse is created with reference to any clock output from 8.

The solid-state image sensor 52 when the light quantity of the subject is judged to be in the standard state by the frequency changing means 79 is
The signal is read out by being driven by a timing pulse based on the clock of c. The electric signal obtained from the solid-state imaging device 52 is sent to the A / D converter 53 and converted into a digital signal by the clock of the frequency fc. The digital signal is sent to the first digital signal processing circuit 54 and is subjected to predetermined processing by a timing pulse or the like. The signal-processed digital signal is written in the memory circuit 55 with reference to the clock and the timing pulse of the frequency fc.

From the reading of the memory circuit 55, the second stage is the second stage.
The timing is controlled by the timing control circuit 59. The second timing control circuit 59 is connected to the storage circuit 55.
The clock generated from the oscillator 62 (hereinafter, frequency f
s clock. The digital signal is read out by a timing pulse or the like created on the basis of (1). The read digital signal is sent to the second digital signal processing circuit 57. The digital signal sent to the second digital signal processing circuit 57 is subjected to predetermined processing by a timing pulse or the like. The digital signal from the second digital signal processing circuit 57 is sent to the D / A converter 58 by the clock of the frequency fs from the second timing control circuit 59 and converted into an analog signal. By the timing pulse output from the third timing control circuit 63 according to the light quantity of the subject, the read operation of the solid-state image sensor 52 is accelerated when the light quantity is large, and the accumulation time for accumulating the photoelectrically converted charges is shortened. To do. When the amount of light is small, the read operation of the solid-state image sensor 52 is delayed to control the accumulation time for accumulating the photoelectrically converted charges to be long. By doing so, the sensitivity can be automatically changed according to the light amount of the subject.

[0089]

According to the first aspect of the present invention, a still image pickup device has N units from the solid-state image pickup device to the input of the memory circuit.
Since the processing is performed at almost the same speed as TSC, high-definition still images can be obtained by using inexpensive parts of NTSC level in the circuits up to the memory circuit.

According to the second aspect of the invention, the speed of the clock serving as the reference for timing control from the solid-state image sensor to the input of the memory circuit is arbitrarily changed according to the light quantity of the object. The sensitivity can be arbitrarily changed according to the light amount to obtain a still image with optimum brightness at all times.

According to a third aspect of the present invention, the clock serving as a reference for timing control from the solid-state image pickup device to the input of the memory circuit is selected from among a plurality of frequency dividing circuits having different frequency dividing ratios. Since the output is selected and varied, the sensitivity can be arbitrarily changed according to the light amount of the subject, and a still image with the optimum brightness can always be obtained.

According to the fourth aspect, the clock serving as a reference for the timing control from the solid-state image pickup device to the input of the memory circuit according to the light quantity of the object is divided by serially connected with the first, second and N clocks. Since the output of each circuit is selected and made variable, the sensitivity can be arbitrarily changed according to the light amount of the subject to obtain a still image with the optimum brightness at all times.

According to the fifth aspect of the invention, the speed of the clock serving as the reference for the timing control from the solid-state image sensor to the input of the memory circuit is automatically changed according to the light quantity of the object detected by the light quantity detecting means. Since it is configured as described above, it is possible to automatically change the sensitivity according to the light amount of the subject and obtain a still image with the optimum brightness at all times.

According to claim 6, the light amount of the object detected by the light amount detecting means is averaged and compared to determine
According to the result, the speed of the clock, which is the reference for timing control from the solid-state image sensor to the input of the memory circuit, is automatically changed. It is possible to always obtain a still image with optimum brightness.

According to a seventh aspect of the present invention, a clock serving as a reference for timing control from the solid-state image pickup element to the input of the memory circuit according to the light quantity of the object detected by the light quantity detecting means is divided into a plurality of clocks having different division ratios. Since it is configured to automatically select and change from any output of the frequency dividing circuit, it is possible to automatically change the sensitivity according to the light amount of the subject and obtain a still image with optimum brightness at all times. .

According to the present invention, a clock serving as a reference for timing control from the solid-state image pickup device to the input of the memory circuit is serially connected to the first, second and Nths in accordance with the light quantity of the object detected by the light quantity detecting means. Since it is configured to automatically select and change from each output of the connected frequency divider circuit, the sensitivity is automatically changed according to the light amount of the subject, and a still image with optimum brightness is always displayed. Obtainable.

According to the ninth aspect, the speed of the clock serving as the reference for the timing control from the solid-state image sensor to the input of the memory circuit is automatically changed according to the amplitude level of the signal obtained from the solid-state image sensor. With this configuration, it is possible to automatically change the sensitivity in accordance with the light amount of the subject and obtain a still image with the optimum brightness at all times.

According to the tenth aspect of the present invention, a plurality of clocks having different frequency division ratios are used as the reference for the timing control from the solid-state image sensor to the input of the memory circuit according to the amplitude level of the signal obtained from the solid-state image sensor. Since it is configured to automatically select and change from any output of the frequency divider circuit of
It is possible to automatically change the sensitivity according to the light amount of the subject and obtain a still image with the optimum brightness at all times.

According to the eleventh aspect, the clock serving as a reference for timing control from the solid-state image sensor to the input of the memory circuit is set to the first, second and Nth points according to the amplitude level of the signal obtained from the solid-state image sensor. Since it is configured to automatically select and change any of the outputs of the divider circuit connected in series, the sensitivity is automatically changed according to the light quantity of the subject, and the still image is always the optimum brightness. Can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a still image capturing apparatus according to claim 1 of the present invention.

FIG. 2 is a block diagram showing a configuration of first and second timing control circuits in FIG.

FIG. 3 is a configuration diagram showing a still image capturing device according to claim 2 of the present invention.

FIG. 4 is a block diagram showing a configuration of a third timing control circuit according to claim 3 of the present invention.

FIG. 5 is a relationship diagram showing a control example of the selector circuit and the clock frequency change instruction means according to claim 3 of the present invention.

FIG. 6 is a block diagram showing a configuration of a third timing control circuit according to claim 4 of the present invention.

FIG. 7 is a configuration diagram showing a still image capturing device according to claim 5 of the present invention.

FIG. 8 is a block diagram showing a configuration of frequency changing means according to claim 6 of the present invention.

FIG. 9 is a state diagram for explaining the operation of the frequency changing means according to claim 6 of the present invention.

FIG. 10 relates to claim 7 of the present invention, and the third aspect of claim 3
7 is a block diagram showing the configurations of the timing control circuit of FIG.

FIG. 11 relates to claim 8 of the present invention, and the third of claim 4
FIG. 7 is a block diagram showing the operation of the timing control circuit and the frequency changing means of claim 6.

FIG. 12 is a configuration diagram showing a still image pickup device according to claim 9 of the present invention.

FIG. 13 is a configuration diagram showing a conventional color imaging device.

FIG. 14 is a configuration diagram showing a configuration of the transmitted light wavelength selection unit of FIG. 13 and a relationship between the transmitted light wavelength selection unit, a lens, and an image sensor.

FIG. 15 is a structural diagram showing a color filter by a conventional transmitted light wavelength selecting means.

FIG. 16 is a timing diagram illustrating an operation of the conventional color image pickup device.

[Explanation of symbols]

2 lens, 52 solid-state imaging device, 53 A / D converter, 54 first digital signal processing circuit, 55 storage circuit, 56 first timing control circuit, 57 second digital signal processing circuit, 58 D / A conversion Device, 59 second timing control circuit, 60 frequency dividing circuit, 61 timing generator, 62 oscillator, 63 third timing control circuit, 64 clock frequency change instruction means,
65, 66, 67 frequency divider circuit, 68 selector circuit, 6
9 second timing generator, 78 light quantity detecting means, 79 frequency changing means, 80 averaging circuit, 81 first comparing circuit, 82 second comparing circuit, 85 first dividing circuit, 86 second dividing circuit , 87 third frequency divider, 88 clock selecting means, 89 third timing generator.

Claims (11)

[Claims] 1. A lens, a solid-state image sensor for converting a subject image formed by the lens into an electric signal, an A / D converter for converting a signal obtained from the solid-state image sensor into a digital signal, and A first digital signal processing circuit for processing the digital signal converted by the A / D converter, a memory circuit for storing the signal from the first digital signal processing circuit, and a signal read from the memory circuit A second digital signal processing circuit for processing
D / A converter for converting a digital signal output from the digital signal processing circuit into an analog signal, a first timing control circuit for performing timing control from the solid-state imaging device to the input of the storage circuit, and the storage A second timing control circuit for controlling the timing from the output of the circuit to the D / A converter, processing at low speed from the solid-state imaging device to the input of the storage circuit, and from the output of the storage circuit. A still image pickup device, characterized in that it processes up to the D / A converter at high speed. 2. A lens, a solid-state image sensor for converting a subject image formed by the lens into an electric signal, an A / D converter for converting a signal obtained from the solid-state image sensor into a digital signal, A first digital signal processing circuit for processing the digital signal converted by the A / D converter, a memory circuit for storing the signal from the first digital signal processing circuit, and a signal read from the memory circuit. A second digital signal processing circuit for processing
A D / A converter for converting a digital signal output from the digital signal processing circuit into an analog signal, a third timing control circuit for performing timing control from the solid-state imaging device to the input of the storage circuit, and the third And a second timing control circuit for controlling the timing from the output of the storage circuit to the D / A converter. The clock frequency change instructing means sends an instruction for changing the frequency of the clock to the third timing control circuit. A still image capturing device characterized by being provided. 3. The third timing control circuit comprises a plurality of frequency dividing circuits having different frequency dividing ratios, a selector circuit for selecting any one of the outputs of the plurality of frequency dividing circuits, and the selector circuit. 3. The still image pickup device according to claim 2, further comprising a second timing generator that creates a timing pulse based on the output clock. 4. The third timing control circuit comprises:
A first frequency dividing circuit for frequency-dividing the clock from the timing control circuit, a second frequency dividing circuit for frequency-dividing the clock output from the first frequency dividing circuit, and N−1 (N = N) 1,
2, 3, ...) Nth frequency divider circuit for dividing the clock output from the frequency divider circuit, and clock selecting means for selecting one of the outputs of the first, second, Nth frequency divider circuits. 3. The still image pickup device according to claim 2, further comprising a third timing generator that creates a timing pulse based on a clock output from the clock selection means. 5. A lens, a solid-state image sensor for converting a subject image formed by the lens into an electric signal, an A / D converter for converting a signal obtained from the solid-state image sensor into a digital signal, and A first digital signal processing circuit for processing a digital signal converted by an A / D converter, a memory circuit for storing a signal from the first digital signal processing circuit, and a digital signal read from the memory circuit. A second digital signal processing circuit for processing a signal, a D / A converter for converting a digital signal output from the second digital signal processing circuit into an analog signal, and an input of the storage circuit from the solid-state imaging device Timing control circuit for performing timing control up to the D / A converter and a second timing control circuit for performing timing control from the output of the storage circuit to the D / A converter. And a frequency changing means for outputting a control signal for changing the frequency of the clock according to the output from the light amount detecting means. Still image pickup device. 6. The frequency changing means includes an averaging circuit for averaging the signals from the light amount detecting means, a first comparing circuit for comparing an output of the averaging circuit with a first reference level, and an output of the averaging circuit. 6. The still image pickup device according to claim 5, further comprising: a second comparison circuit for comparing with the second reference level. 7. A plurality of frequency dividing circuits having different frequency dividing ratios, a selector circuit for selecting any one of the outputs of the plurality of frequency dividing circuits, and a timing pulse based on a clock output from the selector circuit. A third timing control circuit composed of a second timing generator for creating
An averaging circuit for averaging the signals from the light amount detecting means, a first comparing circuit for comparing the output of the averaging circuit with a first reference level, and a second comparing circuit for comparing the output of the averaging circuit with a second reference level. 6. The still image pickup device according to claim 5, further comprising: a frequency changing unit configured with the comparison circuit. 8. A first divider circuit for dividing the clock from the second timing control circuit, and a second divider circuit for dividing the clock output from the first divider circuit. An Nth frequency divider circuit for frequency-dividing the clock output from the N−1th (N = 1, 2, 3, ...) Frequency divider circuit, and the first, second,
Third timing control composed of a clock selecting means for selecting any one of outputs of the N frequency dividing circuit and a third timing generator for producing a timing pulse with reference to a clock output from the clock selecting means. A circuit, an averaging circuit for averaging the signals from the light amount detecting means, a first comparing circuit for comparing the output of the averaging circuit with a first reference level, and an output of the averaging circuit with a second reference level. 6. The still image pickup device according to claim 5, further comprising a frequency changing unit configured with a second comparing circuit for 9. A lens, a solid-state image sensor for converting a subject image formed by the lens into an electric signal, an A / D converter for converting a signal obtained from the solid-state image sensor into a digital signal, A first digital signal processing circuit for processing a digital signal converted by an A / D converter, a memory circuit for storing a signal from the first digital signal processing circuit, and a digital signal read from the memory circuit. A second digital signal processing circuit for processing a signal, a D / A converter for converting a digital signal output from the second digital signal processing circuit into an analog signal, and an input of the storage circuit from the solid-state imaging device Timing control circuit for performing timing control up to and including the second timing control circuit for performing timing control from the output of the storage circuit to the D / A converter. A still image pickup device comprising: a ming control circuit; and a frequency changing means for outputting a control signal for changing a clock frequency according to an amplitude level of a signal obtained from the solid-state image pickup device. 10. A plurality of frequency dividing circuits having different frequency dividing ratios,
Third timing control including a selector circuit that selects one of the outputs of the plurality of frequency divider circuits and a second timing generator that creates a timing pulse based on the clock output from the selector circuit A circuit, an averaging circuit for averaging the signals from the solid-state imaging device, a first comparing circuit for comparing the output of the averaging circuit with a first reference level, and an output of the averaging circuit for a second reference level. The still image pickup device according to claim 9, further comprising a frequency changing unit configured by a second comparing circuit for comparison. 11. A first frequency dividing circuit for frequency-dividing the clock from the second timing control circuit, and a second frequency dividing circuit for frequency-dividing the clock output from the first frequency dividing circuit.
An Nth frequency divider circuit for frequency-dividing the clock output from the N−1th (N = 1, 2, 3, ...) Frequency divider circuit;
Third timing provided with a clock selecting means for selecting any one of the outputs of the frequency dividing circuit of 2 and N and a third timing generator for producing a timing pulse based on the clock output from the clock selecting means. A control circuit, an averaging circuit for averaging the signals from the solid-state imaging device, a first comparing circuit for comparing the output of the averaging circuit with a first reference level, and an output of the averaging circuit for a second reference level. 10. The still image pickup device according to claim 9, further comprising: a frequency changing unit configured by a second comparing circuit for comparing with.