JPH0832525A - Optical reception circuit - Google Patents

Abstract

PURPOSE:To obtain the optical reception circuit operated at a high speed. CONSTITUTION:A collector of a transistor(TR) Q1 is connected to a power supply VCC1, an emitter is connected to a power supply VEE1 via a load resistor RE1 and a base is connected to an anode of a photo diode PD1. A collector of a TR Q2 is connected to a base of the TR Q1, an emitter is connected to the power supply VEE1, and a base is connected to the emitter of the TR Q1. The base of the TR Q1 is connected to the power supply VEE1 via a load resistor RL1. Thus, the charge stored in a parasitic capacitance of the circuit is discharged via the load resistor RL1, then the TR Q1 is turned off at a high speed to attain a high speed operation of the optical reception circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiver circuit.

[0002]

2. Description of the Related Art It is desirable that an optical receiver circuit does not change its turn-on and turn-off times with respect to variations in input light intensity. In general, the light receiving circuit includes a photodetector and a transistor switch circuit, and the photocurrent generated by the photodetector switches the transistor switch circuit. When the input light intensity changes, the photocurrent changes. On the other hand, in the switch circuit, the turn-on / turn-off time changes according to the increase / decrease in the current to drive. Therefore, in order that the turn-on and turn-off times do not change with respect to changes in the intensity of the input light, a constant current means for keeping the current that drives the switch circuit constant is required regardless of the increase or decrease in the photocurrent.

An optical receiving circuit using this constant current converting means is a light receiving I disclosed in Japanese Patent Laid-Open No. 5-152862.
There is C. An example of the light receiving circuit of this light receiving IC is shown in FIG. In this circuit, the current flowing through the load resistor RE at the time of inputting an optical signal is controlled by the transistor Q2 to make it a constant current. That is, even if the photocurrent of the photodiode PD increases or decreases, the current that drives the transistor Q1 is kept constant, thereby suppressing the dependence of turn-on and turn-off times on the input light intensity.

[0004]

FIG. 6 shows a result of simulating an output waveform in the above-mentioned conventional optical receiving circuit with a load resistance RE of 1 kΩ and a parasitic capacitance 1 pF of the photodiode PD. The input photocurrent has a peak value of 2 mA,
Frequency 1MHz, rise and fall time 50n
A square wave of s was input. As a result, it was found that the falling of the output waveform was slow and the operating speed of this optical receiving circuit was limited to about several MHz. That is, it is difficult to apply the conventional optical receiving circuit to optical communication or the like which requires higher speed operation.

As a result of the analysis, the cause of the slow fall is the photodiode PD and the transistors Q1 and Q2.
This is because the voltage between the base and the emitter of the transistor Q1 does not decrease and the transistor Q1 cannot be turned off at high speed because the current path for discharging the electric charge accumulated in the parasitic capacitance such as the wiring at high speed is not set. I understand.

A first object of the present invention is to provide a means for increasing the speed of an optical receiving circuit while making the current for driving the switch circuit constant.

A second object of the present invention is to further speed up the optical receiving circuit in addition to the first object.

[0008]

The first object of the present invention is to:
This can be achieved by connecting the connection point between the first base and the second terminal to the second power source via the second load means.

A second object of the invention is the addition of a first diode with the anode connected to a second bias and the cathode connected to the junction of the first base and the second terminal to provide the input signal The voltage between the first base and the first emitter in the absence thereof is set to be smaller than the voltage between the first base and the first emitter required for the first transistor to be turned on. Can be achieved by setting the bias power supply, the first diode, and the second load means.

[0010]

By connecting the connection point between the first base and the second terminal to the second power source through the second load means, a current for discharging the electric charge accumulated in the parasitic capacitance at high speed. There is a route. As a result, the fall time is shortened, and the optical receiving circuit can operate at high speed.

In order to turn on the first transistor, it is necessary to raise the first base potential until the first transistor is turned on. In order to raise the first base potential, the parasitic capacitance has to be charged. The time for charging the electric charge becomes longer as the potential difference for raising the base potential becomes larger. Therefore, add a diode with the anode connected to the second bias and the cathode connected to the connection point between the first base and the second terminal, and between the first base and the first emitter when there is no input signal. The second bias power supply, the first diode and the second load such that the voltage of the first transistor is smaller than the voltage between the first base and the first emitter required for the first transistor to turn on. Set the means. Thereby, the electric potential of the first base when there is no input is set to an intermediate value between the electric potential of the second power supply and the electric potential of the first base when the first transistor is turned on. That is, since the potential difference that the first base potential has to rise becomes small, the time for charging the parasitic capacitance is shortened. Therefore, the turn-on time of the first transistor is shortened, and the speed of the optical receiving circuit can be further increased.

[0012]

EXAMPLE A first example is shown in FIG. Transistor Q
The collector of 1 is connected to the power supply VCC1 and the emitter is connected to the power supply VEE1 via the load resistor RE1. The connection point between the emitter of the transistor Q1 and the load resistor RE1 is connected to the output terminal OUT1. The base of the transistor Q1 is connected to the anode of the photodiode PD1 and the collector of the transistor Q2. Photodiode PD1
A bias VH1 is applied to the cathode of the. The base of the transistor Q2 is connected to the connection point between the emitter of the transistor Q1 and the load resistor RE1, and the emitter is the power source VEE1.
Connect with. The anode of the photodiode, the base of the transistor Q1 and the collector of the transistor Q2 are connected to the power supply VEE1 via the load resistor RL1.

When an optical signal is input to the photodiode PD1, a photocurrent is generated. This photocurrent is the transistor Q1
Is used to turn on the transistor Q1 and to charge the parasitic capacitance. Then, the surplus photocurrent becomes the collector current of the transistor Q2. When the optical signal input disappears, the charge accumulated in the parasitic capacitance is discharged via the load resistor RL1 and the transistor Q1 is turned off.

In the first embodiment, the load resistance RE1 is 1 kΩ, the load resistance RL1 is 1 kΩ, and the photodiode P is
FIG. 2 shows the result of simulating the output waveform with the parasitic capacitance of 1 pF of D1. The input photocurrent has a peak value of 2 mA, a frequency of 100 MHz, and rise and fall times of 0.
A square wave of 5 ns was input. The transistor was a silicon bipolar transistor. Power supply VCC1 is 3V,
The power supply VEE1 is 0V, the bias VH1 is 3V, the output high level is 0.8V, and the low level is 0V. According to FIG. 2, the optical receiver circuit of the first embodiment has a frequency of 100 MHz.
It can be seen that the optical signal of z can also be received. That is, according to this embodiment, the operating speed can be increased 100 times as compared with the conventional optical receiving circuit.

A second embodiment is shown in FIG. In this embodiment,
In the first embodiment, the anode is connected to the bias VH2,
A diode D1 connected to the anode of the photodiode PD1, the base of the transistor Q1, the collector of the transistor Q2, and the load resistor RL1 is added to the cathode. Here, assuming that the diode D1 is a silicon diode, the forward voltage is 0.8V. Therefore, when the bias VH2 is set to 1.5V, the base potential of the transistor Q1 when there is no input signal is 0.7.
Set to V. The transistor Q1 is turned on when the voltage between the base and the emitter becomes 0.8 V or higher.
Therefore, in the present embodiment, it is sufficient to charge the parasitic capacitance by photocurrent to raise the base potential by 0.1 V, so that the charging time, that is, the turn-on time can be shortened as compared with the first embodiment. it can. The base potential of the transistor Q1 is the forward voltage of the diode D1 and the load resistance.
A desired potential can be set by changing the value of RL1 and the power supply voltage of bias VH2.

In this embodiment, the bias VH2 is 1.
The result of simulating the output waveform at 5 V is shown in FIG. The values and voltage values of the other elements are the same as those in the first embodiment. In FIG. 4, when the solid line is the bias VH2 and the diode D1 is added, the dotted line is the waveform of the first embodiment. It can be seen that the turn-on time is shortened by about 0.5 ns in this embodiment as compared with the first embodiment. That is, according to this embodiment, the speed of the optical receiving circuit can be further increased as compared with the first embodiment.

[0017]

According to the present invention, the current for driving the transistor switch circuit can be made constant and the speed of the optical receiving circuit can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an output waveform diagram of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an output waveform diagram of the second embodiment.

FIG. 5 is a conventional optical receiver circuit diagram.

FIG. 6 is an output waveform diagram of a conventional optical receiver circuit.

[Explanation of symbols]

Q1, Q2 ... Transistors, RE1, RL1 ... Load resistors, PD1 ... Photodiodes, VCC1, VEE1 ...
Power supply, VH1 ... Bias, OUT1 ... Output terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04B 10/06 H03F 3/08 8839-5J

Claims (2)

[Claims] 1. A first photodetector having a first terminal connected to a first bias, a first collector connected to a first power supply, and a first base connected to the first photodetector. A first transistor connected to the second terminal of the first emitter whose first emitter is connected to the second power supply through the first load means, and a second collector connected to the first base and the second base. A second transistor connected to a connection point of a terminal, a second base connected to a connection point between the first emitter and the first load means, and a second emitter connected to the second power supply. In the optical receiving circuit for extracting an output from the connection point between the first emitter and the first load means, the connection point between the first base and the second terminal is connected to the second load means. An optical receiving circuit, characterized in that the optical receiving circuit is connected to the second power source through the above. 2. A second bias, and a first diode having an anode connected to the second bias and a cathode connected to a connection point between the first base and the second terminal. Including a voltage between the first base and the first emitter in the absence of an input signal, the first base and the first emitter required for the first transistor to be in an ON state. An optical receiving circuit in which the second power supply, the first diode, and the second load means are set so as to be smaller than the voltage between them.