JPH0832365A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To improve the frequency characteristic by connecting a source of a FET and an emitter of an NPN transistor(TR) being components of a 2-stage amplifier via a PNP TR so as to suppress the dispersion in a drain current of the FET. CONSTITUTION:An input voltage Vc is amplified by a 2-stage amplifier comprising a FET 4 and an NPN TR5. A source S for grounding the FET 4 is connected to a gate of a PNP TR 6, and an emitter of the TR 5 is connected to an emitter of the TR 6, and a gate G of the FET 4 is fed back via a collector of the TR 6. Thus, the dispersion in the drain current flowing to a drain D of the FET 4 connected to a power supply terminal 3 is suppressed constant independently of the dispersion in the characteristic of the FET 4 and then the frequency characteristic is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit used in the quasi-microwave band to the microwave band.

As an amplifier circuit used in a wireless device such as a mobile communication in the quasi-microwave band to a multiplex radio device in the microwave band, for example, a low noise amplifier is used to reduce a loss and a noise figure in a subsequent stage. There is a demand for an amplifier circuit composed of a two-stage amplifier having a large size.

[0003]

2. Description of the Related Art FIG. 6 shows a conventional amplifier circuit.
This amplifier circuit has good characteristics at high frequencies as well as FET4 which has characteristics such as low noise and high gain at high frequencies.
It is composed of a two-stage amplifier of NPN transistor 5 which can be lower in cost than ET or the like.

The gate (G) of the FET 4 is connected to the input terminal 1 via a direct current blocking (decoupling) capacitor 21 and grounded via a resistor 11.
The source (S) of the FET 4 is grounded via the source resistance 12, and a high frequency bypass capacitor 23 is connected in parallel to the source resistance 12.

Further, the drain (D) of the FET 4 is connected to the base of the NPN transistor 5 via the DC blocking capacitor 26, and is also connected to the power supply terminal 3 via the bias inductor 31. In addition,
A high frequency bypass capacitor 25 is also connected to the power supply terminal 3 with the ground potential.

The base of the NPN transistor 5 has resistors 16 and 17 connected in series between the power supply terminal 3 and the ground potential.
It is connected to a connection point with and its emitter is grounded through an emitter resistor 13.
A high-frequency bypass capacitor 24 is connected in parallel to both ends of 3.

Further, the collector of the NPN transistor 5 is connected to the output terminal 2 via the DC blocking capacitor 22 and also connected to the power supply terminal 3 via the bias inductor 32.

In the operation of such a conventional amplifier circuit, when a signal is input from the input terminal 1, the input signal is an FET operating at the source ground via the capacitor 20.
NP which is amplified by FET4 by being given to the gate of 4 and operates with grounded emitter via capacitor 6.
The signal sent to the base of the N-transistor 5 and further amplified by the NPN transistor 5 is output from the output terminal 2 via the capacitor 22.

Although the gate of the FET 4 is grounded by the resistor 11, the source potential V _{S is changed} to the gate potential V _G by the voltage drop caused by the current flowing through the source resistor 12.
It is made higher and biased by this gate-source voltage V _GS .

On the other hand, a voltage obtained by dividing the power supply voltage from the power supply terminal 3 by the resistors 16 and 17 is applied to the base of the NPN transistor 5 so that a current determined by the emitter resistor 13 flows to the collector of the NPN transistor 5. Is biased to.

[0011]

As described above, the NPN transistor 5 is supplied with a constant bias current by the voltage dividing resistors 16 and 17 and the emitter resistor 13, but operates independently of the NPN transistor 5. F before
The ET4 has a problem that a constant drain current does not flow due to element variation.

This will be described below. FIG. 7A shows the FET 4 shown in FIG.
A linear approximation of the transfer characteristic of T is as shown in FIG. Then, the transfer characteristic is expressed by the following equation.

[0013]

[Equation 1]

Therefore, if the source resistance R _S is determined as shown in FIG. 2B, V _G = 0V, so that the drain current i _DS corresponding to the intersection A between the source resistance R _S and the transfer characteristic of the FET. However, as shown in the figure, F
Since there is variation in the transfer characteristics of ET, the above-mentioned intersection point A is changed to points A ', A "...
As a result, the drain current i _DS also changes as i _{DS ',} i _{DS "} ... And the desired high frequency characteristics are not satisfied.

To keep this drain current constant, F
It is necessary to adjust the resistance value of the source resistance R _S in accordance with the transfer characteristic of ET, which causes a problem that manufacturing takes time.

Therefore, according to the present invention, a constant drain current always flows through the FET in an amplifier circuit having a two-stage amplifier composed of a grounded-source FET having a source resistance and a grounded-emitter NPN transistor having an emitter resistance. The purpose is to

[0017]

In order to achieve the above object, in the amplifier circuit according to the present invention, as shown in principle in FIG.
It is connected to the power supply terminal 3 in common with the collector of the PN transistor 5 and directly to the base of the NPN transistor 5, and the emitter of the NPN transistor 5 and the F
The emitter and the base are connected to the source of ET4 and the collector is connected to the gate of the FET4.
It is characterized in that an NP transistor 6 is provided.

In the above amplifying circuit, the drain of the FET 4 is connected to the NPN transistor 5 via a bias element.
It may be connected to a power supply terminal different from the collector of.

Further, in the above amplifier circuit, the PNP
The emitter of the transistor 6 may be connected to the dividing point of the emitter resistance of the NPN transistor 5.

Further, in the above amplifier circuit, the PNP
The transistor 6 may be a Darlington connection type transistor.

[0021]

In FIG. 1, the signal input from the input terminal 1 is sent to the gate of the FET 4, amplified, and output from the drain terminal. The drain terminal of the FET 4 is directly connected to the base of the NPN transistor 5, and is amplified by the NPN transistor 5 and an output is obtained with the collector as the output terminal 2.

In this case, the base of the NPN transistor 5 is directly connected to the drain of the FET 4 and the drain voltage V
_The collector current is determined by the emitter resistance 13 with _D as the base voltage.

Since the emitter of the PNP transistor 6 is connected to the emitter of the NPN transistor 5 and the base of the PNP transistor 6 is connected to the source of the FET 4, the emitter potential of the NPN transistor 5 is PN.
It is transmitted to the source resistance 12 via the base-emitter voltage of the P-transistor 6, and the source resistance 12 operates as a current source.

Since the collector of the PNP transistor 6 is connected to the gate resistance 11 of the FET 4,
Depending on the collector current of the P-transistor 6, the desired gate
Since the voltage is controlled to be the voltage between the sources, the drain current of the FET 4 is controlled by the emitter potential of the NPN transistor 5, and a desired drain current can be obtained regardless of variations in the transfer characteristics of the FET 4. Become.

This will be explained using mathematical expressions. First, FE
The gate-source voltage V _GS of T4 is expressed by the following equation.

[0026]

[Equation 2]

The following equation is obtained from the operating current of the PNP transistor 6.

[0028]

(Equation 3)

From the above equations (1) to (3), the following equation can be obtained by rearranging the equation for obtaining the drain current i _DS .

[0030]

[Equation 4]

In the above equation, generally R _S << βR _g
And V _P << β · R _g · i _DS and β · R _g · i _DSS , the above equation can be rewritten as follows.

[0032]

(Equation 5)

Thus, if βR _g is sufficiently large, F
The drain current i _{DS of} ET4 is the ratio of the source potential V _S determined by V _EE and V _BE to the source resistance and R _S , but V _EE and V _BE are constant as described above.

Therefore, it is possible to obtain a constant drain current without being affected by variations in the saturation drain current I _DSS and the pinch-off voltage V _P , which are parameters of the transfer characteristic of the FET 4.

In the present invention, if the drain voltage of the FET 4 and the power supply terminal for the collector voltage of the NPN transistor 5 are separated, the collector voltage applied to the NPN transistor 5 can be set arbitrarily, so that the collector-emitter voltage is increased, for example. It can be set, thus realizing a high output amplifier circuit.

Further, by dividing the emitter resistance of the NPN transistor 5 and setting the source potential of the FET 4 small, it becomes possible to increase the drain-source voltage of the FET 4 and increase the output of the amplifier circuit of the FET 4. Can be achieved.

Further, by connecting the PNP transistor 6 to the Darlington connection, since the base-emitter voltage is larger than one transistor, the drain-source voltage of the FET 4 can be set large without increasing the number of parts. Becomes

[0038]

2 shows an embodiment (1) of an amplifier circuit according to the present invention. In this embodiment, the same parts as those in FIGS. 1 and 6 are designated by the same reference numerals.

That is, the DC blocking capacitor 21 is connected between the input terminal 1 and the gate of the FET 4, and the FE
A high frequency bypass capacitor 23 is connected in parallel to the source resistance 12 of T4, and a drain terminal is connected to the power supply terminal 3 via a bias inductor 31 and a resistance 18 as a bias element.

Also in the NPN transistor 5, the high frequency bypass capacitor 24 is connected to the emitter resistor 13.
Are connected in parallel and the collector terminal is the inductor 32
Is connected to the power supply terminal 3 via a DC blocking capacitor 22 and is also connected to an output terminal via a DC blocking capacitor 22.

Further, the collector of the PNP transistor 6 is connected to the gate of the FET 4 via the resistor 14 and grounded via the high frequency bypass capacitor 26. The connection point between the resistor 18 and the inductor 31 is grounded via the high frequency bypass capacitor 25.

In such an embodiment, the signal input from the input terminal 1 is sent to the gate of the FET 4 through the DC blocking capacitor 21 having a sufficiently low impedance in the frequency band used.

The signal amplified by the FET 4 enters the base of the NPN transistor 5 directly connected to the drain of the FET 4 with the inductor 31 having a sufficiently high impedance in the used frequency band as a load, is amplified, and the DC blocking capacitor 22 is supplied from the collector thereof. It is designed to be output to the output terminal via.

In this case, the PNP transistor 6 is the NP
The emitter potential of the N-transistor 5 is passed to the source of the FET 4, and the gate-source voltage V _GS of the FET 4 is controlled by the collector current of the PNP transistor 6 flowing through the resistors 11 and 14.

This resistor 14 has a sufficiently high impedance (for example, 1
It is sufficient to have an electric current of up to 2 KΩ), and it can operate even if it is replaced with an inductor.

The collector current of the PNP transistor 6 is substantially determined by the load resistors 11 and 14, and if these resistance values are about several tens of KΩ, it may be several hundred μA, and the current is branched from the emitter of the NPN transistor 5. But
It does not affect the signal amplification operation.

Thus, according to this embodiment, the FET
Since the drain of No. 4 and the base of the NPN transistor 5 are directly connected, a voltage dividing resistor for applying the base voltage and a capacitor for separating the circuit in terms of DC are not required.

FIG. 3 shows an embodiment (2) of the amplifier circuit according to the present invention. This embodiment and the embodiment (1) shown in FIG. 2 are the drain voltage of the FET 4 and the NPN transistor 5. The collector voltages are power terminals 3 and 3 ', respectively.
The difference is that it is separated into
Since the collector voltage applied to the transistor 5 can be arbitrarily set, a high output amplifier circuit can be realized by setting a large collector-emitter voltage, for example.

FIG. 4 shows an embodiment (3) of the amplifier circuit according to the present invention. The difference between this embodiment and the embodiment (1) shown in FIG. 2 is that the emitter resistance of the NPN transistor 5 is two. This is a point where the resistors 13 and 13 'are divided into two parts, and the source potential of the FET 4 is set low by connecting the connection point of the resistors 13 and 13' and the emitter of the PNP transistor 6. Therefore, the voltage between the drain and the source of the FET 4 can be increased by the above formula, which is effective in increasing the output of the amplifier circuit of the FET 4.

FIG. 5 shows an embodiment (4) of the amplifier circuit according to the present invention. The difference between this embodiment and the embodiment (1) shown in FIG. 2 is that the PNP transistor 6 is of the Darlington connection type. The point is that it is transformed into a transistor 6 ', and since the base-emitter voltage of this Darlington connection type transistor 6'is larger than one transistor, the drain-source voltage of the FET 4 should be increased without increasing the number of parts. Therefore, the output of the FET 4 can be increased as in the case of the embodiment (3).

[0051]

As described above, according to the amplifier circuit of the present invention, the drain of the FET is N
The collector of the PN transistor is connected to a common or another power supply terminal and is directly connected to the base of the NPN transistor, and the emitter of the NPN transistor and the F
Emitter of PNP transistor between source of ET
Since the bases are connected and the collector of the PNP transistor is connected to the gate of the FET, variations in the drain current of the FET can be suppressed and stable high-frequency characteristics can be obtained without increasing the circuit scale. Therefore, it is possible to contribute to the realization of a high-performance communication device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing in principle the configuration of an amplifier circuit according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment (1) of an amplifier circuit according to the present invention.

FIG. 3 is a circuit diagram showing an embodiment (2) of an amplifier circuit according to the present invention.

FIG. 4 is a circuit diagram showing an embodiment (3) of an amplifier circuit according to the present invention.

FIG. 5 is a circuit diagram showing an embodiment (4) of the amplifier circuit according to the present invention.

FIG. 6 is a circuit diagram showing a conventional amplifier circuit.

FIG. 7 is a diagram for explaining the characteristics of the FET.

[Explanation of symbols]

 1 Input terminal 2 Output terminal 3,3 'Power supply terminal 4 FET 5 NPN transistor 6,6' PNP transistor 12 Source resistance 13,13 'Emitter resistance 18 Bias resistance In the figure, the same code | symbol shows the same or corresponding part.

Claims (4)

[Claims] 1. A grounded source FET having a source resistance.
And a grounded-emitter NPN transistor having an emitter resistance, in a two-stage amplifier circuit, the drain of the FET is connected to a power supply terminal in common with the collector of the NPN transistor via a bias element, and the NPN transistor is connected. Is directly connected to the base of
An amplifier circuit comprising a PNP transistor having an emitter-base connection between the emitter of the NPN transistor and a source of the FET and a collector connected to the gate of the FET. 2. The amplifier circuit according to claim 1, wherein the drain of the FET is connected to a power supply terminal different from the collector of the NPN transistor via a bias element. 3. The amplifier circuit according to claim 1, wherein an emitter of the PNP transistor is connected to a dividing point of an emitter resistance of the NPN transistor. 4. The amplifier circuit according to claim 1, wherein the PNP transistor is a Darlington connection type transistor.