JPH08321731A - Bias current source circuit and differential amplifier - Google Patents

Abstract

PURPOSE: To make the area of an integrated circuit by connecting an analog basic circuit individually so as to supply or extract a bias current corresponding to a multi-stage mirror circuit. CONSTITUTION: A voltage Va divided by a PMOS transistor(TR) 1 and an NMOS TR 2 is fed to gates of PMOS TRs 3-6 being components of a mirror circuit for bias current supply and NMOS TRs 7-10 being components of a bias current extract mirror circuit. Then a bias current fed to each analog circuit is generated. Thus, it is possible to have provision for change in the number of analog basic circuits attended with entire specification change by changing the number of PMOS TRs 3-6 and NMOS TRs 7-10. Furthermore, the number of PMOS TRs 1 and NMOS TRs 2 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias current source circuit for outputting or drawing a bias current to a large number of analog basic circuits and a differential amplifier using the bias current source circuit.

[0002]

2. Description of the Related Art The structure of a conventional differential amplifier is shown in FIGS. FIG. 4 shows PMOS transistors 100 and 10.
3, 104 and NMOS transistors 101, 102
2 shows a differential amplifier including a circuit for turning on / off an operation including a PMOS transistor that supplies a bias current to the differential amplifier when the circuit is in an operating state. A bias current source composed of 105 and NMOS transistors 115 and 116 is attached. When the “Low” voltage is applied to the input terminal 123, the PMOS transistors 103 and 104 are turned on because GND (0 V) is applied to the gates of the PMOS transistors 103 and 104. In addition, the gates of the NMOS transistors 102 and 114 are connected to the PMOS transistor 100 and the NMOS that form the first-stage inverter.
Since the output VDD (+ 5V) of the transistor 101 is applied, the NMOS transistors 102 and 114 are turned on. From this, the PMOS transistors 106, 10
Output VDD (+ 5V) to the gate of 7, 108, 113
But NMOS transistors 115, 116, 117, 1
Since GND (0 V) is applied to the gate of 19, the MOS transistors 106, 107, 108, 11
3, 115, 116, 117, and 119 are all off. That is, when the “Low” voltage is applied to the input terminal 123, the differential amplifier of FIG. 4 is in a non-operating state. On the contrary, when "High" is applied to the input terminal 123,
Transistors 103 and 104 and NMOS transistor 1
02 and 114 are turned off, and the PMOS transistor 1
05 is turned on and the PMOS transistor 105 is connected to NM
When the bias current flows into the OS transistors 115, 116 and 118, the differential amplifier shown in FIG. 4 is put into operation.

The differential amplifier is an NMOS transistor 11
1, a differential input circuit composed of 112, a mirror circuit composed of PMOS transistors 109 and 110, and a differential amplifier circuit composed of a PMOS transistor 118, an output circuit composed of an NMOS transistor 113 and a PMOS transistor 119, and a phase compensation capacitor 122. Composed of and. In addition, VINP is a positive input terminal, VINN is a negative input terminal,
OUT is an output terminal.

Unlike the differential amplifier shown in FIG. 4, the differential amplifier shown in FIG. 5 does not have a circuit on / off function but has only a bias current source composed of a PMOS transistor 130 and an NMOS transistor 137. . The differential amplifier includes a differential input section including NMOS transistors 135 and 136, a differential amplifier circuit including a mirror circuit including PMOS transistors 131 and 132, and a PMOS transistor 138, and NMOS transistors 133 and 1.
An output circuit including 34 and 140 and a PMOS transistor 139, and a phase compensation capacitor 143.

[0005]

The problem of the above-mentioned conventional example is that when a large number of these differential amplifiers are used to construct an analog circuit, the differential amplifier of FIG. 4 has an on / off circuit and a bias current source, Since the bias current source is attached to the differential amplifier in FIG. 5, when a large number of differential amplifiers are integrated, there is a problem that the area of the entire integrated circuit becomes large. . Particularly, in the bias current source, the resistance component of the PMOS transistor and the NMOS transistor determines the bias current value. Therefore, the MOS transistor used as the current source of the small-signal amplification circuit unit has a larger scale than the MOS transistor forming the amplification circuit unit. Transistors will be used. In the case where the operational amplifier shown in FIG. 4 is provided with an on / off circuit, the output voltage becomes unstable when the circuit state shifts from the operating state to the non-operating state, and the output is input to the comparator. However, there is a problem that even after that, the circuit after the comparator may malfunction.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a bias current source circuit capable of reducing the circuit area when integrated. To provide. The invention of claim 2 relates to claim 1
In another aspect of the invention, there is provided a bias current source circuit capable of turning on and off a bias current to be output.

According to a third aspect of the present invention, in the configuration in which the bias current is supplied from the bias current source circuit according to the first or second aspect of the invention, the output voltage is forced when the bias current is cut and becomes inoperative. Is to realize a differential amplifier that can be set to 0V.

[0008]

According to the invention of claim 1, N
It has a multistage mirror circuit composed of a MOS transistor and a PMOS transistor, and an analog basic circuit is connected to each of the mirror circuits so as to apply or extract a bias current corresponding to each mirror circuit. According to a second aspect of the present invention, in the first aspect of the present invention, a resistance component is used to generate a voltage applied to the gates of the NMOS transistor and the PMOS transistor used in each of the mirror circuits. A first PMOS transistor is connected in parallel with a second PMOS transistor for controlling on / off of a bias current.

According to a third aspect of the present invention, in the differential amplifier connected to the mirror circuit of the bias current circuit according to the second aspect and operated by receiving the bias current, an NMOS transistor is connected in parallel to the output terminal. By controlling the gate voltage of the NMOS transistor, the output voltage is forcibly set to 0V when the bias current from the bias current source circuit is cut and the non-operation state is set.

[0010]

According to the present invention, there is provided a multistage mirror circuit composed of NMOS transistors and PMOS transistors, and an analog basic circuit is separately provided for applying or extracting a bias current corresponding to each mirror circuit. Since it is connected, the PMOS transistor that supplies the bias current of the mirror circuit and the N that extracts the bias current
By changing the number of MOS transistors arranged, it is possible not only to cope with the variation in the number of analog basic circuits used due to the specification change of the entire circuit to be used, but also to use the PMOS transistors and N
Since the number of MOS transistors can be reduced, it is possible to reduce the area of the entire circuit when integrated with the analog basic circuit.

According to the invention of claim 2, in the invention of claim 1, the NMOS used in each of the mirror circuits.
Since the second PMOS transistor is connected in parallel to the first PMOS transistor provided so as to utilize the resistance component to generate the voltage applied to the gates of the transistor and the PMOS transistor, the second P
By controlling the gate voltage of the MOS transistor, the bias current output from each mirror circuit is turned on,
Can be switched off.

According to the invention of claim 3, in the differential amplifier connected to the mirror circuit of the bias current circuit of claim 1 or 2 and operated by receiving the bias current,
By connecting an NMOS transistor in parallel with the output terminal and controlling the gate voltage of the NMOS transistor, the output voltage is forced when the bias current from the bias current source circuit is cut off to bring it into a non-operating state. Since the bias current supplied from the bias current source circuit is cut and the output voltage is forcibly set to 0 V, the malfunction of the circuit using the output of the differential amplifier is caused. Can be prevented.

[0013]

EXAMPLES The present invention will be described below with reference to examples. (Embodiment 1) FIG. 1 shows the present embodiment corresponding to the invention of claim 1, which is a PMOS for resistively dividing a power supply voltage.
P of the transistor 1 and the NMOS transistor 2
The MOS transistor 1 has a source connected to VDD (+ 5V) and a drain connected to the drain of the NMOS transistor 2,
The source of the NMOS transistor 2 is connected to GND (0V), and the gates and drains of the PMOS transistor 1 and the NMOS transistor 2 are commonly connected.

The PMOS transistors 3, 4, 5 and 6 each constituting a mirror circuit for supplying bias current have their sources connected to VDD (+ 5V) and their drains to the bias current supply terminals IP1, IP2, IP3 and IP4. Each is connected. The NMOS transistors 7, 8, 9 and 10 which form the mirror circuit for extracting the bias current have their sources connected to GND (0V) and their drains connected to the bias current extracting terminals IM1, IM2, IM3 and IM4, respectively. . PMOS transistor 1 and NMOS
Drain of transistor 2 and PMOS transistor 3,
4, 5, 6 and NMOS transistors 7, 8, 9, 1
It is commonly connected to the 0 gate.

Thus, the PMOS transistor 1 and the NMOS
The voltage Va divided by the transistor 2 is applied to the gates of the transistors 3, 4, 5, 6 and 7, 8, 9, 10 of the PMOS and NMOS constituting the mirror circuit, and is supplied to the analog circuits. To occur. As described above, even if the number of analog circuits is changed by changing the use of the entire analog circuit, the adjustment can be easily performed by adding or removing the PMOS transistor and the NMOS transistor.

(Embodiment 2) FIG. 2 shows a circuit of this embodiment corresponding to the invention of claim 2, and the circuit of this embodiment shows a method of making a bias current to be supplied to each analog circuit and a circuit operation. 1 is the same as the bias current source circuit of FIG. 1 except that the PMOS transistor 11 is connected in parallel to the PMOS transistor 1 of FIG. When the bias current is output in the circuit of this embodiment, the input terminal 12 is a PMOS.
A voltage is applied so that the transistor 11 is turned off. In that case, PMOS transistors 3, 4, 5, 6
The voltage Vb output from the resistance division circuit composed of the PMOS transistor 1 and the NMOS transistor 2 is applied to the gate of the. When the bias current is cut, the whole circuit operation is set so that 0 V is input to the input terminal 12. Then, when the voltage applied from the input terminal 12 is lowered and the PMOS transistor 11 is turned on, a current flows in from the power supply line VDD (+ 5V), and charges are accumulated in the gates of the PMOS transistors 3, 4, 5, and 6, so that the PMOS transistor 11 is turned on. 3, 4, 5 and 6 are turned off and the bias current is cut. With such a structure, the circuit for cutting the operation, which is arranged in the differential amplifier shown in FIG. 4, is not necessary, and the area can be reduced.

(Embodiment 3) FIG. 3 shows a circuit of a differential amplifier of the present embodiment corresponding to the invention of claim 3. In the figure, NMOS transistors 55 and 56 form a differential input section, and PMOS transistors 51 and 52 and NMO are formed.
Each of the S transistors 58, 59, 60 constitutes a mirror circuit. The capacitor 57 is a capacitor for phase compensation. The input terminal 67 is a terminal for inputting the bias current from the bias current source circuit of the second embodiment (or 1), and when the bias current from the bias current source circuit is cut off, the current applied to the input terminal 67 is also Therefore, it is cut. Then, the operation of the differential amplifier is also turned off. In this case, since the output voltage of the output terminal POUT becomes unstable, it is necessary to apply a voltage to the extent that the NMOS transistor 62 is turned on from the gate voltage input terminal 66 of the NMOS transistor 62 connected to the output terminal OUT of the differential amplifier. The output is forcibly set to GND (0V) when the entire circuit is operated and the differential amplifier is in a non-operating state. Therefore, it is possible to prevent malfunction of, for example, the comparator to which the output of the differential amplifier is input and the entire circuit in which the differential amplifier is used. The output circuit is MOS transistors 53, 54, 61 and PM.
It is composed of the OS transistor 60.

[0018]

According to the present invention, there is provided a multistage mirror circuit composed of an NMOS transistor and a PMOS transistor, and an analog basic circuit is separately provided for applying or extracting a bias current corresponding to each mirror circuit. Since it is connected, the PMOS transistor that supplies the bias current of the mirror circuit and the N that extracts the bias current
By changing the number of MOS transistors arranged, it is possible not only to cope with the variation in the number of analog basic circuits used due to the specification change of the entire circuit to be used, but also to use the PMOS transistors and N
Since the number of MOS transistors can be reduced, there is an effect that the area of the entire circuit when integrated with the analog basic circuit can be reduced.

According to a second aspect of the invention, in the first aspect of the invention, the resistance component is used to generate the voltage applied to the gates of the NMOS transistor and the PMOS transistor used in each of the mirror circuits. A second P is provided in parallel with the provided first PMOS transistor.
Since the MOS transistor is connected, the second PMOS
By controlling the gate voltage of the transistor, the bias current output from each mirror circuit can be switched on and off.

According to a third aspect of the present invention, in a differential amplifier connected to the mirror circuit of the bias current circuit according to the first or second aspect and operated by receiving a bias current, an NMOS is provided in parallel with an output terminal. Connect the transistor,
By controlling the gate voltage of the MOS transistor, the output voltage is forcibly set to 0 V when the bias current from the bias current source circuit is cut and becomes inoperative, so that it is supplied from the bias current source circuit. By forcing the output voltage to 0 V when the bias current is cut and the device is in the non-operating state, it is possible to prevent the malfunction of the circuit using the output of the differential amplifier.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a bias current source circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a bias current source circuit of a second embodiment corresponding to the invention of claim 2;

FIG. 3 is a circuit diagram of a differential amplifier of a third embodiment corresponding to the invention of claim 3;

FIG. 4 is a circuit diagram of a conventional differential amplifier.

FIG. 5 is a circuit diagram of another conventional differential amplifier.

[Explanation of symbols]

 1 to 6 PMOS transistor 7 to 10 NMOS transistor IP1 to IP4 Bias current supply terminal IM1 to IM4 Bias current extraction terminal

Claims (3)

[Claims] 1. A multi-stage mirror circuit composed of an NMOS transistor and a PMOS transistor is provided, and an analog basic circuit is connected to each of the mirror circuits so as to apply or extract a bias current corresponding to each mirror circuit. Bias current source circuit. 2. An NMO used in each of the mirror circuits.
A second PMOS transistor for controlling on / off of a bias current in parallel with a first PMOS transistor provided so as to use a resistance component to generate a voltage applied to the gates of the S transistor and the PMOS transistor. 2. The bias current source circuit according to claim 1, further comprising: 3. A differential amplifier connected to the mirror circuit of the bias current circuit according to claim 1 or 2 and operated by receiving a bias current, wherein N is provided in parallel with the output terminal.
By connecting a MOS transistor and controlling the gate voltage of the NMOS transistor, the output voltage is forcibly set to 0 V when the bias current from the bias current source circuit is cut off to bring it into a non-operating state. And a differential amplifier.