JPH08320743A - Information equipment - Google Patents

Abstract

PURPOSE: To suppress the unnecessary consumption of a battery due to a leak current from an integrated circuit which is fed with electricity in power-down mode even as to the information equipment which has the power-down mode. CONSTITUTION: In the power-down mode, the integrated circuit 38, a memory 37, and a CPU 36 are fed with electricity and none of an integrated circuit 39, an LCD 40, and a keyboard 41 is not fed with the electricity, so that the electric power of the battery 31 is prevented from being consumed. A power- down signal 42 is generated in this power-down mode and the output of the integrated circuit 38 supplied with the electric power enters a high-impedance state, so the unnecessary consumption of the power supply due to the leak current from the integrated circuit is suppressed and the information equipment is obtained which is usable for a longer period with a power source with the same capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information device, and more particularly to an information device provided with an integrated circuit which is fed with power and a non-power fed integrated circuit in a power down mode.

[0002]

2. Description of the Related Art In information equipment represented by a notebook personal computer and an electronic notebook, one of the important performances is how long the battery can be used with a limited battery capacity. For this reason, products having a power-down mode that suppresses power consumption have been realized. In the power-down mode, power is supplied only to the CPU, memory, etc. necessary for data retention and the like, and processing for turning off power to peripheral circuits unnecessary for operation is performed, thereby suppressing power consumption.

[0003]

However, when an integrated circuit which is supplied with power and an integrated circuit which is not supplied with power are mixed in the same device and the signal lines are connected to each other, the power is supplied. Leakage current flows to an integrated circuit to which power is not supplied from the integrated circuit. As a result, the battery is consumed unnecessarily, and the use time of the device and the data holding time are shortened.

The present invention has been made to solve such a drawback, and an object of the present invention is to provide an information device capable of further preventing power consumption in the power down mode.

[0005]

According to the present invention, in order to solve this problem, in an information device including an integrated circuit to which power is supplied and an integrated circuit to which power is not supplied in a power down mode, Structure comprising means for generating a power down signal indicating a power down mode in the down mode, and means for controlling an output of an integrated circuit to which power is supplied in the power down mode to a high impedance state by the power down signal It was adopted.

[0006]

In such a configuration, the power down signal indicating the power down mode is generated in the power down mode, and the output of the integrated circuit to which power is supplied in response to the power down signal is in a high impedance state. Controlled to be. Therefore, it is possible to suppress the unnecessary consumption of the power source due to the leakage current from the integrated circuit, and to provide the information device which can be used for a long time with the power source having the same capacity.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings.

1 and 2 show a first embodiment of the present invention. FIG. 1 is a block diagram of the entire apparatus.
The battery voltage from the battery 31 that is the power source of the device is DC-D.
It is converted into an appropriate voltage by the C converter 32. DC
The DC converter 32 is connected with switch circuits 34 and 35 which are respectively controlled by the power supply control circuit 33. When the switch circuit 34 is turned on by the power supply control circuit 33, the DC-DC converter 32 supplies the power supply VCC.
(1) is supplied to the integrated circuit 38, the memory 37, and the CPU 36, while the power supply control circuit 33 causes the switch circuit 35 to be supplied.
Is turned on, the power supply VCC (2) is supplied from the DC-DC converter 32 to the integrated circuit 39, LCD (liquid crystal display),
It is supplied to the keyboard 41.

The power supply control circuit 33 is provided with a power down mode operation switch 43. When the switch 43 is operated, the power down mode is set, and the switch 3 is turned on.
When 5 is turned off, a power down signal 42 is generated and this power down signal is input to the integrated circuit 38.

As shown in detail in FIG. 2, the integrated circuit 38 has a latch circuit 21 at its connecting portion,
The output signal is output to the output terminal 23 via the output buffer 22.
Be led to. The signal from the output terminal 23 is guided to the output terminal 25 of the integrated circuit 39 via the signal line 27 and taken into the integrated circuit 39 via the input buffer 26. Also,
The integrated circuit 38 has an input terminal 24, and a power down signal 42 is input to this terminal. In the power down mode, the power down signal 42 becomes active (“L” state), and the output buffer 22 becomes high impedance state. On the other hand, when not in the power down mode, the power down signal 42 becomes inactive (“H” state), and the output buffer 22 becomes low impedance state.

Next, the operation of the apparatus having such a configuration will be described.

Now, when the device is operating in the normal mode, power is supplied to all circuits of the device. That is, the switch circuit 34 and the switch circuit 35 are both turned on by the power supply control circuit 33, and the integrated circuit 38, the memory 37, and the CPU 36 are powered by the power supply VCC (1), while the integrated circuit 39, the LCD 40, and the keyboard 41 are powered by the power supply VCC (1). Powered by 2).

At this time, the power down signal 42 is "H".
The level is inactive, that is, the output buffer 22 is in a low impedance state, and the output signal from the output buffer is output from the output terminal 23. This flows into the input buffer 26 through the input terminal 25 of the integrated circuit 39.

Next, when the power down mode operation switch 43 is operated and turned on, the power supply control circuit 33 detects this and puts the system into the power down mode. That is, the switch circuit 34 remains on and the power supply VCC
Although (1) is continuously supplied to each circuit or element, the switch circuit 35 is turned off, the power supply VCC (2) is turned off, and the integrated circuit 39, the LCD 40, and the keyboard 41 are unpowered. Further, the power-down signal 42 becomes active and becomes "L" level, and the output buffer 22 is brought into a high impedance state. Since the output buffer 22 is in the high impedance state, the output terminal 23 to the input terminal 25
The current flowing through the input buffer 26 via the above is cut, and an unnecessary leakage current is prevented from flowing from the integrated circuit 38 to the integrated circuit 39.

Next, a second embodiment of the present invention is shown in FIG.
This embodiment is an example in which a microcomputer is used for the power supply control circuit in the first embodiment. The microcomputer 61 includes a CPU 62 and an R that stores a program.
An OM 63, a RAM 64 for storing data, an A / D converter 65, and an I / O port 66. Also, DC-D
From the C converter 32, voltage or power supply VCC (1), V
CC (2) is supplied to each circuit or element of FIG. 1 through switch circuits 34 and 35 which are turned on / off by a signal from an I / O port 66 of the microcomputer 61. A power down signal 42 is output from the I / O port.

In such a configuration, the CPU 62 is
When the voltage of the battery 31 drops below a certain voltage according to a predetermined program stored in the ROM 63 in advance, the entire system is set to the power down mode. That is, the voltage of the battery 31 is monitored at regular intervals by the A / D converter 65, it is determined that the power-down mode should be entered when this voltage drops below a predetermined voltage, and the I / O port 66 is used. The switch circuit 34 is kept on and the switch circuit 35 is turned off. As a result, the integrated circuit 39, LCD 40, and keyboard 41 are de-powered. Further, the power-down signal 42 is brought into the active state, that is, the “L” level, which brings the output buffer 22 of the integrated circuit 38 into the high impedance state. Thereby, the integrated circuit 38 to the integrated circuit 3
It is possible to prevent an unnecessary leakage current from flowing to 9.

In each of the above-described embodiments, one output terminal of the integrated circuit is set to the high impedance state in the power down mode, but all other output terminals of the integrated circuit or selected output terminals are set to the high impedance state. You may do it.

[0018]

As described above, according to the present invention, in an information device having a power down mode, a power down signal is generated in the power down mode, and power is supplied in the power down mode by this power down signal. Since the output terminal of the integrated circuit is set to a high impedance state, unnecessary battery consumption due to leakage current from this integrated circuit can be suppressed, and a portable device that can be used for a longer period of time can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a first embodiment.

FIG. 2 is a circuit diagram showing an internal configuration example of a connecting portion of the integrated circuit in the first embodiment.

FIG. 3 is a block diagram showing a configuration in which a microcomputer controls power supply in a second embodiment.

[Explanation of symbols]

 31 battery 32 DC-DC converter 33 power supply control circuit 34, 35 switch circuit 36 CPU 37 memory 38, 39 integrated circuit 40 LCD 41 keyboard

Claims (4)

[Claims] 1. A means for generating a power down signal indicating a power down mode in a power down mode in an information device including an integrated circuit to which power is supplied in the power down mode and an integrated circuit to which power is not supplied. And a means for controlling the output of the integrated circuit, which is supplied with power in the power-down mode by the power-down signal, to a high impedance state. 2. The information device according to claim 1, wherein the power-down signal is generated by operating a switch. 3. The information device according to claim 1, wherein the power down signal is generated by a microcomputer. 4. The information device according to claim 1, wherein the power down signal is generated when the battery is exhausted.