JPH08320740A - Power circuit of portable information processor - Google Patents

Power circuit of portable information processor

Info

Publication number
JPH08320740A
JPH08320740A JP7126508A JP12650895A JPH08320740A JP H08320740 A JPH08320740 A JP H08320740A JP 7126508 A JP7126508 A JP 7126508A JP 12650895 A JP12650895 A JP 12650895A JP H08320740 A JPH08320740 A JP H08320740A
Authority
JP
Japan
Prior art keywords
power
power supply
portable information
circuit
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7126508A
Other languages
Japanese (ja)
Inventor
Yoshiki Yamada
嘉樹 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7126508A priority Critical patent/JPH08320740A/en
Publication of JPH08320740A publication Critical patent/JPH08320740A/en
Pending legal-status Critical Current

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  • Power Sources (AREA)

Abstract

PURPOSE: To provide a power unit which delays the timing of electricity feeding to respective device and is designed with relatively small power source capacity by varying the constant values of the resistance and capacitor of a power source controller consisting of the resistance and capacitor. CONSTITUTION: Of the power circuit of the portable information processor, a device 1 connects with a main substrate, a device 2 connects with a hard disk, and a device 3 connects with a device which consumes large electric power like a floppy disk. As circuits which control the power sources of the respective devices 1-(n), the device 1 consists of a circuit composed of a resistance R1 and a capacitor C1, the device 2 consists of a circuit of R2 and C2, and a device (n) consists of a circuit of Rn and Cn. Those device require peak currents almost at the same time, so the constants of R1-Rn and C1-Cn are made different to supply electric power to the devices 1-(n) at different time, thereby saving the electric power.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はノートブックやパームト
ップパソコンなどのように軽量、小型化が要求されるパ
ソコンにおいて、電源に必要以上に余裕を持たせること
なく、また、コスト的に安価で調整のための変更も容易
なRC時定数による遅延を利用して、システム起動時、
リジューム時等デバイスに電源が印加される際に、各デ
バイスの電源投入タイミングを少しずつずらすことによ
って、各デバイスの消費電流のピークが重なることを防
ぎ、この結果必要最小限の能力の電源で各デバイスの起
動時の電源電圧の落ち込みを防ぎ、安全なリジュームを
実現する携帯型情報処理装置の電源回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention can be applied to a personal computer such as a notebook or a palmtop personal computer, which is required to be lightweight and small in size, without making the power supply have an unnecessarily large margin and at low cost. Utilizing the delay due to the RC time constant, which can be easily changed for adjustment, at system startup,
When power is applied to a device when it is resumed, by slightly shifting the power-on timing of each device, it is possible to prevent the peaks of the current consumption of each device from overlapping, and as a result, use the power supply with the minimum required capacity. The present invention relates to a power supply circuit of a portable information processing device that prevents a power supply voltage from dropping at the time of device startup and realizes a safe resume.

【0002】[0002]

【従来の技術】従来の携帯型情報処理装置の電源回路に
おいては、ノートブックパソコン、パームトップパソコ
ン等電池駆動のパソコンは小型軽量化が要求され、電源
部にも省スペース化が要求される。したがって、システ
ム起動時等各デバイスに対して電源が与えられるときに
は、各デバイスのピーク電流が一斉に流れることにな
る。また、これらのパオコンはパワーセーブの手段とし
てサスペンド等の機能を有しており、必要に応じて各デ
バイスの電源をオンオフすることができる。したがっ
て、サスペンド時には可能な限りのデバイスの電源をオ
フすることによって低消費電力化を図ることになる。逆
にリジューム時にはこれらのオフされたデバイスの電源
が一斉にオンされることになり、このときの急激な負荷
変動にも追従できるだけの能力が電源に要求される。こ
のため、従来は、 (1)電源能力に余裕を持たせる。 この方法は各デバイスの起動時のピーク電流の合計の電
流が供給可能な電源設計を行うもので、通常使用時の最
大電流より大きな容量の電源にするものである。
2. Description of the Related Art In a power supply circuit of a conventional portable information processing device, a battery-operated personal computer such as a notebook personal computer or a palmtop personal computer is required to be small and lightweight, and a power source section is also required to be space-saving. Therefore, when power is supplied to each device at the time of system startup, the peak current of each device flows simultaneously. Further, these computers have a function such as suspend as a means for power saving, and the power of each device can be turned on / off as necessary. Therefore, the power consumption is reduced by turning off the power supply of the device as much as possible during the suspend. On the contrary, at the time of resume, the power supplies of these turned off devices are turned on all at once, and the power supplies are required to have the ability to follow a sudden load change at this time. Therefore, conventionally, (1) the power supply capacity is provided with a margin. This method is to design a power supply that can supply the total peak current at the time of starting each device, and to make the power supply have a capacity larger than the maximum current during normal use.

【0003】(2)各デバイスの電源コントロールを別
系統で行い、電源オンのタイミングをソフトウエアまた
はハードウエアで制御する。この方法は各デバイスの電
源の投入タイミングを別々に制御できるために電源オン
のタイミングをずらすことにより電源の負担を軽くする
ことができる
(2) The power supply of each device is controlled by a separate system, and the power-on timing is controlled by software or hardware. In this method, the power-on timing of each device can be controlled separately, so the power-on timing can be reduced by shifting the power-on timing.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな携帯型情報処理装置の電源回路にあっては、上述の
(1)の方法は、最も安全にシステムの起動やリジュー
ム行うことが可能であるが、電源の容量が大きくなって
しまうことから、小型軽量化を要求されるパソコンにお
いては不利なものになる。また、電源のコストが高くな
ってしまい、低価格が図れない。
However, in the power supply circuit of such a portable information processing apparatus, the above method (1) can start and resume the system most safely. However, the capacity of the power supply becomes large, which is disadvantageous for a personal computer that is required to be small and lightweight. Moreover, the cost of the power source becomes high, and the price cannot be lowered.

【0005】(2)の方法では、電源の小型化は図れる
が、ソフトウエアによる制御ではソフトウエアの負担が
大きくなり、また、調整が必要な際にはソフトウエアの
変更が必要となりマスクされている場合等には、ROM
のマスク変更になりコストアップとなる。同様にハード
ウエアによる制御であっても、制御を行うLSIのマス
ク変更は必要となり、やはりコストアップとなる問題が
ある。
According to the method (2), the power source can be downsized, but the control by software imposes a heavy load on the software, and when adjustment is required, the software must be changed and masked. ROM etc.
The mask will be changed and the cost will increase. Similarly, even in the case of control by hardware, it is necessary to change the mask of the LSI that performs control, which also raises the problem of cost increase.

【0006】[0006]

【課題を解決するための手段】本発明はこれらの課題を
解決するためのものであり、起動時に大消費電力を必要
とするハードディスクまたはフロッピーディスク等のデ
バイスが内蔵され電池で駆動する携帯型情報処理装置の
電源回路において、各デバイスの電源シーケンスをコン
トロールする電源コントロールと、該電源コントロール
は抵抗およびコンデンサとから構成され、該抵抗および
コンデンサの定数値にもとずいて各デバイスへの電源投
入のタイモングを遅延させることを特徴とする携帯型情
報処理装置の電源回路を提供する。
The present invention is intended to solve these problems, and is a battery-powered portable information device having a built-in device such as a hard disk or a floppy disk which requires large power consumption at the time of startup. In a power supply circuit of a processing device, a power supply control for controlling a power supply sequence of each device, and the power supply control is composed of a resistor and a capacitor. The power supply to each device is turned on based on a constant value of the resistor and the capacitor. Provided is a power supply circuit for a portable information processing device, which is characterized by delaying timong.

【0007】[0007]

【作用】本発明は、電池駆動される携帯型情報処理装置
に起動時に大消費電力を必要とするハードディスクまた
はフロッピーディスク等が内蔵されているデバイスへの
電源シーケンスをコントロールする回路が抵抗およびコ
ンデンサとから構成され、これらの定数を変更すること
によって各デバイスへの電源投入のタイモングをずらす
ことができるために比較的小さな電源容量で設計でき
る。したがって、コスト的にもスペース的にも有利なシ
ステムを提供できる。
According to the present invention, a circuit for controlling a power supply sequence to a device in which a hard disk drive or a floppy disk, which requires a large amount of power consumption at the time of start-up in a battery-powered portable information processing device, has a resistor and a capacitor. It is possible to shift the timing of power-on to each device by changing these constants, so that it is possible to design with a relatively small power supply capacity. Therefore, a system that is advantageous in terms of cost and space can be provided.

【0008】[0008]

【実施例】以下、本発明の実施例について図面を用いて
説明する。図1は本発明の携帯型情報処理装置の電源回
路のブロック図であり、図2は本発明の携帯型情報処理
装置の電源回路に使用されているデバイスのピーク電流
を説明した図であり、図3は本発明の携帯型情報処理装
置の電源回路の動作を説明した図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a power supply circuit of a portable information processing device of the present invention, and FIG. 2 is a diagram illustrating a peak current of a device used in the power supply circuit of the portable information processing device of the present invention. FIG. 3 is a diagram for explaining the operation of the power supply circuit of the portable information processing device of the present invention.

【0009】図1の本発明の携帯型情報処理装置の電源
回路において、DEVICE1(デバイス1)はメイン
基板、DEVICE2(デバイス2)はハードディス
ク、DEVICE3(デバイス3)はフロッピーディス
クのように大容量の消費電力を使用するデバイスが接続
されている。これらの各デバイスの電源をコントロール
するための回路として、それぞれのデバイスに対して抵
抗(R)、コンデンサ(C)およびスイッチ(FET
SW)とが配設されている。デバイス1についてはR
1、C1、デバイス2については、R2、C2、デバイ
ス3についてはR3、C3の回路から構成されている。
図1乃至図3にもとずいて動作説明を行う。
In the power supply circuit of the portable information processing apparatus of the present invention shown in FIG. 1, DEVICE1 (device 1) has a large capacity such as a main substrate, DEVICE2 (device 2) has a hard disk, and DEVICE3 (device 3) has a large capacity like a floppy disk. A device that uses power is connected. As a circuit for controlling the power supply of each of these devices, a resistor (R), a capacitor (C) and a switch (FET) are provided for each device.
SW) is provided. R for device 1
1, C1 and R2 and C2 for the device 2, and R3 and C3 for the device 3.
The operation will be described based on FIGS. 1 to 3.

【0010】図2において、横軸に時間、縦軸に電流値
を示している。(a)はデバイス1の起動時にピーク電
流を示し、(b)はデバイス2の起動時にピーク電流を
示し、(c)はデバイス3の起動時にピーク電流を示し
ている。図2から分かるようにこれらのデバイスはほぼ
同じ時間にピーク電流を必要とするために大容量の電池
が必要とされる。そこで、本発明はこの問題を解消する
ために上述のR1、C1、R2、C2、R3、C3に定
数を設定することによって各デバイスへの電源供給の時
間を遅延させることにした。
In FIG. 2, the horizontal axis represents time and the vertical axis represents current value. (A) shows the peak current when the device 1 starts up, (b) shows the peak current when the device 2 starts up, and (c) shows the peak current when the device 3 starts up. As can be seen in FIG. 2, these devices require peak currents at approximately the same time, thus requiring large capacity batteries. Therefore, in order to solve this problem, the present invention delays the power supply time to each device by setting constants in R1, C1, R2, C2, R3 and C3.

【0011】例えば、 R1=1KΩ、C1=10μF R2=0Ω、C2=不使用 R3=560Ω、C3=10μF の時定数が設定されているときには、遅延時間はそれぞ
れ、t1=0.01秒、t2=0秒、t3=0.005
6秒となる。以上のことより、図3の(a)で示される
ようにそれぞれのピーク電流が上述のような遅延時間に
もとずいてピーク電流が発生する。これらのピーク電流
を合成したものが図3の(b)で示されている。この図
から分かるようにピーク電流が遅延するために一度に大
きな電流が発生しないために小型の電池を使用すること
ができる。
For example, when the time constants of R1 = 1KΩ, C1 = 10 μF R2 = 0Ω, C2 = not used R3 = 560Ω and C3 = 10 μF are set, the delay times are t1 = 0.01 seconds and t2, respectively. = 0 seconds, t3 = 0.005
It will be 6 seconds. From the above, as shown in FIG. 3A, each peak current is generated based on the delay time as described above. A combination of these peak currents is shown in FIG. As can be seen from this figure, since the peak current is delayed and a large current is not generated at one time, a small battery can be used.

【0012】[0012]

【発明の効果】以上説明したように本発明は、電池駆動
される携帯型情報処理装置に起動時に大消費電力を必要
とするハードディスクまたはフロッピーディスク等が内
蔵されているデバイスへの電源シーケンスをコントロー
ルする回路の抵抗およびコンデンサの定数を変更するこ
とによって各デバイスへの電源投入のタイモングを遅延
させることによって小さな電源容量で設計できるし、コ
スト的にもスペース的にも有利なシステムを提供でき
る。
As described above, the present invention controls the power supply sequence to a device in which a hard disk drive or a floppy disk, which requires a large power consumption at the time of startup, is incorporated in a battery-powered portable information processing apparatus. It is possible to design with a small power source capacity by delaying the power-on timing of each device by changing the constants of the circuit resistance and capacitor, and it is possible to provide a system that is advantageous in terms of cost and space.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の携帯型情報処理装置の電源回路のブ
ロック図である。
FIG. 1 is a block diagram of a power supply circuit of a portable information processing device according to the present invention.

【図2】 本発明の携帯型情報処理装置の電源回路で使
用されているデバイスのピーク電流を説明した図であ
る。
FIG. 2 is a diagram illustrating a peak current of a device used in a power supply circuit of a portable information processing device according to the present invention.

【図3】 本発明の携帯型情報処理装置の電源回路の動
作を説明した図である。
FIG. 3 is a diagram for explaining the operation of the power supply circuit of the portable information processing device according to the present invention.

【符号の説明】[Explanation of symbols]

R1、R2、R3 抵抗 C1、C2、C3 コンデンサ R1, R2, R3 resistors C1, C2, C3 capacitors

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】起動時に大消費電力を必要とするハードデ
ィスクまたはフロッピーディスク等のデバイスが内蔵さ
れ電池で駆動する携帯型情報処理装置の電源回路におい
て、各デバイスの電源シーケンスをコントロールする電
源コントロールと、該電源コントロールは抵抗およびコ
ンデンサとから構成され、該抵抗およびコンデンサの定
数値にもとずいて各デバイスへの電源投入のタイモング
を遅延させることを特徴とする携帯型情報処理装置の電
源回路。
1. A power supply control circuit for controlling the power supply sequence of each device in a power supply circuit of a portable information processing device which has a built-in device such as a hard disk or a floppy disk which requires a large amount of power consumption at startup and is driven by a battery, A power supply circuit for a portable information processing device, wherein the power supply control is composed of a resistor and a capacitor, and delays the power-on timing of each device based on the constant values of the resistor and the capacitor.
JP7126508A 1995-05-25 1995-05-25 Power circuit of portable information processor Pending JPH08320740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7126508A JPH08320740A (en) 1995-05-25 1995-05-25 Power circuit of portable information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7126508A JPH08320740A (en) 1995-05-25 1995-05-25 Power circuit of portable information processor

Publications (1)

Publication Number Publication Date
JPH08320740A true JPH08320740A (en) 1996-12-03

Family

ID=14936948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7126508A Pending JPH08320740A (en) 1995-05-25 1995-05-25 Power circuit of portable information processor

Country Status (1)

Country Link
JP (1) JPH08320740A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019986A (en) * 2004-06-30 2006-01-19 Toshiba Corp Telephone terminal of network telephone system and power feeding method used by the same telephone terminal
JP2009530997A (en) * 2006-03-21 2009-08-27 リーディス・テクノロジー・インコーポレーテッド Switching method of distributed class G type amplifier
CN106033660A (en) * 2015-03-25 2016-10-19 辛纳普蒂克斯日本合同会社 Semiconductor device and electronic apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006019986A (en) * 2004-06-30 2006-01-19 Toshiba Corp Telephone terminal of network telephone system and power feeding method used by the same telephone terminal
US7634079B2 (en) 2004-06-30 2009-12-15 Kabushiki Kaisha Toshiba Telephone terminal and method for supplying power to the same
JP2009530997A (en) * 2006-03-21 2009-08-27 リーディス・テクノロジー・インコーポレーテッド Switching method of distributed class G type amplifier
CN106033660A (en) * 2015-03-25 2016-10-19 辛纳普蒂克斯日本合同会社 Semiconductor device and electronic apparatus
US9892706B2 (en) 2015-03-25 2018-02-13 Synaptics Japan Gk Semiconductor device for mitigating through current and electronic apparatus thereof
US10504478B2 (en) 2015-03-25 2019-12-10 Synaptics Japan Gk Semiconductor device having shifted operation voltages in different modes and electronic apparatus thereof
CN106033660B (en) * 2015-03-25 2021-04-09 辛纳普蒂克斯日本合同会社 Semiconductor device and electronic device

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