JPH0831942A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enable a defective cell to be relieved even after packaging by impressing a prescribed voltage on an external terminal of a semiconductor memory package having a second cell array comprising a first cell array and a redundant cell and replacing the defective cell of the first cell array with the redundant cell of the second cell array. CONSTITUTION:A spare section cell 2 is controlled by a spare section cell array control circuit(SSACC) 4. Section cell array control circuits 3-1,...3-n and the SSACC 4, upon receiving a control signal RS from an RD (redundancy) pin 5, replaces a section cell array including a defective cell with a spare section cell array. A section selection signal SS is also inputted to the SSACC 4. Upon receiving the section selection signal SS from the SSACC 4, the section cell array control circuits 3-1,...3-n select one cell array from the spare section cell array and n-1 section cell arrays.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory used for a redundancy circuit for repairing a defective cell.

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory is tested before a chip is enclosed in a package. If the chip contains a defective cell and the semiconductor memory does not operate normally, the redundant cell is used to replace the defective cell with the redundant cell.

However, this test has only been performed on wafers. Therefore, if a defective cell occurs during the process of encapsulating the chip in the package, there is no means for relieving the semiconductor memory. Therefore, if defective cells occur during the process of encapsulating the chip in the package, the manufacturing cost of the semiconductor memory increases.

[0004]

As described above, since the conventional semiconductor memory test is conducted only on the wafer, the defective cell cannot be relieved after the chip is encapsulated in the package. Therefore, if defective cells are generated in the process of encapsulating the chip in the package, the manufacturing cost of the semiconductor memory increases.

The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to provide a redundant circuit capable of relieving a defective cell even after the chip is enclosed in a package. The purpose is to increase the repair rate of defective semiconductor memories and reduce the manufacturing cost.

[0006]

To achieve the above object, a semiconductor memory device of the present invention comprises a first cell array composed of memory cells and a second cell array composed of redundant cells.
There is provided means for replacing a defective cell in the first cell array with a redundant cell in the second cell array by applying a predetermined potential to an external terminal of a package of a semiconductor memory having a cell array.

The semiconductor memory has a first control circuit for selecting the first cell array and a second control circuit for selecting the second cell array, and the means is a first control circuit provided in the first control circuit. A fuse and a plurality of second fuses provided in the second control circuit are provided, and by applying a predetermined potential to the external terminal, the first fuse and the predetermined second fuse are provided. Then, the defective cells of the first cell array are replaced with the redundant cells of the second cell array.

The external terminal is provided only for applying a predetermined potential when replacing a defective cell in the first cell array with a redundant cell in the second cell array. A predetermined potential for replacing a defective cell of the first cell array with a redundant cell of the second cell array is applied to the external terminal during a test, and a signal or a potential for driving the semiconductor memory during a normal operation is applied. Is applied.

[0009]

According to the above structure, a predetermined potential (potential higher than the power supply potential) is applied to the external terminals of the package of the semiconductor memory, and the first and second fuses are respectively applied to the first and second cell arrays. Are set up.

That is, the first and second fuses are cut,
The defective cell of the first cell array can be replaced with the redundant cell of the second cell array. As a result, the semiconductor memory can be tested even after the semiconductor memory chip is sealed in the package, and the manufacturing cost of the semiconductor memory can be reduced as compared with the conventional method in which the test can be performed only on the wafer. Can be significantly reduced.

Further, if an external terminal is provided only for applying a predetermined potential during the test, the test can be easily performed. If the external terminals are used to apply a predetermined potential during testing and to apply signals or potentials for driving the semiconductor memory during normal operation, increase the number of external terminals in the package of the semiconductor memory. Nor.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a semiconductor memory according to an embodiment of the present invention. In this embodiment, a section cell array including defective cells is replaced with a spare section cell array including redundant cells.

In one chip, n section cell arrays 1-1, ... 1-n and, for example, one spare section cell array 2 are formed. Each section cell array 1-1, ... 1-n is controlled by a section cell array control circuit 3-1, ... 3-n. These section cell array control circuits 3-1, ... 3-n are
Upon receiving the section selection signal SS, one of the n section cell arrays 1-1, ... 1-n is selected.

Further, the spare section cell array 2 is
It is controlled by the spare section cell array control circuit 4. Section cell array control circuit 3-1, ... 3-
n and the spare section cell array control circuit 4 are RD
Upon receiving the control signal RS from the (redundancy) pin 5, the section cell array including the defective cell is replaced with the spare section cell array.

The section selection signal SS is also input to the spare section cell array control circuit 4. Therefore, the spare section cell array control circuit 4 and the section cell array control circuits 3-1, ..., 3-n receive the section selection signal SS and receive the spare section cell array and n−
One cell array is selected from one section cell array.

FIG. 2 shows the appearance of a chip having the semiconductor memory of FIG. 1 enclosed in a package. In this embodiment, RD for externally inputting a control signal RS for replacing a section cell array having defective cells with a spare section cell array having redundant cells.
Pin 5 is newly provided.

Further, 6-1, ... 6-6 are address pins, 7-1, ... 7-4 are control pins, 8-1 ,.
8-3 is an I / O pin, 9 is a power supply (VDD) pin, and 10 is a power supply (VSS) pin.

Whether or not the section cell array having defective cells is replaced with the spare section cell array having redundant cells is determined by, for example, the power supply potential VDD on the RD pin 5.
Is applied or not applied.

The RD pin 5 does not need to be newly provided, and the existing pin can be used as the RD pin only during the test. In this case, the RD pin (existing pin) is applied with a potential that is not used during normal operation (potential higher by 1 to 3 V than the power supply potential (high potential) VDD).

FIG. 3 specifically shows the configuration of the section cell array control circuit of FIG. The section selection signal SSi (i = 1 to n) is input to the gate of the P-channel type MOS transistor P1 and the gate of the N-channel type MOS transistor N1. The source of the MOS transistor P1 is connected to the power supply terminal 11 which supplies the power supply potential VDD, and the drain is connected to the inverter I1. The source of the MOS transistor N1 is
The drain is connected to one end of the current fuse 13 which is connected to the power supply terminal 12 which supplies the power supply potential VSS.
The other end of the current fuse 13 is connected to the inverter I1. Section cell array control signal SCi (i =
1, to n) are output from the inverter I1.

The RD pin 5 is connected to the source of the N-channel type MOS transistor N2. In the MOS transistor N2, a source and a gate are connected to each other, and a drain is connected to the other end of the current fuse 13.

The latch circuit LA includes a MOS transistor P
1 and the other end of the current fuse 13 and the inverter
It is connected to the terminal I1. The latch circuit LA is composed of, for example, two inverters I2 and I3.

FIG. 4 specifically shows the structure of the spare section cell array control circuit of FIG. The section selection signal SS1 is input to the gate of the P-channel MOS transistor TP1 and the gate of the N-channel MOS transistor TN1 via the inverter INV1. The source of the MOS transistor TP1 is connected to the power supply terminal 11 that supplies the power supply potential VDD, and the drain is connected to the NAND circuit 14. The source of the MOS transistor TN1 is connected to the power supply terminal 12 which supplies the power supply potential VSS, and the drain thereof is the current fuse 1
It is connected to one end of 3-1. Current fuse 13-1
The other end of is connected to the NAND circuit 14. NAN
The output terminal of the D circuit 14 is connected to the inverter I, and the section cell array control signal SC is output from the inverter I.

The RD pin 5 is connected to the source of the N-channel type MOS transistor MN1. In the MOS transistor MN1, the source and the gate are connected to each other,
The drain is connected to the other end of the current fuse 13-1.

The latch circuit LA1 includes a drain of the MOS transistor TP1 and the other end of the current fuse 13-1.
It is connected to the NAND circuit 14. The latch circuit LA1 is composed of, for example, two inverters.

Similarly, the section selection signal SSn is input to the gate of the P-channel type MOS transistor TPn and the gate of the N-channel type MOS transistor TNn via the inverter INVn. The source of the MOS transistor TPn is connected to the power supply terminal 11 that supplies the power supply potential VDD, and the drain is the NAND circuit 14
It is connected to the. The source of the MOS transistor TNn is connected to the power supply terminal 12 that supplies the power supply potential VSS, and the drain is connected to one end of the current fuse 13-n. The other end of the current fuse 13-n is connected to the NAND circuit 14. The output terminal of the NAND circuit 14 is connected to the inverter I, and the section cell array control signal SC is output from the inverter I.

The RD pin 5 is connected to the source of the N-channel type MOS transistor MNn. In the MOS transistor MNn, a source and a gate are connected to each other,
The drain is connected to the other end of the current fuse 13-n.

The latch circuit LAn has a drain of the MOS transistor TPn and the other end of the current fuse 13-n,
It is connected to the NAND circuit 14. The latch circuit LAn is composed of, for example, two inverters.

Next, the operation of the redundant circuit of the semiconductor memory of FIGS. 3 and 4 will be described. In the section cell array control circuit of FIG. 3, current fuses 13, 13-1,
Before disconnecting ~ 13-n, as shown in FIG. 5, the section cell array selection signal SSi (i = 1, ...
n) is the logic level of the section cell array control signal S
This is the same as the logic level of Ci (i = 1 to n).

In order to replace the section cell array having defective cells with the spare section cell array, the current fuse of the section cell array control circuit of FIG. 3 may be cut off.

A method of cutting the current fuse will be described. The selection signal SSi of the section cell array having the defective cell is set to "H" level, and the N-channel type MOS transistor N1 is turned on. Also, the control signal RS input from the outside through the RD pin 5 is set to the “H” level.

As a result, the N-channel MOS transistor N2 is turned on and a current flows through the current fuse 13, so that the current fuse 13 is cut off. When the current fuse 13 is cut off, the section cell array control signal SCi is always at "L" level regardless of the logic level of the section cell array selection signal SSi.

That is, as shown in FIG. 5, when the section cell array selection signal SSi is at "L" level, the P-channel MOS transistor P1 is turned on and the section cell array control signal SCi is at "L" level. . Further, even if the section cell array selection signal SSi goes to the “H” level, the latch circuit LAi holds the previous state (the section cell array selection signal SSi is at the “L” level), and therefore the section cell array control signal SCi Goes to "L" level.

As described above, the section cell array having defective cells can be replaced with the spare section cell array by setting the selection signal SSi of the section cell array having defective cells to the "H" level.

The spare section cell array control circuit of FIG. 4 operates as follows. Now, suppose that the first section cell array has a defective cell and the first section cell array is replaced with a spare section cell array. In this case, the section cell array selection signal SSi (i = 1) in FIG. 3 is at "H" level. Therefore, when the control signal RC input from the outside through the RD pin 5 becomes "H" level, the current fuse 13 of the first section cell array is cut off.

On the other hand, the section cell array selection signal SSi (i = 1) in FIG. 4 is also at "H" level. Therefore, the output of the inverter INV1 is at "L" level, and the N-channel MOS transistor TN1 is in the off state. Therefore, even if the control signal RC input from the outside through the RD pin 5 is set to "H" level, the current
13-1 does not flow current, so current fuse 13
-1 is not cut.

However, the other section cell array selection signals SSi (i = 2 to n) are at "L" level. Therefore, the outputs of the inverters INV2 to INVn are at "H" level, and the N-channel type MOS transistors TN2 and TNn are in the ON state. Therefore, when the control signal RC input from the outside through the RD pin 5 is set to the “H” level, the current fuses 13-2, 13
A current flows through -n, and the current fuses 13-2, 13-
n is cut off.

The section cell array control circuit whose current fuse has been cut off receives the section cell array selection signal SS.
i (i = 2, ... n) is at any logic level,
"H" level section cell array control signal SC2
', -SCn' are output.

Therefore, of the n input terminals of the NAND circuit 14, the section cell array selection signal SSi (i =
2, to n) are input to the n−1 input terminals at the logic level “H”.

That is, the section cell array selection signal SS
The logic level of 1 determines the logic level of the section cell array control signal SC. As described above, even after the chip is sealed in the package, the section cell array having defective cells can be replaced with the spare section cell array.

Although one spare section cell array is used in the above embodiment, it goes without saying that two or more spare section cell arrays may be used.
In this case, it is preferable to provide the same number of RD pins as the number of spare section cell arrays.

Although the section cell array having defective cells is replaced by the spare section cell array, defective cells may be replaced by spare word lines or spare bit line units.

[0043]

As described above, according to the semiconductor device of the present invention, the following effects can be obtained. An RD pin is provided in the package, a high voltage is applied to this RD pin, and a current fuse is provided in the section cell array control circuit. −
Can be cut.

As a result, the semiconductor memory can be tested even after the chip is sealed in the package, and the manufacturing cost of the semiconductor memory can be reduced as compared with the conventional method in which the test can be performed only on the wafer. Can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a semiconductor memory according to an embodiment of the present invention.

FIG. 2 is a view showing a package in which a chip having the semiconductor memory of FIG. 1 is enclosed.

FIG. 3 is a circuit diagram showing a section cell array control circuit of FIG.

FIG. 4 is a circuit diagram showing a spare section cell array control circuit of FIG.

FIG. 5: Control signals SSi and SC before and after disconnecting the current fuse
The figure which shows the logic level of i.

[Explanation of symbols]

1-1 to 1-n ... Section cell array, 2 ... Spare section cell array, 3-1 to 3-n ... Section cell array control circuit, 4 ... Spare section cell array control circuit, 5 ... RD (redundancy) pin, 6 -1, ~ 6-6 ... address pin, 7-1, ~ 7-4 ... control pin, 8-1, ~ 8-3 ... I / O pin, 9 ... power supply (VDD) pin, 10 ... power supply ( VSS) pin, 11 ... Power supply (VDD) terminal, 12 ... Power supply (VSS) terminal, 13, 13-1, to 13-n ... Current fuse, 14 ... NAND circuit, P1, TP1, to TPn ... P channel Type MOS transistors, N1, TN1, to TNn, MN1, to MNn ... N-channel type MOS transistors, I, I1 to I3, INV1, to INVn.
Ta.

Claims (4)

[Claims] 1. A defect of the first cell array is applied by applying a predetermined potential to an external terminal of a package of a semiconductor memory having a first cell array composed of memory cells and a second cell array composed of redundant cells. A semiconductor memory device comprising means for replacing a cell with a redundant cell of the second cell array. 2. The semiconductor memory has a first control circuit that selects the first cell array and a second control circuit that selects the second cell array, and the means is provided in the first control circuit. A first fuse and a plurality of second fuses provided in the second control circuit are provided, and the first fuse and the second fuse are predetermined by applying a predetermined potential to the external terminal. 2. The semiconductor memory device according to claim 1, wherein the defective cell of the first cell array is replaced with a redundant cell of the second cell array by cutting off the defective cell. 3. The external terminal is provided only for applying a predetermined potential when replacing a defective cell of the first cell array with a redundant cell of the second cell array. Semiconductor memory device. 4. A predetermined potential for replacing a defective cell of the first cell array with a redundant cell of the second cell array is applied to the external terminal during a test, and drives the semiconductor memory during a normal operation. 2. The semiconductor memory device according to claim 1, wherein the signal or the electric potential is applied.