JPH08313745A - Semiconductor optical integrated circuit and its production - Google Patents

Semiconductor optical integrated circuit and its production

Info

Publication number
JPH08313745A
JPH08313745A JP7122364A JP12236495A JPH08313745A JP H08313745 A JPH08313745 A JP H08313745A JP 7122364 A JP7122364 A JP 7122364A JP 12236495 A JP12236495 A JP 12236495A JP H08313745 A JPH08313745 A JP H08313745A
Authority
JP
Japan
Prior art keywords
semiconductor
receiving element
light receiving
layer
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7122364A
Other languages
Japanese (ja)
Inventor
Takaaki Hirata
隆昭 平田
Shinji Iio
晋司 飯尾
Masayuki Suehiro
雅幸 末広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP7122364A priority Critical patent/JPH08313745A/en
Publication of JPH08313745A publication Critical patent/JPH08313745A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible shut off the stray light to a photodetector by forming a groove deeper than a semiconductor light absorption layer around the photodetector and covering the flanks of this groove exclusive of the photodetecting part of the photodetector with opaque thin films. CONSTITUTION: The groove 51 which limits the current implantation region of a distribution feedback type semiconductor laser 2 part and the groove 52 which shuts off the stray light to the semiconductor photodetector 3 are formed by etching in a head for a one-chip interference measurement formed by integrating a distribution feedback type semiconductor laser 2, a semiconductor photodetector 3 and an optical waveguide 4 on a GaAs semiconductor substrate 1 by using an integration process applying the disordering of, for example, a quantum well structure. The groove 52 is formed deeper than an undoped GaAs quantum well layer (a light absorption layer to the semiconductor photodetector 3) and the flanks thereof exclusive of the photodetecting part of the photodetector 3 are coated with upper electrodes as opaque thin films. As a result, the semiconductor photodetector 3 is electrically insulated and the stray light from distribution feedback type semiconductor laser to the semiconductor photodetector is shut off.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体光集積回路に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optical integrated circuit.

【0002】[0002]

【従来の技術】従来より微弱な光を検出する光測定器で
は、受光素子に入射する信号光以外の光である迷光の除
去が重要な課題であり、光学的遮蔽板や光吸収体を用い
受光素子に入射する迷光を除いている。
2. Description of the Related Art Conventionally, in an optical measuring device for detecting weak light, it is an important issue to remove stray light which is light other than signal light incident on a light receiving element, and an optical shield plate or a light absorber is used. Stray light incident on the light receiving element is excluded.

【0003】[0003]

【発明が解決しようとする課題】この問題は種々の光学
素子を半導体基板上に集積化した半導体光集積回路にお
いても重要な課題であり、特に発光素子と受光素子を同
一基板上に形成した半導体光集積回路において大きな問
題となっている。
This problem is also an important issue in a semiconductor optical integrated circuit in which various optical elements are integrated on a semiconductor substrate, and particularly a semiconductor in which a light emitting element and a light receiving element are formed on the same substrate. This is a big problem in optical integrated circuits.

【0004】本発明の目的は、このような点に鑑み、受
光素子または発光素子の周囲に深いみぞを形成し、その
側面を不透明な薄膜でおおうことにより受光素子への迷
光を遮断することのできる半導体光集積回路を実現する
ことにある。本発明の他の目的は、受光素子または発光
素子の周囲に深いみぞを形成し、その側面を不透明な薄
膜でおおうことにより受光素子への迷光を遮断すること
のできる半導体光集積回路の製造方法を提供することに
ある。
In view of the above points, an object of the present invention is to block stray light to the light receiving element by forming a deep groove around the light receiving element or the light emitting element and covering the side surface with an opaque thin film. It is to realize a semiconductor optical integrated circuit that can be performed. Another object of the present invention is to provide a method for manufacturing a semiconductor optical integrated circuit capable of blocking stray light to the light receiving element by forming a deep groove around the light receiving element or the light emitting element and covering the side surface with an opaque thin film. To provide.

【0005】[0005]

【課題を解決するための手段】このような目的を達成す
るために本願の第1の発明では、発光素子と受光素子が
同一基板上に形成された半導体光集積回路において、前
記受光素子の周囲に半導体光吸収層より深いみぞが形成
され、そのみぞの側面が受光素子の受光部分を除き不透
明な薄膜でおおわれるように形成されたことを特徴とす
る。また本願の第2の発明では、発光素子と受光素子が
同一基板上に形成された半導体光集積回路において、前
記発光素子の周囲に半導体活性層より深いみぞが形成さ
れ、そのみぞの側面が光出力部分を除き不透明な薄膜で
おおわれるように形成されたことを特徴とする。
In order to achieve such an object, according to the first invention of the present application, in a semiconductor optical integrated circuit in which a light emitting element and a light receiving element are formed on the same substrate, the periphery of the light receiving element is provided. Is characterized in that a groove deeper than the semiconductor light absorption layer is formed, and the side surface of the groove is formed so as to be covered with an opaque thin film except the light receiving portion of the light receiving element. In a second invention of the present application, in a semiconductor optical integrated circuit in which a light emitting element and a light receiving element are formed on the same substrate, a groove deeper than a semiconductor active layer is formed around the light emitting element, and a side surface of the groove is an optical element. It is characterized in that it is formed so as to be covered with an opaque thin film except the output portion.

【0006】本願の方法の発明では、半導体結晶成長法
により、GaAs基板上に、少なくともクラッド層と、
GRIN層と、量子井戸層と、GRIN層と、ガイド層
を成長させる工程と、前記ガイド層に半導体レーザ用の
回折格子とリブ型光導波路を形成する工程と、前記半導
体レーザと半導体受光素子からなる部分をマスクし、そ
れ以外の部分には不純物をイオン注入する工程と、半導
体結晶成長法により、前記回折格子とリブ型光導波路を
形成したガイド層上に、クラッド層とキャップ層を成長
させる工程と、前記半導体受光素子の電極を電気的に絶
縁しかつ半導体受光素子への迷光を遮断するためのみぞ
構造をエッチングする工程と、その後前記みぞ構造の側
面をおおうように半導体レーザと半導体受光素子に上部
電極と下部電極を形成する工程を含むことを特徴とす
る。
In the method invention of the present application, at least a cladding layer and at least a cladding layer are formed on a GaAs substrate by a semiconductor crystal growth method.
A step of growing a GRIN layer, a quantum well layer, a GRIN layer, and a guide layer; a step of forming a diffraction grating for a semiconductor laser and a rib type optical waveguide in the guide layer; The mask layer is masked, and impurities are ion-implanted into the other portions, and a clad layer and a cap layer are grown on the guide layer on which the diffraction grating and the rib type optical waveguide are formed by a semiconductor crystal growth method. A step of etching the groove structure to electrically insulate the electrodes of the semiconductor light receiving element and to block stray light to the semiconductor light receiving element, and then to the semiconductor laser and the semiconductor light receiving so as to cover the side surface of the groove structure. The method is characterized by including a step of forming an upper electrode and a lower electrode in the device.

【0007】[0007]

【作用】受光素子または発光素子の周囲にみぞを形成
し、その側面を不透明な薄膜でおおう。これにより受光
素子への迷光を遮断する。
Function: A groove is formed around the light receiving element or the light emitting element, and the side surface thereof is covered with an opaque thin film. This blocks stray light to the light receiving element.

【0008】[0008]

【実施例】以下図面を用いて本発明を詳しく説明する。
ここでは、量子井戸構造の無秩序化を応用した集積化プ
ロセスを用いて、GaAs半導体基板上に分布帰還型半
導体レーザ(DFB−LD:Distributed Feedback - L
aser Diode)と、半導体受光素子と、光導波路を集積化
したワンチップ干渉計測用ヘッドを例にとって説明す
る。
The present invention will be described in detail below with reference to the drawings.
Here, a distributed feedback semiconductor laser (DFB-LD: Distributed Feedback-L) is formed on a GaAs semiconductor substrate by using an integration process which applies disordering of a quantum well structure.
aser diode), a semiconductor light receiving element, and a one-chip interferometric measuring head in which an optical waveguide is integrated.

【0009】図1は上記ワンチップ干渉計測用ヘッドの
一例を示す構成図である。図において、1はGaAs半
導体基板、2は分布帰還型半導体レーザ、3は半導体受
光素子、4は光導波路、5,6はレンズ、7はプリズム
である。
FIG. 1 is a block diagram showing an example of the one-chip interference measuring head. In the figure, 1 is a GaAs semiconductor substrate, 2 is a distributed feedback semiconductor laser, 3 is a semiconductor light receiving element, 4 is an optical waveguide, 5 and 6 are lenses, and 7 is a prism.

【0010】分布帰還型半導体レーザ2の出力光は光導
波路4で二分され、一方は曲がり導波路により直接半導
体受光素子3に向かい、他方は半導体基板1から出射し
て出力レンズ5でコリメートされプリズム7に向かう。
プリズム7で反射された出力光は入力レンズ6で集光さ
れ、半導体基板1上の光導波路4に再度入射し半導体受
光素子3に向かう。分布帰還型半導体レーザ2の曲がり
導波路を導波した出力光とプリズム7で反射して戻って
来た出力光の2つの光は半導体受光素子3の手前で結合
し、半導体受光素子3には両出力光の干渉信号が得られ
る。
The output light of the distributed feedback semiconductor laser 2 is divided into two by the optical waveguide 4, one of which directly goes to the semiconductor light receiving element 3 by the curved waveguide and the other of which is emitted from the semiconductor substrate 1 and collimated by the output lens 5 to be a prism. Head to 7.
The output light reflected by the prism 7 is condensed by the input lens 6, again enters the optical waveguide 4 on the semiconductor substrate 1, and goes to the semiconductor light receiving element 3. Two lights, that is, the output light guided through the curved waveguide of the distributed feedback semiconductor laser 2 and the output light reflected and returned by the prism 7 are combined before the semiconductor light receiving element 3, and the semiconductor light receiving element 3 receives the light. An interference signal of both output lights is obtained.

【0011】次に作製プロセスについて説明する。 (1) 半導体結晶成長法、例えば有機金属気相成長法によ
り、図2の断面図に示すように、n型GaAs基板11
上に、n型GaAsバッファー層12(厚さ0.5μ
m)と、n型Al0.6Ga0.4Asクラッド層13(厚さ
1.5μm)と、アンドープAlxGa1-xAs(x=
0.6〜0.3)のGRIN層14(厚さ150nm)
と、アンドープGaAs量子井戸層15(厚さ10n
m)と、アンドープAlxGa1-xAs(x=0.3〜
0.6)のGRIN層16(厚さ150nm)と、アン
ドープAl0.6Ga0.4Asのキャリアブロック層17
(厚さ30nm)と、Al0.15Ga0.85Asのガイド層
18(厚さ20nm)を温度780゜Cで成長させる。
この場合、バッファー層12、キャリアブロック層17
は必ずしも必要とはしない。なお、アンドープGaAs
量子井戸層15は、分布帰還型半導体レーザ2では活性
層として動作し、半導体受光素子3では光吸収層として
動作する。
Next, the manufacturing process will be described. (1) As shown in the sectional view of FIG. 2, an n-type GaAs substrate 11 is formed by a semiconductor crystal growth method, for example, a metal organic chemical vapor deposition method.
N-type GaAs buffer layer 12 (thickness 0.5 μ
m), the n-type Al 0.6 Ga 0.4 As cladding layer 13 (thickness 1.5 μm), and the undoped Al x Ga 1-x As (x =
0.6-0.3) GRIN layer 14 (thickness 150 nm)
And the undoped GaAs quantum well layer 15 (thickness 10 n
m) and undoped Al x Ga 1-x As (x = 0.3 to
0.6) GRIN layer 16 (thickness 150 nm) and carrier block layer 17 of undoped Al 0.6 Ga 0.4 As
A guide layer 18 (thickness 30 nm) and Al 0.15 Ga 0.85 As (thickness 20 nm) are grown at a temperature of 780 ° C.
In this case, the buffer layer 12 and the carrier block layer 17
Is not always necessary. Undoped GaAs
The quantum well layer 15 operates as an active layer in the distributed feedback semiconductor laser 2 and operates as a light absorption layer in the semiconductor light receiving element 3.

【0012】(2) 電子ビーム露光と硫酸過水によるエッ
チングによって、ガイド層18に分布帰還型半導体レー
ザ用の回折格子21と、リブ型光導波路22を形成す
る。エッチング後の上面図を図3に示し、図3のa−b
とc−dの断面をそれぞれ図4と図5に示す。このとき
のエッチングは、ガイド層18を完全にエッチングしキ
ャリアブロック層17中で止まるように制御する。これ
によりエッチングされた部分とされていない部分の違い
がガイド層の有無となり、エッチングによる屈折率差が
ガイド層の厚さにより決まることになる。
(2) A diffraction grating 21 for a distributed feedback type semiconductor laser and a rib type optical waveguide 22 are formed in the guide layer 18 by electron beam exposure and etching with sulfuric acid / hydrogen peroxide mixture. A top view after etching is shown in FIG.
And cd cross sections are shown in FIGS. 4 and 5, respectively. The etching at this time is controlled so that the guide layer 18 is completely etched and stopped in the carrier block layer 17. As a result, the difference between the etched portion and the non-etched portion is the presence or absence of the guide layer, and the difference in the refractive index due to etching is determined by the thickness of the guide layer.

【0013】(3) 分布帰還型半導体レーザ2と半導体受
光素子3からなる部分を図6に示すようにマスク(斜線
部分)31a,31bを施し、これ以外の部分にはエネ
ルギー100keV、ドーズ量1×1013cm-2で不純
物例えばSiをイオン注入する。
(3) As shown in FIG. 6, masks (hatched portions) 31a and 31b are applied to the portion composed of the distributed feedback semiconductor laser 2 and the semiconductor light receiving element 3, and the other portions have energy of 100 keV and a dose of 1 An impurity such as Si is ion-implanted at × 10 13 cm -2 .

【0014】(4) 有機金属気相成長法により、回折格子
21とリブ型光導波路22を形成したガイド層18上
に、p型Al0.6Ga0.4Asクラッド層41(厚さ1.
5μm)と、p型GaAsキャップ層42(厚さ0.3
μm)を温度750゜Cで成長させる。Si不純物によ
りAlとGaの相互拡散が助長されるため、このときの
昇温によりSiをイオン注入した部分の量子井戸が無秩
序化する。この無秩序化により量子井戸の吸収端が短波
長側にシフトし、Siをイオン注入した部分が低損失の
導波路となる。図3中のc−d断面を図7に示す。図中
点線部のGaAs量子井戸層151が無秩序化されてい
る。
(4) A p-type Al 0.6 Ga 0.4 As clad layer 41 (thickness: 1. is formed on the guide layer 18 on which the diffraction grating 21 and the rib type optical waveguide 22 are formed by the metal organic chemical vapor deposition method).
5 μm) and the p-type GaAs cap layer 42 (thickness 0.3
μm) at a temperature of 750 ° C. Since the Si impurity promotes the interdiffusion of Al and Ga, the temperature rise at this time makes the quantum well in the portion where Si ions are implanted disorder. Due to this disordering, the absorption edge of the quantum well shifts to the shorter wavelength side, and the Si ion-implanted portion becomes a low-loss waveguide. The cd cross section in FIG. 3 is shown in FIG. The GaAs quantum well layer 151 indicated by the dotted line in the figure is disordered.

【0015】(5) 分布帰還型半導体レーザ2部分の電流
注入領域を制限するための深さ1.6μmのみぞ構造5
1と、半導体受光素子3の電極を電気的に絶縁し、かつ
半導体受光素子3への迷光を遮断するための深さ3μm
のみぞ構造52をエッチングする。みぞ構造51,52
の上面図を図8に示す。
(5) Groove structure 5 having a depth of 1.6 μm for limiting the current injection region of the distributed feedback semiconductor laser 2 portion 5
1 and the electrode of the semiconductor light receiving element 3 are electrically insulated, and a depth of 3 μm for blocking stray light to the semiconductor light receiving element 3
Etch the trench structure 52. Groove structure 51, 52
A top view of the above is shown in FIG.

【0016】(6) SiO2 膜61の成膜と、分布帰還型
半導体レーザ2と半導体受光素子3部分のSiO2 膜6
1のエッチングを行い、その後分布帰還型半導体レーザ
2と半導体受光素子3に上部電極62(分布帰還型半導
体レーザ2の上部電極を62a、半導体受光素子3の上
部電極を62bとする)と下部電極63を形成する。図
9に上部電極62a,62bの上面図を、また図10お
よび図11に図9におけるe−fおよびg−hでの断面
図をそれぞれ示す。図9と図11に示されるように、深
さ3μmのみぞ構造52の側面が半導体受光素子3の受
光部分を除いてすべて上部電極62でおおわれる構造と
なっており、これにより、強力な発光源である分布帰還
型半導体レーザ2から側面方向へ放射され受光部分に入
る迷光を遮断することができる。
[0016] (6) and the deposition of the SiO 2 film 61, a distributed feedback semiconductor laser 2 and the semiconductor light-receiving element 3 portion of the SiO 2 film 6
1 is etched, and then the distributed feedback semiconductor laser 2 and the semiconductor light receiving element 3 have an upper electrode 62 (the upper electrode of the distributed feedback semiconductor laser 2 is 62a and the upper electrode of the semiconductor light receiving element 3 is 62b) and the lower electrode. 63 is formed. 9 is a top view of the upper electrodes 62a and 62b, and FIGS. 10 and 11 are sectional views taken along line ef and line gh in FIG. As shown in FIGS. 9 and 11, the side surface of the groove structure 52 having a depth of 3 μm is entirely covered with the upper electrode 62 except for the light receiving portion of the semiconductor light receiving element 3, whereby strong light emission is achieved. It is possible to block stray light emitted from the distributed feedback semiconductor laser 2 as a source in the lateral direction and entering the light receiving portion.

【0017】以上のように側面を上部電極62でおおっ
た深さ3μmのみぞ構造52は、半導体受光素子3を電
気的に絶縁し、かつ半導体受光素子3への迷光を遮断す
る効果を持ち、これにより微弱な干渉信号を測定するこ
とが可能となる。また不透明な薄膜として上部電極を用
いることにより、上部電極の形成と同じプロセスで迷光
遮断用の不透明薄膜を形成でき、作製プロセスが簡略化
できる。
As described above, the groove structure 52 having a depth of 3 μm whose side surface is covered with the upper electrode 62 has an effect of electrically insulating the semiconductor light receiving element 3 and blocking stray light to the semiconductor light receiving element 3. This makes it possible to measure a weak interference signal. Further, by using the upper electrode as the opaque thin film, the opaque thin film for blocking stray light can be formed by the same process as the formation of the upper electrode, and the manufacturing process can be simplified.

【0018】なお、本発明は上記実施例に限定されな
い。例えば、上記実施例においては側面を不透明な薄膜
でおおったみぞ構造を受光素子の周囲に形成し、迷光を
遮断する構造としたが、逆に上記みぞ構造を半導体発光
素子3の周囲に形成し迷光を遮断する構造としてもよ
い。また両方を併用する構造としてもよい。
The present invention is not limited to the above embodiment. For example, in the above embodiment, a groove structure whose side surface is covered with an opaque thin film is formed around the light receiving element to block stray light. On the contrary, the groove structure is formed around the semiconductor light emitting element 3. A structure for blocking stray light may be used. Also, both may be used in combination.

【0019】[0019]

【発明の効果】以上説明したように本発明によれば、半
導体光集積回路において受光素子または発光素子の周囲
に深いみぞを形成し、その側面を不透明な薄膜でおおう
ことにより、受光素子を電気的に絶縁し、かつ受光素子
への迷光を遮断することができ、これにより微弱な干渉
信号を測定することが可能になるという効果がある。ま
た、不透明な薄膜として上部電極を用いることにより、
上部電極の形成と同じプロセスで迷光遮断用の不透明薄
膜を形成でき、作製プロセスが簡略化できるという効果
がある。
As described above, according to the present invention, in a semiconductor optical integrated circuit, a deep groove is formed around a light receiving element or a light emitting element, and the side surface thereof is covered with an opaque thin film so that the light receiving element is electrically connected. It is possible to electrically insulate and to block stray light to the light receiving element, which makes it possible to measure a weak interference signal. Also, by using the upper electrode as an opaque thin film,
An opaque thin film for blocking stray light can be formed by the same process as the formation of the upper electrode, and the manufacturing process can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体光集積回路の一実施例を示
す構成図
FIG. 1 is a configuration diagram showing an embodiment of a semiconductor optical integrated circuit according to the present invention.

【図2】図1に示す半導体光集積回路の断面図FIG. 2 is a sectional view of the semiconductor optical integrated circuit shown in FIG.

【図3】半導体光集積回路の作製プロセスにおけるエッ
チング処理後の上面図
FIG. 3 is a top view after etching treatment in a manufacturing process of a semiconductor optical integrated circuit.

【図4】図3におけるa−bでの断面図FIG. 4 is a sectional view taken along line ab in FIG.

【図5】図3におけるc−dでの断面図5 is a sectional view taken along line cd in FIG.

【図6】イオン注入用マスクの形状を示す図FIG. 6 is a view showing the shape of an ion implantation mask.

【図7】量子井戸層の無秩序化を示す図FIG. 7 is a diagram showing disordering of a quantum well layer.

【図8】みぞ構造の上面図FIG. 8 is a top view of the groove structure.

【図9】上部電極を示す図FIG. 9 is a diagram showing an upper electrode.

【図10】図9におけるe−fでの断面図10 is a sectional view taken along line ef in FIG.

【図11】図9におけるg−hでの断面図11 is a sectional view taken along line gh in FIG.

【符号の説明】[Explanation of symbols]

1 GaAs半導体基板 2 分布帰還型半導体レーザ 3 半導体受光素子 4 光導波路 5,6 レンズ 7 プリズム 11 GaAs基板 12 バッファー層 13 クラッド層 14 GRIN層 15 量子井戸層 16 GRIN層 17 ブロック層 18 ガイド層 21 回折格子 22 リブ型光導波路 31a,31b マスク 41 クラッド層 42 キャップ層 51,52 みぞ 62,62a,62b 上部電極 63 下部電極 151 無秩序化量子井戸層 1 GaAs semiconductor substrate 2 distributed feedback semiconductor laser 3 semiconductor light receiving element 4 optical waveguide 5, 6 lens 7 prism 11 GaAs substrate 12 buffer layer 13 clad layer 14 GRIN layer 15 quantum well layer 16 GRIN layer 17 block layer 18 guide layer 21 diffraction Lattice 22 Rib type optical waveguide 31a, 31b Mask 41 Cladding layer 42 Cap layer 51, 52 Groove 62, 62a, 62b Upper electrode 63 Lower electrode 151 Disordered quantum well layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 // H01L 31/10 H01L 31/10 A ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location // H01L 31/10 H01L 31/10 A

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】発光素子と受光素子が同一基板上に形成さ
れた半導体光集積回路において、 前記受光素子の周囲に半導体光吸収層より深いみぞが形
成され、そのみぞの側面が受光素子の受光部分を除き不
透明な薄膜でおおわれるように形成されたことを特徴と
する半導体光集積回路。
1. In a semiconductor optical integrated circuit in which a light emitting element and a light receiving element are formed on the same substrate, a groove deeper than a semiconductor light absorbing layer is formed around the light receiving element, and a side surface of the groove is a light receiving element of the light receiving element. A semiconductor optical integrated circuit characterized by being formed so as to be covered with an opaque thin film except for a part.
【請求項2】発光素子と受光素子が同一基板上に形成さ
れた半導体光集積回路において、 前記発光素子の周囲に半導体活性層より深いみぞが形成
され、そのみぞの側面が光出力部分を除き不透明な薄膜
でおおわれるように形成されたことを特徴とする半導体
光集積回路。
2. In a semiconductor optical integrated circuit in which a light emitting element and a light receiving element are formed on the same substrate, a groove deeper than a semiconductor active layer is formed around the light emitting element, and a side surface of the groove except a light output portion. A semiconductor optical integrated circuit characterized by being formed so as to be covered with an opaque thin film.
【請求項3】前記不透明な薄膜が、前記半導体光集積回
路において用いられる電極と同じ材料であることを特徴
とする請求項1または請求項2記載の半導体光集積回
路。
3. The semiconductor optical integrated circuit according to claim 1 or 2, wherein the opaque thin film is made of the same material as an electrode used in the semiconductor optical integrated circuit.
【請求項4】発光素子と受光素子が同一基板上に形成さ
れる半導体光集積回路の製造方法であって、 半導体結晶成長法により、GaAs基板上に、少なくと
もクラッド層と、GRIN層と、量子井戸層と、GRI
N層と、ガイド層を成長させる工程と、 前記ガイド層に半導体レーザ用の回折格子とリブ型光導
波路を形成する工程と、 前記半導体レーザと半導体受光素子からなる部分をマス
クし、それ以外の部分には不純物をイオン注入する工程
と、 半導体結晶成長法により、前記回折格子とリブ型光導波
路を形成したガイド層上に、クラッド層とキャップ層を
成長させる工程と、 前記半導体受光素子の電極を電気的に絶縁しかつ半導体
受光素子への迷光を遮断するためのみぞ構造をエッチン
グする工程と、 その後前記みぞ構造の側面をおおうように半導体レーザ
と半導体受光素子に上部電極と下部電極を形成する工程
を含むことを特徴とする半導体光集積回路の製造方法。
4. A method for manufacturing a semiconductor optical integrated circuit in which a light emitting element and a light receiving element are formed on the same substrate, wherein at least a cladding layer, a GRIN layer, and a quantum layer are formed on a GaAs substrate by a semiconductor crystal growth method. Well layer and GRI
Growing an N layer and a guide layer; forming a diffraction grating for a semiconductor laser and a rib type optical waveguide in the guide layer; masking a portion including the semiconductor laser and the semiconductor light receiving element; A step of ion-implanting impurities into the portion; a step of growing a clad layer and a cap layer on the guide layer on which the diffraction grating and the rib type optical waveguide are formed by a semiconductor crystal growth method; and an electrode of the semiconductor light receiving element. Etching the groove structure to electrically insulate the semiconductor and block stray light to the semiconductor light receiving element, and then form the upper electrode and the lower electrode on the semiconductor laser and the semiconductor light receiving element so as to cover the side surface of the groove structure. A method of manufacturing a semiconductor optical integrated circuit, comprising:
JP7122364A 1995-05-22 1995-05-22 Semiconductor optical integrated circuit and its production Pending JPH08313745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7122364A JPH08313745A (en) 1995-05-22 1995-05-22 Semiconductor optical integrated circuit and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7122364A JPH08313745A (en) 1995-05-22 1995-05-22 Semiconductor optical integrated circuit and its production

Publications (1)

Publication Number Publication Date
JPH08313745A true JPH08313745A (en) 1996-11-29

Family

ID=14834059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7122364A Pending JPH08313745A (en) 1995-05-22 1995-05-22 Semiconductor optical integrated circuit and its production

Country Status (1)

Country Link
JP (1) JPH08313745A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004023010A (en) * 2002-06-20 2004-01-22 Yokogawa Electric Corp Semiconductor laser and its manufacturing method
JP2004214059A (en) * 2003-01-06 2004-07-29 Smk Corp Operation panel input device
JP2009047726A (en) * 2007-08-13 2009-03-05 Fujitsu Ltd Optical modulator and optical transmitter
JP2018026478A (en) * 2016-08-10 2018-02-15 富士ゼロックス株式会社 Light-emitting element, light-emitting element array, and optical transmission device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004023010A (en) * 2002-06-20 2004-01-22 Yokogawa Electric Corp Semiconductor laser and its manufacturing method
JP2004214059A (en) * 2003-01-06 2004-07-29 Smk Corp Operation panel input device
JP2009047726A (en) * 2007-08-13 2009-03-05 Fujitsu Ltd Optical modulator and optical transmitter
JP2018026478A (en) * 2016-08-10 2018-02-15 富士ゼロックス株式会社 Light-emitting element, light-emitting element array, and optical transmission device

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