JPH0831200A - Detection for deffective memory transistor and its detecting device - Google Patents

Abstract

PURPOSE:To detect a low Vth memory cell in an erasing state by selecting all rows by voltage of a non-selection row or lower voltage than Vth of a memory FET in which electrons are already discharged from IG at the time of a test, and reading out by adding higher voltage than that at the time of read-out to a selected column. CONSTITUTION:When a bit line BL1 is selected by a signal CS in an erasing state in which all memory cells are normal, a potential of FG comes to a potential based on capacity coupling of the FG and a drain, this potential is far lower than a potential by which Q is turned on, a drain current IM is a sense current or less, and a sense amplifier is judged as 0V, that is, normal. When only Q11 is defective, a potential of the FG is indicated as BL1 is 0V, for example, 0.5V. When 2V is applied to a drain through the BL1, a potential of the FG is raised and the Q11 is turned on, IM exceeds a sense current, the sense amplifier 30 is judged as abnormal. The higher BL voltage at the time of test read-out is raised, the more detecting sensitivity are increased. Concerning a soft line, since a word line WL at the time of a test is non- selection and is finished to detect by one time read-out, considering its influence is not required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defective memory transistor detecting method and detecting device, and more particularly, to a plurality of variable transistors for injecting electrons into a floating gate (floating gate) and emitting electrons by electrical or ultraviolet irradiation. A defective memory transistor in a semiconductor memory device in which the gates of threshold type nonvolatile semiconductor memory transistors (hereinafter simply referred to as “memory transistors”) are connected in the row direction and the drains thereof are connected in the column direction are arranged in a matrix. The present invention relates to a detection method and a detection device thereof.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram for explaining a conventional method and apparatus for detecting a defective memory transistor disclosed in Japanese Patent Laid-Open No. 62-114200, in which Q11 to Qnm are FAMOS. Type memory transistors (memory cells), 1 to m are column select gates to which column select (column selection) signals CS1 to CSm are applied, and BL1 to BLm, drains of the memory cells Q11 to Qnm are commonly connected in the column direction. Bit line, WL1
˜WLn is a word line in which the gates of the memory cells Q11 to Qnm are commonly connected in the row direction, and 20 is a sense amplifier connected to the drain of each memory cell via the column select gates 1 to m. Also, WS1, WS2-WS
n is a word line selection signal for selecting the word lines WL1 and WL2 to WLn.

Next, the operation will be described. In the EPROM configured as described above, in order to read the written information, a word line having a memory cell at a specified address is selected and set to a normal power supply voltage (5V), and all the other word lines are read. Is not selected and the normal ground potential (0 V) is set. Further, only the bit line having the designated memory cell is selected by the column select signal and connected to the sense amplifier 20.

FIG. 6 shows the characteristics of the drain voltage and the gate voltage or word line voltage of the memory cell. In the figure, the threshold value of the memory cell in the erased state "1" is about 1.
The characteristic of A is shown at around 5V, and the characteristic of B is shown at the threshold value of the memory cell in the written state "0" of about 6-10V. Further, the sense current Isense is a level for determining whether the drain current of the memory cells Q11 to Qnm detected by the sense amplifier 20 is information "1" or "0". When a word line voltage (usually 5V) is applied to the gates of the memory cells Q11 to Qnm, the memory cell in the erased state having the characteristic A in FIG. FIG. 6 is determined.
Since the drain current IM does not flow through the memory cell in the written state having the B characteristic of No. 3, it is determined as "0".

A more detailed operation will be described with reference to FIG. When the memory cell Q11 is addressed, the word line signal WS1 is selected, the other word line signals WS2 to WSn are deselected, the column select signal CS1 is selected, and the other column select signals CS2 to CSm are deselected. By selection, the bit line BL1 is selected and connected to the sense amplifier 20.

Here, considering the case where the memory cell Q11 is in the erased state "1", the memory cell Q11 is A in FIG.
Since the gate voltage becomes 5 V and the drain current IM exceeds the sense current Isense, the sense amplifier 20 determines "1". At this time,
Other memory cells Q21 to Q on the same bit line BL1
The n1 does not affect the reading of the memory cell Q11 because the gate voltage is 0 V and the drain current IM does not flow whether the erased state is "1" or the written state is "0".

Considering when the memory cell Q11 is in the write state "0", the drain current IM does not flow because the memory cell Q11 has the characteristic of B shown in FIG. 6 and the gate voltage is 5V. That is, since the drain current IM is smaller than the sense current Isense, the sense amplifier 20
Is determined to be "0". At this time, since the drain current IM does not flow to the other memory cells on the same bit line as in the above description, the memory cell Q1
It does not affect the reading of 1.

However, in reality, the memory cell Q11
.About.Qnm varies, and especially the threshold voltage in the erased state is about 1.5 V in a normal value, but there is a threshold voltage higher or lower by 1 to 2 V. A memory cell with a high threshold voltage is in the same state as a shallowly written state, and almost no drain current IM flows even if it is selected, so it can be rejected as an erase failure, but the threshold voltage is abnormal on the same bit line. When there is a low memory cell, the drain current IM exceeding the sense current Isense of the memory cell having an abnormally low threshold value even if the memory cell has a high threshold value.
, It is difficult to reject it.

Next, the operation of reading the memory cell Q11 will be described. It is assumed that the memory cell Q11 is normal and is in the erased state "1", and the memory cell Q21 is abnormal and has a threshold voltage of about -1.5V. The other memory cells Q31 to Qn1 on the same bit line are normal memories and are set to the erased state "1" or the written state "0".

A normal memory cell Q11 has the same structure as that shown in FIG.
Since it is selected, the gate voltage is 5V because it is selected.
Is applied, the drain current IM exceeds the sense current Isense, and the sense amplifier 20 determines "1".
At this time, assuming that the memory cell Q21 has the characteristic C shown in FIG. 7, the gate voltage is 0V for the non-selected word line voltage.
However, a drain current exceeding the sense current Isense flows through the memory cell Q21. This drain current is added to the drain current IM for reading the memory cell Q11, but this does not affect reading the memory cell Q11 as "1". Because the sense amplifier 20 has the sense current Ise.
This is because if the flow is nse or more, it is determined as "1". Similarly, the sense current Isense is applied to the memory cells Q31 to Qn1.
Even if the above drain current IM flows, it has no effect.

On the contrary, the memory cell Q11 is in the normal state and the write state is "0", and the threshold value of the memory cell Q21 is about -1.
If it is 5V, the memory cell Q11 has the characteristic of B shown in FIG. 7, and even if 5V is applied to the gate voltage because it is selected, the drain current IM does not flow.
However, similar to the above description, the memory cell Q21 has the characteristic of C, and the drain current IM flows beyond the sense current Isense even if the gate voltage is 0V. Then, the sense amplifier 20 catches the drain current of the memory cell Q21 as the drain current of the memory cell Q11, and the sense amplifier 20 judges "1", and the correct reading cannot be performed.

However, since it is possible to write even with such a depletion type memory cell,
In the state where the memory cell Q21 is written, its threshold voltage is 6 V or more, and it does not affect other memory cells on the same bit line, and the memory cell Q21 is not affected.
21 can also be read correctly. Even if the memory cell Q21 is in the erased state, there is no particular problem in reading the memory cell Q21 itself. This is because the drain current of the memory cell Q21 flows more than that of the memory cell in the normally erased state.

[0013] Now, in order to reject an abnormal memory cell of this type by a test, the conventional procedure is as follows.
First, all the memory cells Q11 to Qnm are set in an erased state, only one of the memory cells on each bit line BL1 to BLm is written, and the memory cell of each written bit line is read to write the written memory. Memory cells other than cells can be checked. Next, except for the memory cells written after erasing, one of the memory cells on each bit line is written, and the written memory cells are read to check the memory cells that have been written and erased first. I do. In this way all memory cells can be checked.

[0014]

Since the conventional method and apparatus for detecting a defective memory transistor are configured as described above, it is possible to test once by repeating writing and erasing twice. Considering the writing and erasing times, there are problems such as lack of mass productivity.

The present invention has been made in order to solve the above problems, and a defective memory which can be easily tested in a short time in an erased state without repeating writing and erasing in this type of defective memory cell. An object is to obtain a transistor detection method and a detection device thereof.

[0016]

According to another aspect of the present invention, there is provided a method of detecting a defective memory transistor, wherein a memory transistor designated by an address signal is selected by a row decoder and a column decoder in a normal read mode. Information is read through a sense amplifier, and in a test operation, a voltage equal to or higher than the voltage of the non-selected row in the normal read mode, or higher than that and a normal threshold value of the memory transistor that has emitted electrons from the floating gate. All the rows are selected with a voltage lower than the voltage, and a voltage higher than that in the normal read mode is applied to the selected column to read.

According to another aspect of the present invention, there is provided a defective memory transistor detection device, which includes a switching circuit for outputting a test enable signal for switching between a sense operation in a normal read mode and a sense operation in a test read, and the test. When the enable signal indicates the test read time, a sense amplifier for applying a higher voltage to the column than in the normal read mode is provided.

[0018]

According to the method of detecting a defective memory transistor of the present invention, in the test operation, the voltage is equal to or higher than the voltage of the non-selected row in the normal read mode, and electrons are emitted from the floating gate. Since all the rows are selected with a voltage lower than the normal threshold voltage of the memory transistor and a voltage higher than that in the normal read mode is applied to the selected column, the erased memory transistor connected to the selected column is selected. Has an abnormally low threshold value, a larger amount of current flows than in the read operation in which the normal voltage is applied to the selected column, and the detection accuracy of the defective memory transistor by the sense amplifier can be improved. Also, in normal operation, it is possible to select rows,
Since the normal voltage is applied to the selected column, the read operation by the sense amplifier becomes possible.

According to another aspect of the present invention, there is provided a defective memory transistor detecting device, wherein a switching circuit for outputting a test enable signal for switching between a sense operation in a normal read mode and a sense operation in a test read, and the test enable. When the signal indicates the test read time, a sense amplifier for applying a higher voltage to the column than in the normal read mode is provided, so that the normal read mode (normal read operation) and the test read (test read operation) are switched. For example, the test enable signal may be set to "1" or "0", and the normal read operation and the test read operation can be easily switched.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing an embodiment of the present invention,
First, a defective memory cell (defective memory transistor) will be described. A defective memory cell, that is, a memory cell having a lower threshold voltage (negative threshold value) or a negative threshold value than a memory cell normally erased by ultraviolet rays or the like has a floating gate potential higher than a normal range for some reason. Control gate potential is 0V
A memory transistor in which a channel is formed between a source and a drain to be in a conductive state even at a (ground) potential.

FIG. 2 is a schematic sectional view showing a memory cell. In the figure, 101 is a control gate connected to a word line, and 102 is a channel and control gate 1.
01 is a floating gate electrically floating, 103 is a drain connected to the bit line, and 104 is an electrically grounded source, which are formed on the substrate 105. The channel is formed between the drain 103 and the source 104. Here, the threshold value is a voltage of the control gate 101 which makes the memory cell conductive when 0 V is applied to the source 104 and the substrate 105 and 1 V is applied to the drain 103.

In FIG. 2, if the threshold of the memory cell (threshold seen from the control gate as described above) is 1 V and the capacitance ratio of each part is CCF, CFB, CFD, CFS = 5: 3: 1: 1, the floating gate is The potential VF of 102 is: Q = CCF (VF-VG) + CFB.VF + CFD (VF-V
D) + CFS · VF. Where VG is the control gate potential and VD
Is the drain potential, and Q is the floating gate accumulated charge amount. From this equation, VF = 0.6V + (Q / 10), and if the memory is completely erased by ultraviolet rays or the like, then Q = 0, so VF = 0.6V. That is, when the potential of the floating gate 102 becomes 0.6 V during reading, the memory cell becomes conductive.

Writing is to raise the threshold value of a memory cell, and erasing is to lower the threshold value.
M, writing in the flash memory is performed by injecting channel hot electrons (CHE) into the floating gate, that is, by making the floating gate potential VF negative and raising the threshold value. In addition, erasing is done by EPRO
In M, the ultraviolet rays are irradiated to excite the accumulated electrons, and in the flash memory, the accumulated electrons are extracted by the FN current as a tunnel current.

Next, the operation of a normal memory cell and a defective memory cell will be described with reference to FIG. In FIG. 2, when reading the memory cell, a voltage of about 1V is applied to the drain 103 via the bit line, and the control gate of the non-selected memory cell in which the row (word line) direction is not selected is 0V (ground potential). Becomes

In such a bias state, the potential of the floating gate 102 of the normal memory cell becomes 0.1 V due to the capacitive coupling between the floating gate 102 and the drain 103 via the capacitance CFD. The minimum potential of the floating gate 102 for making the drain 103 and the source 104 conductive is 0.6
It is lower than V and the normal memory cell does not conduct in the non-selected state.

On the other hand, in the defective memory cell, since the electrons in the floating gate 102 are excessively erased during the erasing, the potential of the floating gate 102 itself becomes 0.5 V, and the potential of the floating gate 102 becomes 0. 1V is applied, and the potential of the floating gate 102 eventually becomes 0.6V, so that the defective memory cell becomes conductive even in the non-selected state. The present invention detects such defective memory cells.

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram for explaining a defective memory transistor detecting method and a detecting device according to the present invention. In the figure, the same or corresponding parts as those in FIG. IM
Sense amplifier circuit (sense amplifier) 31 for determining "1" or "0" by means of a switching circuit which outputs a test enable signal TE for switching between normal read (in normal read mode) and test read. is there.

In FIG. 1, bit lines (columns) BL1 and BL
2 to column select gate 1 to select BLm 1
The drains of m are commonly connected, and the common line thereof is connected to the sense amplifier circuit 30. The sense amplifier circuit 30 is configured so that a test enable signal TE for switching between a normal read sense operation and a test read sense operation is input from a switch circuit 31.

Next, the operation of the circuit shown in FIG. 1 will be described. At the time of normal read, the test enable signal TE becomes 0 V (“L” level), and normal read operation is performed. This is done by a circuit as shown in FIGS. 3 and 4, for example.

FIG. 3 shows an example of a word line selection address input circuit. The word line selection address input circuit is a part of a circuit for selecting a word line, and only one address (corresponding to the address signal A0) is shown in FIG. This circuit is normally a
Although 0 and its inverted signal are generated, both signals are fixed to the “L” level during the test so that the word line cannot be selected. FIG. 4 is a circuit diagram showing an example of the sense amplifier circuit 30. The word line selecting address input circuit of FIG. 3 is composed of two NOR circuits 41 and 42. As can be seen from the circuit configuration, the "L" level signal TE has no effect on the address signal A0, and therefore it is a normal one. A word line (row) is selected by an address signal.

The sense amplifier circuit of FIG. 4 has a positive power supply terminal T
P-channel transistor P connected to 1, T2 and T3
1, P2, P3, an n-channel transistor N1 whose drain is connected to the source connection point B of the p-channel transistors P1, P2, and an n-channel transistor N2 whose drain is connected to the source of the p-channel transistor P3.
And an inverter INV1 arranged between the p-channel transistors P1 and P2, and a connection point C between the input side of the p-channel transistor P3 and the n-channel transistor N2.
And an inverter INV2 connected to the gate of the n-channel transistor N1 and the source of the n-channel transistor N2.
Is connected to a memory transistor (memory cell) Q controlled by a word line selection signal WS via a column select gate N controlled by.

When the "L" level signal TE is input to the p-channel transistor P1 of the sense amplifier circuit having such a configuration, the transistor P1 is turned on and the transistor P1 is turned on.
2 becomes non-conductive, and the connection point B is connected to the transistors P1 and N1.
The potential becomes according to the conduction resistance value of. This potential changes due to the operation of the transistor N1 whose gate input is the potential of the connection point A, and when the information of the memory transistor is "1", the potential of the connection point A is lowered by the current flowing through the bit line and rises. On the contrary, when the information of the memory transistor is "0", the potential of the connection point A rises due to the transistor N2, and the potential drops. By applying such feedback, it is preset so that the potential of the bit line during the normal read operation is maintained at about 1V. 1V
The reason for this is that when the voltage applied to the bit line BL is 2 V or higher, a phenomenon called soft write occurs in which the threshold value of the memory cell increases as the number of times of reading increases.

At the time of test read, the test enable signal TE becomes 5V ("H" level), and an operation different from the normal read operation is performed.

At the time of test reading, a signal TE of "H" level is input to NOR circuits 41 and 42 of the word line selecting address input circuit of FIG. 3, and both a0 and a0 become 0V. By this signal, all the word line selection signals WS0, WS1 to WSn are set to the level indicating non-selection, and the column corresponding to the column select signals CS1 and CS2 to CSm is selected from the bit lines (columns) BL1 to BLm.

Further, at the time of test reading, when the "H" level signal TE is input to the p-channel transistor P1 of FIG. 4, the transistor P1 is turned off and the transistor P1 is turned off.
2 becomes conductive, and the connection point B has a potential corresponding to the conduction resistance values of the transistors P2 and N1. This potential is preset so as to change so as to maintain the potential of the bit line at a voltage higher than usual, for example, 2V, by the same operation (feedback operation) as described above. As described above, the bit line BL during test read is 1 compared to the voltage of 1 V during normal read.
A voltage higher than V is applied.

Next, the operation at the time of test reading of the normal memory cell and the defective memory cell in this embodiment will be described with reference to FIGS. 1 and 2.

It is assumed that the memory cells Q11 to Qnm are all in the normal erased state and the bit line BL1 is selected by the column select signal CS. At this time, the potential VF of the floating gate 102 is 0 V when the voltage applied to the bit line BL is 0 V, and when a higher voltage (2 V) than usual is applied to the bit line BL1 by the circuit of FIG. Potential VF becomes equal to 0.2V due to capacitive coupling between the floating gate 102 and the drain 103. This potential is much lower than the potential (0.6 V) for conducting the memory cell, the drain current IM of the memory cell is less than or equal to the sense current Isense, and the sense amplifier circuit 30 determines that it is "0", that is, normal.

Next, the operation when the memory cell Q11 is a defective memory cell and the other memory cells Q21 to Qn1 are in the normal erased state will be described. The potential VF of the floating gate 102 of the defective memory cell is the bit line B
When the applied voltage of L1 is 0V, it becomes 0.5V, for example.
When 2V is applied to the drain 103 of the memory cell Q11 through the bit line BL1, the potential VF of the floating gate 102 rises by 0.2V to 0.7.
It becomes V. When the potential VF of the floating gate 102 becomes 0.7 V, the memory cell Q11 becomes conductive, the drain current IM exceeds the sense current Isense, and the sense amplifier circuit 30 determines "1", that is, abnormal.

By applying a bit line voltage higher than that during normal reading, it is possible to detect defective memory cells with high sensitivity. The higher the bit line voltage applied during the test read, the higher the detection sensitivity thereof, and the more severe the detection becomes. Regarding the soft write described above, the word line during the test is not selected and the detection operation is completed by reading once,
Its impact need not be taken into account.

[0040]

As described above, according to the first aspect of the present invention, during the test operation, the voltage is equal to or higher than the voltage of the non-selected row in the normal read mode, and the voltage is higher than the voltage of the non-selected row and the electrons are fed from the floating gate. Since all the rows are selected with a voltage lower than the normal threshold voltage of the released memory transistor and a voltage higher than that in the normal read mode is applied to the selected column to perform the read, the conventional writing, There is an effect that detection of a low threshold voltage memory cell, which takes time to repeat erasing, can be performed quickly and easily in the erased state.

According to the second aspect of the present invention, a switching circuit for outputting a test enable signal for switching between a sense operation in a normal read mode and a sense operation in a test read, and the test enable signal is a test signal. Since a sense amplifier for applying a voltage higher than that in the normal read mode to the column is provided when indicating the read time, switching between the normal read mode and the test read only requires a command by the test enable signal. There is an effect that the above switching can be performed easily and quickly.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a method and apparatus for detecting a defective memory cell according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing the configuration of a general memory cell.

FIG. 3 is a circuit diagram showing an example of a word line selection address input circuit.

FIG. 4 is a circuit diagram showing an example of a sense amplifier circuit.

FIG. 5 is a circuit diagram for explaining a conventional defective memory cell detection method and detection apparatus.

FIG. 6 is a characteristic diagram showing an erased state and a written state of a memory cell.

FIG. 7 is a characteristic diagram showing erased state characteristics of a normal memory cell and erased state characteristics of a defective memory cell.

[Explanation of symbols]

Q11 to Qnm memory cells (memory transistors),
30 sense amplifier circuit (sense amplifier), 31 switching circuit.

Claims (2)

[Claims] 1. A plurality of variable threshold nonvolatile semiconductor memory transistors, which inject electrons into a floating gate and emit electrons by electrical or ultraviolet irradiation, are connected in a row direction with their drains in a column direction. In a method of detecting defective memory transistors in a semiconductor memory device connected and arranged in a matrix, in a normal read mode, a memory transistor designated by an address signal is selected by a row decoder and a column decoder, and the information is sensed by a sense amplifier. During read and test operations, a voltage equal to the voltage of the non-selected row in the normal read mode, or a voltage higher than that and lower than the normal threshold voltage of the memory transistor that has emitted electrons from the floating gate. To select all rows and set the selected column higher than in the normal read mode. A method for detecting a defective memory transistor, which is characterized in that a voltage is applied to perform reading. 2. A gate of a plurality of variable threshold type non-volatile semiconductor memory transistors which inject electrons into a floating gate and emit electrons upon electrical or ultraviolet irradiation are connected in a row direction, and their drains are connected in a column direction. In a defective memory transistor detecting device in a semiconductor memory device connected and arranged in a matrix, a switching circuit that outputs a test enable signal for switching between a sensing operation in a normal read mode and a sensing operation in a test read, A defective memory transistor detection device comprising: a sense amplifier that applies a higher voltage to the column when the test enable signal indicates a test read time than in a normal read mode.