JPH0831190A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To lengthen the life time of a memory device by detecting whether a defective address occurring during use is already stored or not, and switching a defective address occurring in a main memory region to a redundant memory region. CONSTITUTION:An address signal is inputted to an address decoder 3 and control circuits 8, 9, 12. After the address signal is decoded by the decoder 3, a memory cell of a main memory region 1 or a redundant memory region 2 is selected and accessed by an address sub-decoder 4. This selection is performed by a circuit 12, and it is judged whether the address is already replaced by the region 2 or not. In the circuit 12, a block number of an address held in an address latch 11 is compared with a block number of a defective address already written in a defective address memory 6. When they coincide, the decoder 4 accesses the region 2, and when they don't coincide, the decoder 4 accesses the region 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device provided with an electrically writable / erasable memory life extension means, and more particularly, to a defect of a memory element which occurs when a flash memory or the like is used. The present invention relates to a non-volatile semiconductor memory device that relieves this product from a writing failure that occurs during writing.

[0002]

2. Description of the Related Art In a writable / erasable non-volatile semiconductor memory device represented by a flash memory, a defect of a memory element occurs when a writable / erasable operation is repeated.
For example, a defect occurs in the tunnel oxide film, resulting in a write failure. Occurrence of a memory cell defect due to deterioration of the tunnel oxide film depends on the number of times of writing, and the service life of the memory is determined. Such a write failure due to a defect in the tunnel oxide film also occurs in the memory manufacturing stage. Normally, when such a defective memory occurs, a spare memory cell (redundant memory) provided in the nonvolatile semiconductor memory device is provided. The production yield is improved by switching to a cell and operating normally. Further, even when the memory product is mounted on the device, a defect due to deterioration of the tunnel oxide film may occur accidentally.

From such a point of view, by developing a technique for avoiding the cause of the writing failure of the memory element itself, and skillfully avoiding the writing failure that occurs accidentally to maintain the normal operation state of the memory. , The technological development for the purpose of substantially extending the life of memory usage is in progress. As an example of means for avoiding the risk that the product life of a memory device accidentally occurs, a defect detection circuit that detects the presence of a defect during a write operation in the circuit of the memory device and an output from the defect detection circuit are used. And a logic circuit for receiving and deactivating the entire memory device. A method is also adopted in which the entire memory device is deactivated when a write failure occurs, and the user is notified of the failure occurrence.

FIG. 6 shows a conventional example of extending the life of the memory device disclosed in Japanese Patent Laid-Open No. 1-128300. In FIG. 6, 1 is a main memory area, 2 is a redundant memory area for compensating for memory cells in which a defect has occurred in the main memory area, 3 is a row address decoder, and 4 is when switching from the main memory area 1 to the redundant memory area 2. Switching circuit, 5
Is a control circuit for controlling the switching circuit 4, 6 is a non-volatile memory for storing the address of the defective memory cell, 7
Is a write control circuit for controlling the nonvolatile memory 6.

The operation of the memory device shown in FIG. 6 will be briefly described. If a defective bit is found by the characteristic inspection of the manufactured memory device, the address of this defective bit is stored in the nonvolatile memory 6 in advance. . When the defective bit is accessed during use of this memory product, that is, during reading or writing, the control circuit 5 detects this access and simultaneously generates a control signal to the switching circuit 4, Switching from the memory area 1 to the redundant memory area 2, the normal redundant memory area 2 corresponding to the defective bit
Allows access to a bit of. As a result, by repairing a memory device which is originally a defective product from a defect generated in a part of the main memory region 1, the manufacturing yield can be improved and the life can be substantially extended.

Next, the conventional automatic writing function will be described. This automatic writing function, in the process of automatically writing the specified information to the specified address of the memory,
It has the function of verifying the written state each time writing is performed (for example, USP 4460982). This feature
In the event that a write failure occurs while the memory is in use, assuming the situation that writing cannot be completed normally, the entire memory is stopped and a self-stop function is added to clearly indicate the occurrence of the failure to the user. There is. FIG. 7 is a block diagram of a conventional automatic write circuit, and its operation will be described. In the figure, the input address signal is temporarily held by the address latch 11 and then decoded by the address decoder 3 to select a certain block in the main memory area 1. On the other hand, the data signal is the data latch 1
It is temporarily held at 0 and then input to the main memory area 1. The data signals are simultaneously input to the first control circuit 8,
A high voltage for write control is applied to the main memory area 1. Data is written by these operations. Then, the first control circuit 8 performs a write verify operation, that is, reading the data of the written block, compares it with the data to be written held in the address latch 11, and confirms whether the data has been written correctly. If the comparison result is not correct, the write operation is repeated. The writing is performed the maximum number of times, and if the writing operation is not completed yet, the operation of the memory element itself is stopped by the first control circuit 8.

Next, the first control circuit 8 shown in FIG. 7 will be described with reference to the block diagram of FIG. In the figure, the data held in the data latch 10 is input to the multi-input NAND circuit 53 in the first control circuit 8. When a data signal other than "1" is input to all the data, "1" is input to the write control circuit 52. As a result, the automatic writing operation is started. That is, data is written to the address in the main memory area 1 indicated by the address input signal 36 input from the address latch 11, and subsequently, the verify circuit 51 performs the write confirmation operation up to the maximum number of times. As a result, if the writing is normally confirmed, the writing control circuit 52 writes to the next address. If the verify operation does not end normally, it is determined that the entire nonvolatile memory is defective, and the verify circuit 51 generates the entire chip operation stop signal 34 and sends it to the write control circuit 52 to operate the entire chip. Stop.

Next, an outline of the automatic write cycle in the conventional nonvolatile semiconductor memory device will be described with reference to the flowchart of FIG. This automatic writing is performed by the verify circuit 51 and the write control circuit 52. In the same figure, for example, it is an automatic write cycle of the flash memory in which 1 bit or 8 bits is a block unit. The block number K is set to 0 as shown in step S ₁ , and the block number K is sequentially incremented by 1 as shown in step S ₆ to write data in each block. In the process, writing is performed subsequently to each write operation (step S ₂₎ is one of the verification operation being carried out correctly (verification) (Step S _3). If the writing of the memory cell in a certain block is normally performed, the process proceeds to step S ₅ . In step S ₅ , it is determined whether or not it is the final block. If the last block, it is incremented by 1 block number K proceeds to step S _6, the write operation for the next block (step S _2). The writing verification of the memory cell in the next block is performed again (step S ₃ ). In the block S ₃ , even if writing to a block is not normal, writing to the block with the same data is repeated a finite number of times N, for example, N = 32 times at maximum. This repetition is performed while counting the number of repetitions N. If it is verified that normal writing has not been performed on the block even at the maximum number of times, the process proceeds to step S ₄ . In step S ₄ , it is determined that writing is not possible, and the operation of this memory device itself is stopped. The occurrence of defects is clearly indicated to the user of the memory device. Such writing and verification operation (verify) is performed for all blocks to complete the automatic writing.

[0009]

However, in the nonvolatile memory device having the life prolonging means shown in FIG. 6, the memory device can be repaired only by the manufacturer and the manufacturer using the memory device. Inspection is limited to the range. Therefore, the characteristics of the memory device can be inspected, the address of the defective memory cell can be detected, and the address of the defective memory cell can be detected.
It is up to the stage where you can write to. After that, for example, if a defect occurs while the user is using the memory product, even if the defective portion is a very small portion of the memory area, the redundant memory area 2 is You cannot write. Further, as shown in FIG. 7, in the case where the first control circuit 8 including the verify circuit 51 is provided, if a failure occurs while the user is using the memory product, the failure that has occurred. Even if the portion is a very small portion of the memory area, the whole chip operation stop signal 34 is applied to the write control circuit 52 as shown in FIG. That is, the self-stop function of the memory device itself operates, and the entire product incorporating the memory device stops operating. As a result, the user is forced to discard the product incorporating the memory device, which is uneconomical and not preferable.

The present invention has been made in view of the above-mentioned problems, and is a defect of a memory element that occurs when a non-volatile semiconductor memory device is used, in particular, a writing failure that occurs when information is written causes non-volatility. It is an object of the present invention to provide a non-volatile semiconductor memory device that can relieve a semiconductor memory device and substantially prolong its life.

[0011]

In order to achieve the above object, a first non-volatile semiconductor memory device according to the present invention includes a first storage means for storing a defective address generated in a main memory area and an address signal. For the input, when the address signal has already been stored as a defective address by the first storage means, a determination means, and if the determination means determines a new defective address,
Second storage means for storing in the redundant memory area.

A second non-volatile semiconductor memory device of the present invention is a second non-volatile semiconductor memory device provided with a first memory area formed of a non-volatile memory element and a defective memory cell in the first memory area. If the memory area, the defective address memory area for accumulating the address of the defective memory cell, and the address of the defective memory cell generated in the first memory area are not accumulated in the defective address memory area, the defective address memory is A control circuit for instructing storage of the defective address and an address switching circuit for switching an address signal from the first memory area to the second memory area when an address of a defective memory cell stored in the defective address memory area is accessed. And are provided.

A third non-volatile semiconductor memory device of the present invention is the second non-volatile semiconductor memory device according to the second non-volatile semiconductor memory device, wherein the first memory area or the second memory area corresponding to the address signal is used.
It is characterized by further comprising a data input circuit for writing data in the memory area. The fourth non-volatile semiconductor memory device of the present invention is the second and third non-volatile semiconductor memory device, wherein the data stored in the first memory area or the second memory area corresponding to the address signal is stored. Is further provided with a data output circuit for reading out. A fifth non-volatile semiconductor memory device according to the present invention is the second and third non-volatile semiconductor memory device according to the first memory area or the second non-volatile semiconductor memory device.
A self-stop circuit for detecting an abnormal storage of data written in a memory area or data of a defective address stored in the defective address memory area and instructing to stop the operation of the first memory area is further provided. It is what

A sixth non-volatile semiconductor memory device of the present invention includes a first memory area formed of a non-volatile memory element, a second memory area for compensating for a defect in the first memory area, and Third for compensating for defects in the second memory area
A memory area; a defective address memory area for storing an address of a defective memory cell in the first memory area or an address of a defective memory cell in the second memory area;
An address switching circuit that switches an address signal from a memory area to the second memory area or from the second memory area to the third memory area, and an address of a defective memory cell in the first memory area or a defect in the second memory area. When the address of the memory cell is not accumulated, the first control circuit for instructing accumulation of the defective address in the defective address memory area, and when the defective address accumulated in the defective address memory area is accessed, the address switching circuit And a second control circuit for instructing the operation of.

The seventh non-volatile semiconductor memory device of the present invention is the sixth non-volatile semiconductor memory device, wherein an abnormal storage of the data of the address of the defective memory cell stored in the defective address memory area is detected. In addition, a self-stop circuit for instructing stop of the operation of the first memory area is further provided. An eighth non-volatile semiconductor memory device according to the present invention includes a first memory area including a non-volatile memory element, and a second memory area prepared to supplement a defective memory cell in the first memory area. A defective address memory area for accumulating an address of a defective memory cell in the first memory area, an address switching circuit for switching an address signal from the first memory area to the second memory area, and written in the first memory area A first control circuit for verifying information and generating a signal instructing defect generation; and a second control circuit for controlling accumulation of an unaccumulated defect address by the defect address memory based on the signal instructing defect generation. A third control circuit for instructing an operation of the address switching circuit when a defective address accumulated in the defective address memory is accessed. And it is characterized in Rukoto.

A ninth nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the seventh aspect, wherein the first control circuit stores in the first memory area and the second memory area. It further comprises a self-stop circuit for detecting an abnormal write of the written data and instructing to stop the operation of the first memory area. A tenth non-volatile semiconductor memory device according to the present invention is the tenth non-volatile semiconductor memory device according to the tenth non-volatile semiconductor memory device, wherein the second control circuit detects an abnormal storage of a defective address stored in the defective address memory. In addition, a stop signal generating circuit for generating a signal instructing the operation of the self-stop circuit is further included.

[0017]

According to the present invention, even if a defect occurs in the first memory area during use of the nonvolatile semiconductor memory device,
The memory device can be repaired. Specifically, first, when a defective memory cell occurs in the first memory area, it is determined whether or not the defective memory cell has already occurred, and if the defect is a new defect. In addition, the address of the defective memory cell is stored in the defective address memory area to relieve the defective memory device. Further, when the address signal corresponding to the defective address is accessed, the address signal is transferred to the second memory area, which is a redundant memory area, and the data is read or written. In this way, since the defect in the first memory area is compensated by the second memory area, even if a defect occurs in the memory device, it can be relieved. That is, writing and reading of data are performed with respect to substantially two memory areas.

Furthermore, since a defect may occur not only in the first memory area but also in the second memory area,
It is also possible to provide a third memory area in order to eliminate the trouble caused by the defect in the memory area and transfer the address signal to the third memory area. Then, writing and reading of data are performed substantially for the three memory areas, and the degree of freedom of relief increases. It should be noted that adding a plurality of memory areas having the same function as the third memory area and transferring the address signal to the additional areas is an improvement that can be easily devised by those skilled in the art, and as a result, there are three or more areas. However, it does not depart from the scope of the present invention. Further, according to the present invention, a write failure in a defective address memory faces a fatal functional failure. Therefore, by adding a self-stopping mechanism for defective writing of the defective address memory to the memory device, it is provided for the convenience of the user. Further, in addition to the main memory area, the same memory area can be divided into several areas, and each area can be used as a redundant memory area.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a nonvolatile semiconductor memory device according to the present invention will be described below with reference to the drawings. The block diagram of FIG. 1 illustrates one embodiment of a non-volatile semiconductor memory device. In the figure, 1 is a main memory area, 2 is a redundant memory area for compensating for defective memory cells in the main memory area 1, 3 is an address decoder, and 4 is for switching from the main memory area 1 to the redundant memory area 2. An address sub-decoder, 6 is a defective address memory for storing an address of a defective memory cell generated in the main memory area 1, 8 is a first control circuit for performing a verify operation of the main memory area 1, and 9 is for occurrence of a defective memory cell. , A second step of performing a verify operation of the defective address memory 6 while judging the possibility of repair
A control circuit, 10 is a data latch for temporarily holding a data signal, 11 is an address latch for temporarily holding an address signal, and 12 is an address sub-decoder 4 for switching between the main memory area 1 and the redundant memory area 2. Is a third control circuit for controlling.

Next, with reference to the block diagram of FIG. 1, the operation of each unit at the time of automatically writing the data signal will be described. In the figure, the address signal is input and held in the address latch 11. The address signal is supplied to the address decoder 3, and the first to third control circuits 8,
Input to 9 and 12. After the address signal is decoded by the address decoder 3, a memory cell in the main memory area 1 or the redundant memory area 2 is selected and accessed by the address sub-decoder 4. This selection is made by the third control circuit 12, and it is judged whether or not the address is already replaced by the redundant memory area 2. In the third control circuit 12, the address latch 1
The block number of the address held in 1 is compared with the block number of the defective address already written in the defective address memory 6, and if the block number already replaced by the redundant memory cell matches, the address sub-decoder 4 is switched. The redundant memory area 2 is accessed for writing, and if they do not match, the main memory area 1 is accessed.

On the other hand, the data input signal is the data latch 1
After being held at 0, the data is supplied to the main memory area 1 or the redundant memory area 2 to write to the memory element selected by the address signal. The data input signal is supplied to the main memory area 1 and the redundant memory area 2 via the data latch 10 and at the same time sent to the first control circuit 8. In the first control circuit 8, the write verify operation is performed as described in the conventional example. In the write verify operation of the first control circuit 8, when a defective block having a defective memory cell is detected, a defect generation signal is generated. The defect occurrence signal is output from the first control circuit 8 to the second control circuit 9. The second control circuit 9 reads the address written in the defective address memory 6,
If the data is not written, it is determined that the defective memory block can be relieved. A defective memory block is detected by the write verify operation performed by the first control circuit 8, and the block number corresponding to the address of the defective memory cell is written to the defective address memory 6 again via the second control circuit 9. On the other hand, if data is already written in the defective address memory 6, it is determined that a new defective memory cannot be relieved, and a signal instructing the first control circuit 8 to stop operation is sent to the entire memory chip. Stop the operation of. Further, when there are a plurality of redundant memory areas 2 for defect relief, it is determined whether or not addresses have been written in the defective address memory 6 for all of these redundant memory areas 2.

As in the above embodiment, the redundant memory area 2
May be one memory area, or a plurality of first to third memory areas may be prepared. When a plurality of first to third memory areas are used as the redundant memory area 2, when an arbitrary address signal is accessed, it is determined whether or not the address is written in the defective address memory 6 as a defective address. If the address exists, the third control circuit 12 causes the address sub-decoder 4 to generate a switching signal to select and access the first to third memory areas of the redundant memory area 2. In order to enhance the effect of extending the life of the entire chip, it is desirable to hold a plurality of memory areas in this way. Of course,
Obviously, one memory area may be divided into three or more to form a redundant memory area divided into three or more.

FIG. 2 is a block diagram showing the second and third control circuits in more detail. In the figure, the second control circuit 9 includes a latch circuit 21, a comparator 22, [1, 1
..., 1] data 23, write / read circuit 24, O
R circuits 25 and 27, verify circuit 26, AND circuit 2
8 and an inverter circuit 29. The address signal is input to the write / read circuit 24 and the verify circuit 26 of the second control circuit 9 via the address latch 11, respectively. The third control circuit 12 is composed of a comparator 41, and receives an address signal via the address latch 11. The signal path of the data input / output signal is not shown.

Next, description will be made with reference to FIG. First, a case where a defect is detected by the verify operation of the first control circuit 8 when writing to the main memory area 1 will be described. The defect generation signal 31 is output from the first control circuit 8 to the second control circuit 9. In the second control circuit 9, the defect occurrence signal 31 is temporarily held in the latch 21. Latch 2
The output of 1 is used as the operation signal 32 of the comparator 22, and the comparator 22 starts its operation. In this comparator 22, writing / writing from the defective address memory 6 is performed.
The read signal 37 output from the read circuit 24 is compared with the [1, 1, ... 1] Data 23. By the way,
The [1, 1, ... 1] data 23 is stored in the defective address memory 6
Is data indicating an unused state. Comparator 22
Is for detecting the usage state of the defective address memory 6. In the comparator 22, the write / read circuit 2
As a result of reading the contents of the defective address memory 6 by 4, the output 1 is "1" (unused signal 33) if the defective address memory 6 is unused, and "0" if it is used. These signals are inverted by the inverter 29 to "1" (unused signal 33) or "0" (used signal) and sent to the OR circuit 27. When “1” is input as the used signal through the OR circuit 27, it is transferred to the first control circuit 8 as the whole chip operation stop signal 34. That is, although the defective memory block is detected, but the defective address memory 6 has already been used, it is determined that a new defective memory block cannot be repaired, and the operation of the entire chip is stopped. This embodiment has a basic function of a self-stop circuit for stopping the operation of the entire chip, which is similar to the conventional one when such a repair is impossible.

Next, reading / writing of the defective address memory 6
The write control will be described. Bad address memory 6
The read / write control is controlled by the write / read circuit 24 including the generation of the control high voltage. When the write instruction signal 35 is input, the write / read circuit 24 writes the address latch 11 in the defective address memory 6.
After writing the data corresponding to the address input signal 36 from, the verify instruction signal 38 is transferred to the verify circuit 26. In the write / read circuit 24,
It has a function of reading the contents of the defective address memory 6 and outputting a read signal 37 as another function.

The operation signal 32 from the latch 21 and the output signal (unused signal 33) of the comparator 22 are input to the AND circuit 28, and the logical product of these signals is taken. Further, the output from the AND circuit 28 and the output from the verify circuit 26 are input to the OR circuit 25, and the output from the OR circuit 25 is used as the write instruction signal 35 of the write / read circuit 24. When a write failure occurs in the main memory area 1, that is, the operation signal 32
AND circuit 2 of (defect occurrence signal 31) and unused signal 33
By the output of 8, the defective address memory 6 when a defect occurs
If it is determined that the defective memory generated in the main memory area can be repaired, it is determined that the address input signal 36 held in the address latch 11 is written in the defective address memory 6. I do.

On the other hand, when the verify circuit 26 receives the verify instruction signal 38 from the write / read circuit 24, it compares the read signal 37 with the address input signal 36. The verify circuit 26 compares the two, and if there is a difference between the two, the write instruction signal 3 is again sent via the OR circuit 25.
5 is output to the write / read circuit 24, and the verify operation is repeated. In the verify circuit 26, the above operation is repeated a maximum number of times to generate a write failure signal 39 if writing is not completed normally, and a relief end signal 40 is generated if writing is completed normally. The OR circuit 27 ORs the write failure signal 39 and the inverted unused signal 33 obtained via the inverter 29. Since both are signals indicating that the defective memory cell cannot be relieved, they are transferred to the first control circuit 8 as the whole chip operation stop signal 34 via the OR circuit 27.
The non-volatile semiconductor memory device has a self-stop function and stops. The repair end signal 40 output from the verify circuit 26 is a signal indicating that the repair of the defective memory element is normally completed. The repair end signal 40 is transferred to the first control circuit 8 and instructs the automatic write operation with the same block number to be performed again. At the same time, the latch 21 is reset and the held defect occurrence signal 3 is reset.
Reset 1

The third control circuit 12 is composed of a comparator 41 and controls switching of the address sub-decoder 4. The address input signal 36 held in the address latch 11 is compared with the read signal 37 read from the defective address memory 6 by the write / read circuit 24 of the second control circuit 9. As a result of comparison by the comparator 41, if the two match, it is determined that the data needs to be written in the redundant memory area 2 instead of the main memory area 1. In that case, comparator 4
The output of 1 switches the address sub-decoder 4 from the main memory area 1 to the redundant memory area 2. The address input signal 36 is transferred to the redundant memory area 2 and data is written therein. In addition, as a result of comparison by the comparator 41,
If the two are different, the address input signal 36 is transferred to the memory cell of the corresponding block number in the main memory area 1 as usual, and the data is written.

Next, an embodiment of the first control circuit 8 shown in FIG. 2 will be described with reference to FIG. In the figure, the operation up to the point where a write operation and a subsequent write verify operation are performed on the address input signal 36 are the same as in the conventional example.
When the verify operation is performed the maximum number of times but the writing is not normally performed, the entire chip operation stop signal 34 is generated to stop the operation of the entire chip as described in the conventional example shown in FIG. I am letting you. But,
In the present invention, the same whole chip operation stop signal 34 is caused to function as the defect generation signal 31 and sent to the second control circuit 9. As described above, the second control circuit 9 relieves the defective memory cell (defective memory block included in the defective memory cell) generated in the main memory area 1. When the defect relief is completed, the relief completion signal 40 is transferred to the first control circuit 8 and is applied to the AND circuit 55 as a negative pulse by the pulse generation circuit 54 of the first control circuit 8. A NAND circuit 53 to which the negative pulse from the pulse generation circuit 54 and the data input signal of the data latch 10 are input to the AND circuit 55.
Output signal is input, a logical product is obtained, and the output pulse is applied to the write control circuit 52. This means that all "1" s are NAND as data input signals.
When the actual data signal is input after being input to the circuit 53, the write control circuit 52 is to start automatic writing. Therefore, the write control circuit 52 starts the automatic write operation by reproducing the state where all the data input signals are "1" by the pulse generated by the pulse generation circuit 54. Since the address input signal and the data input signal are held in the address latch 11 and the data latch 10, respectively, the automatic write operation is performed again for the memory cell that has repaired the defective memory cell. If the second control circuit 9 cannot repair the defective memory block generated in the main memory area 1,
Whole chip operation stop signal 3 generated from the second control circuit 9
4, the operation of the write control circuit 52 is stopped. That is, the self-stop circuit of the nonvolatile semiconductor memory device operates to stop the operation.

Next, the control will be described with reference to FIG. 4 with reference to the flow chart of the automatic write cycle of the above embodiment. This automatic write cycle is programmed in the ROM or the like and is controlled by the CPU (central processing unit). An example of the control method is shown below in FIG.
Will be described with reference to. In FIG. 4, as in FIG. 7, the block number K is set to 0 in step S ₁ , and the block number K is sequentially incremented from 0 by 1 as shown in step S ₆ , and writing is performed in each block. At that time, in step S ₂ , it is judged whether or not the block number has already been relieved of the defective memory block by reading the contents of the defective address memory. If the defective block does not exist in the main memory area 1, the process proceeds to step S ₃ and the main memory area 1 is written. If the defective block exists, it is determined that the block is replaced by the redundant memory area 2, and the step is executed. Proceed to S ₇ , and write in the redundant memory area 2. Then, the process proceeds to step S ₄ , and the maximum number of times N (for example, N = 3) is the same as in the conventional technique described above.
The write verify operation up to 2) is performed, and step S
If it is confirmed that normal writing has been performed in ₅ increments the block number K proceeds to step S _6, the process proceeds to write the next block.

In step S ₄ , if the write operation is not normally completed even after the maximum number of verify operations, it is determined that there is a defective memory cell, and the process proceeds to step S ₈ . In step S _8, the second control circuit 9 reads the contents of the defective address storing nonvolatile memory (defective address memory) 6, already address to detect whether stored. As the detection result,
It is determined whether the defective memory generated in the main memory area 1 is being relieved. When it is determined that the relief has already been made, that is, the redundant memory area 2 has already been used,
This is the case where it is determined that the defect of the memory cell has occurred, and therefore it is determined that the new defective memory cannot be relieved, and the operation of the entire chip is stopped. Step S ₈
If there is an unused part in the defective memory address,
The block number K of the defective address is written in the defective memory cell 6 which is a nonvolatile memory prepared in advance for recording the defective block address. The writing method of the defective address memory 6 is similar to the other writing methods. That is, as shown in step S ₁₀ , if the write verify operation is performed up to the maximum number of times and the writing is not normally completed even after performing the verify of the maximum number of times,
The operation of the entire chip is stopped because it is impossible to repair the defective memory element any more. On the other hand, if the write verify operation is completed normally, the process proceeds to step S ₂ .
The write operation for the same block number K is performed again. The verify operation in step S ₄ is performed in the main memory area 1
Alternatively, the redundant memory area 2 is made by the first control circuit 8 and the defective address memory 6 is made by the second control circuit 9.

Next, the control of the second control circuit 9 will be described based on the flowchart of FIG. This control is usually performed by a CPU (central processing unit). First control circuit 8
As a result, when a defective memory cell (defective memory cell) is detected in the write verify operation to a memory block in the main memory area 1, as shown in step S ₁ , the first control circuit 8 outputs a defective block detection signal (defective The generated signal 31) is transferred to the second control circuit 9. Second control circuit 9
Receives this signal and starts the operation of reading the contents of the defective address memory 6. Succeedingly, in the step S ₂ , if it is detected that the address block number is already recorded in the defective address memory cell 6, the step S ₂ is executed.
_Proceeding to step ₆ , the first control circuit 8 is made to stop the operation of the entire chip because it is impossible to repair the defective memory any more. On the other hand, if the defective address memory 6 is not used, the process proceeds to step S ₃ and the memory block number in which the defect is detected is written in the defective address memory 6. Step S
_Proceeding to ₄ , the verify operation is performed up to the maximum number of times for writing to the defective address memory 6. Here, if the write verification to the defective address memory 6 is not completed even after performing the maximum number of times, the process proceeds to step S ₆ , and it is determined that the defective address memory 6 itself is defective. To stop the operation of. On the other hand, when the verification of the defective address memory 6 is completed, the repair operation for the memory block in which the write failure has occurred is completed. Therefore, the repair end signal 40 is transferred to the first control circuit 8 to complete the repair operation. Give instructions. In response to this, the first control circuit 8 restarts the automatic write operation by newly writing the same data in the redundant memory block. By such an operation, the life of the nonvolatile semiconductor memory device can be extended.

As described above, in the present invention, first, it is confirmed whether or not the block number corresponding to the memory cell in which the defective memory cell has occurred has already been relieved of the defective memory block. If the writing to the defective address memory has already been completed, the writing to the redundant memory cell is selected, and the verify operation is continued after the writing to the redundant memory cell. After that, at the time of writing, it is determined whether the redundant memory block has been replaced, and the defective address is written to the redundant memory cell, and otherwise, the operation of writing to the main memory area 1 is performed. Here, if the defective address memory 6 is in an unused state and the defective memory block can be relieved, a maximum of the write operation of the defective block number to the defective address memory 6 is given by the instruction of the second control circuit 9. Perform the write verify operation for the number of times. If the writing is not completed at this time, the first control circuit 8 is instructed to stop the operation of the entire chip. Further, when the defective memory block is detected during the write verify and the above condition that the defective memory can be newly relieved is satisfied, the address signal currently held in the address latch 11 is sent to the main memory to the address sub-decoder 4. The third control circuit 12 switches the address sub-decoder 4 so that the redundant memory area 2 is accessed instead of the corresponding block in the area 1, and the redundant memory area 2 is selected. At the same time, the data for the address held in the data latch 10 is transferred to the redundant memory area 2.

At the time of this switching, the write control signal from the first control circuit 8 is output to the second control circuit 9. Therefore, as a result of the maximum number of verify operations in the write cycle to the main memory area 1, the content of the memory cell determined to be defective will be written to the redundant memory area 2 again. Subsequently, similarly to the conventional example, the first control circuit 8 performs the verify operation up to the maximum number of times for the writing to the redundant memory area 2. After that, the defect generated in the main memory area 1 is replaced by the redundant memory area 2, and the writing to the block in which the defect repair is performed is performed by the third control circuit 12 and the address sub-decoder 4 to the redundant memory area 2. Since the access can be performed and the defect generated during use can be compensated, the life of the non-volatile semiconductor memory device can be substantially extended.

It is obvious that the redundant memory area 2 and the defective address memory 6 of the embodiment can be used as long as the memory cells have a nonvolatile structure. On the other hand, as the redundant memory area 2 and the defective address memory 6, it is desirable to use a flash memory cell having the same structure as the main memory area 1 from the viewpoint of simplification of the manufacturing process. Further, in the embodiment, it is clear that the main memory area can be applied to both the flash memory of the dual power supply system and the single power supply system.
It goes without saying that the present invention can be applied to all writable / erasable nonvolatile semiconductor memories including ultraviolet erasable type. Of course, the above verify operation is performed only when a write / read abnormality occurs, and since it is not necessary to perform the verify operation after that, the write / read operation is not delayed.

[0036]

As described above, according to the present invention, even if a defective memory cell (defective address) occurs during use, by switching to the redundant memory cell, electrically erasable and writable nonvolatile This is an extremely effective method that can repair a defective memory cell that has occurred in a semiconductor memory device and substantially extend the life.
Next, the effect which occurs in each claim will be shown. According to a first aspect of the present invention, by detecting whether or not the defective address generated during use is already stored, the defective address generated in the main memory area is switched to the redundant memory area to extend the life of the nonvolatile semiconductor memory device. There is an effect that can be. By providing the control circuit and the address switching circuit according to claim 2, it is detected whether or not the address of the defective memory cell generated in the first memory area during use is already stored,
It is intended to prolong the life of a non-volatile semiconductor memory device by making it possible to perform a switching operation of a memory area in response to an address input signal. By providing the data input circuit of claim 3, there is an advantage that the data in the first and second memory areas is written.

By providing the data output circuit of claim 4, there is an advantage that the data in the first and second memory areas can be read. By providing the self-stopping circuit of claim 5, there is an advantage that loss of operation and input time can be minimized. By providing the third memory area which is the redundant memory area of the sixth aspect, it is possible to prolong the life of the nonvolatile semiconductor memory device even if a defective address occurs in the second memory area.

By providing the self-stop circuit of claim 7, there is an advantage that the user can be notified of the occurrence of the defect and the error at the time of input can be minimized. By providing the first control circuit according to claim 8, the information written in the first memory area is verified, thereby efficiently detecting the defective address and prolonging the life of the nonvolatile semiconductor memory device. . By providing the self-stop circuit of claim 9, there is an advantage that a user can be notified of the occurrence of a defect and an error can be minimized at the time of input. By providing the self-stop circuit by operating the self-stop circuit from the stop signal generation circuit of claim 10, there is an advantage that the user can be notified of the occurrence of a defect and the error at the time of input can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of second and third control circuits in FIG.

3 is a block diagram showing an embodiment of the first control circuit of FIG. 1. FIG.

FIG. 4 is a flowchart of an automatic write cycle.

FIG. 5 is a flowchart showing the operation of the second control circuit.

FIG. 6 is a block diagram showing an example of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a block diagram showing an example of a conventional nonvolatile semiconductor memory device.

8 is a block diagram of the first control circuit of FIG. 7. FIG.

FIG. 9 is a flowchart showing the operation of a control circuit of a conventional example.

[Explanation of symbols]

 1 Main Memory Area 2 Redundant Memory Area 3 Address Decoder 4 Address Sub Decoder 6 Defective Address Memory 8 First Control Circuit 9 Second Control Circuit 10 Data Latch 11 Address Latch 12 Third Control Circuit

Claims (10)

[Claims] 1. In a non-volatile semiconductor memory device, first storage means for storing a defective address generated in a main memory area, and said address signal is already a defective address when the address signal is input. And a second storage unit that stores the redundant address in a redundant memory area when the determination unit determines that the defective address is a new defective address. Non-volatile semiconductor memory device. 2. A first memory area formed of a non-volatile memory device, a second memory area prepared to supplement the defective memory cell of the first memory area, and an address of the defective memory cell is accumulated. A defective address memory area; and a control circuit for instructing the defective address memory to store the defective address when the address of the defective memory cell generated in the first memory area is not accumulated in the defective address memory area, A non-volatile semiconductor comprising: an address switching circuit that switches an address signal from the first memory area to the second memory area when an address of a defective memory cell accumulated in the defective address memory area is accessed. Memory device. 3. The nonvolatile semiconductor memory device according to claim 2, further comprising a data input circuit that writes data in the first memory area or the second memory area corresponding to the address signal. 4. The data output circuit according to claim 2, further comprising a data output circuit for reading out data stored in the first memory area or the second memory area corresponding to the address signal.
A nonvolatile semiconductor memory device according to claim 1. 5. The operation of the first memory area is stopped by detecting an abnormal storage of data written in the first memory area or the second memory area or data of a defective address stored in the defective address memory area. 4. The non-volatile semiconductor memory device according to claim 2, further comprising a self-stop circuit for instructing. 6. A first memory area including a non-volatile memory device, a second memory area for compensating for a defect in the first memory area, and a third memory for compensating for a defect in the second memory area. A region, a defective address memory region for storing an address of a defective memory cell in the first memory region or an address of a defective memory cell in the second memory region, and the first memory region to the second memory region, or An address switching circuit for switching an address signal from the second memory area to the third memory area; and when the address of the defective memory cell of the first memory area or the address of the defective memory cell of the second memory area is not accumulated, A first control circuit for instructing accumulation of a defective address in the defective address memory area, and a defective address accumulated in the defective address memory area And a second control circuit for instructing the operation of the address switching circuit when is accessed. 7. A self-stop circuit for detecting an abnormal storage of data of an address of a defective memory cell stored in the defective address memory area and instructing to stop the operation of the first memory area. The non-volatile semiconductor memory device according to claim 6. 8. A first memory region formed of a non-volatile memory device, a second memory region prepared to supplement the defective memory cell of the first memory region, and a defective memory cell of the first memory region. A defective address memory area for accumulating an address, an address switching circuit for switching an address signal from the first memory area to the second memory area, and verifying information written in the first memory area to indicate a defect occurrence. A first control circuit for generating a signal; a second control circuit for controlling accumulation of an unaccumulated defect address by the defect address memory based on the signal instructing the defect generation; and a defect address accumulated by the defect address memory And a third control circuit for instructing the operation of the address switching circuit when accessed. Conductor memory device. 9. The self-stop circuit, wherein the first control circuit detects a write abnormality of data stored in the first memory area and the second memory area and instructs the operation stop of the first memory area. The non-volatile semiconductor memory device according to claim 7, further comprising: 10. The second control circuit further includes a stop signal generation circuit for detecting an abnormal storage of defective addresses stored in the defective address memory and generating a signal instructing the operation of the self-stop circuit. The nonvolatile semiconductor memory device according to claim 9, comprising: