JPH0830436A - Bit search circuit - Google Patents

Abstract

PURPOSE:To contrive high-speed operation by shortening a discharge time. CONSTITUTION:Sixteen-bit input signals /D15-/DO are divided by every successive 4 bits and inputted to encoders 5a-5d. The encoders 5a 5d output 2-bit encoded signals Ea-Ed and flag signals /Fa/Fd. The flag signals /Fa-/Fd specify the encoders 5a-5d including bits of '0' level and are inputted to an encoder 5e. A selector 6 selects the encoded signals of the encoders 5a-5d including the bits of '0' level based on the encoded signal of the encoder 5e and outputs them. A coupler 7 couples the encoded signal of the encoder 53 and the encoded signal selected by the selector 6 so that the former encoded signal is on the high-order bit side and the latter encoded signal is on the low-order bit side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit search circuit used in a microcomputer.

[0002]

2. Description of the Related Art FIG. 10 shows a dynamic 16-bit priority encoder which constitutes a conventional bit search circuit. D15 to D0 are input signals to be operated. Calculated input signal Dn (n = 15, 14, to 0)
Are precharge / discharge units 1-n, respectively.
(N = 15, 14, ~ 0).

Precharge discharge unit 1-n
Is an N-channel MOS transistor Nn (n = 15,
14, to 0) and P-channel MOS transistor Pn
(N = 15, 14, to 0).

The source and drain of the MOS transistor Nn are connected to the carry line 2, and the gate of the MOS transistor Nn receives the operated input signal Dn. Calculated input signal Dn
Serves as a control signal for switching the MOS transistor Nn. The source of the MOS transistor Pn is the power supply VC
It is connected to C, and the gate is supplied with a precharge signal / PR.

The drain of the MOS transistor Pn is connected to the node 3-n (n = 15, 14, ... 0). The node 3-n is the source / drain of the MOS transistor Nn of the precharge / discharge unit 1-n and the MOS transistor N of the precharge / discharge unit 1- (n-1). It is a connection point with the source / drain of (n-1).

However, the node 3-0 (that is, n = 0) is the source / drain of the MOS transistor of the precharge / discharge unit 1-0 and the source / drain of the discharge MOS transistor M1. -This is the connection point with the drain.
Also, the MO of the precharge / discharge unit 1-15
A connection point between the source / drain of the S transistor and the source / drain of the discharge MOS transistor M2 is designated as a node 3-16.

On the upper bit (D15) side,
The source of the P-channel MOS transistor P'is connected to the power supply VCC, and the gate is connected to the precharge signal / P.
R is entered. The drain of the MOS transistor P'is connected to the node 3-16.

MOS transistor for discharge M1
The source drain is connected between one end of the carry line 2 on the lower bit (D0) side and the ground point GND. Source MOS transistor M2 for discharge
The drain is the upper bit (D1 of carry line 2).
It is connected between one end on the 5) side and the ground point GND.

Each node 3-n (n = 16, to 0) has a MOS when the precharge signal / PR becomes "0" level.
Since the transistors Pn (n = 15 to 0) and P'are turned on, they are precharged to the "1" level (power supply potential VCC).

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the upper bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

Each node 3-n (n = 16, to 0) is discharged to the "0" level (ground potential) according to the level of the input signal Dn (n = 15 to 0). Will be The bit select / encoder circuit 4 receives the operation input signal Dn and each precharge / discharge unit 1-
The potential of the node 3-n of n is input. The bit select / encoder circuit 4 outputs 4-bit encode output signals Q3 to Q0.

The priority encoder having the above construction is
It has a static circuit configuration by a combination gate. Therefore, although high speed is achieved, many logic circuits are required for coding, and the circuit scale dramatically increases from several times to several tens of times as the number of bits of the input signal increases. It has the drawback of becoming larger.

Further, the priority encoder having the above structure is
The carrier line is constituted by pass transistors. Therefore, the ratio of the area of the priority encoder to the entire chip area can be made relatively small. However, as the number of bits of the input signal increases, it takes time to discharge each node of the carry line.

Next, the operation of the priority encoder of FIG. 10 will be described. This priority encoder
The counter has a function of determining which bit of the operated input signal Dn is at the "0" level.

First, consider the lower bit priority mode. The precharge signal / PR goes to "1" level and each node 3-n (n = 16, to 0) goes to "1" level (power supply potential V
CC) is precharged. After this, the control signal PRL
H becomes "1" level, the control signal PRHL becomes "0" level, the MOS transistor M1 is turned on, and the MOS transistor M2 is turned off.

Then, each node 3-n is discharged in accordance with the level of the input signal Dn to be operated. For example,
When only the most significant bit (D15) is at "0" level and the other bits (D14 to D0) are at "1" level, the discharge from node 3-0 to node 3-15 is sequentially performed. Will be done.

Next, consider the upper bit priority mode. The precharge signal / PR goes to "1" level and each node 3-n (n = 16, to 0) goes to "1" level (power supply potential V
CC) is precharged. After this, the control signal PRH
L becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on, and the MOS transistor M1 is turned off.

Then, each node 3-n is discharged in accordance with the level of the input signal Dn to be operated. For example,
When only the most significant bit (D0) is at "0" level and the other bits (D15 to D1) are at "1" level, the discharge from node 3-15 to node 3-0 is sequentially performed. Will be done.

As described above, in the case of the lower bit priority mode, only the bit on the most significant bit side is at the "0" level, and in the case of the higher bit priority mode, the bit on the least significant bit side. In the case that only one is at "0" level, there is a drawback that the discharge time becomes long.

This disadvantage is that the number of bits of the input signal Dn to be operated is 32 bits (n = 31, 0) and 64 bits (n =
63, to 0), which becomes remarkable and becomes a bottleneck for high-speed arithmetic processing.

[0022]

As described above, in the priority encoder that constitutes the conventional bit search circuit, the discharge time becomes longer as the number of bits of the input signal to be operated increases, and this number of bits becomes larger. There is a drawback that the increase in the number becomes a bottleneck in high-speed arithmetic processing.

The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to provide a bit search circuit capable of operating at a high speed in a small area even if the number of bits of an input signal to be operated increases. That is.

[0024]

In order to achieve the above object, the bit search circuit of the present invention is configured such that continuous 2 ^j (j is a natural number) bits of an i-bit input signal are input.
Outputs a flag signal indicating whether it contains a first level bits Some of the 2 ^j bits, and the 2 ^j
2 ^k (where i = 2 ^{j + k} ) number of j-bit first encoded signals for specifying the first level bit when the bit includes the first level bit Of the first encoder and the flag signals of the respective first encoders are input, and the k-bit first encoder for specifying the first encoder including the bit of the first level based on the flag signal is input. A second encoder for outputting a two-encoder signal and a second encoder signal for the second encoder are input, and a first encoder for the first encoder specified by the second encoder signal is input. A selector for selecting and outputting one encode signal,
The second and first encoding signals of the second encoder are on the upper bit side, and the first and first encoding signals of the specified first encoder are on the lower bit side, and the first and second
And a concatenator for concatenating the encode signals and outputting a j + k-bit third encode signal for specifying a first level bit included in the i-bit input signal.

The first and second encoders have a function of selecting and designating an upper bit priority mode and a lower bit priority mode. In the upper bit priority mode, the i bit is selected. The first level bit of the most significant bit of the input signals is specified, and in the least significant bit priority mode, the first bit of the most significant bit of the i bits of the input signal is specified. Identify one level of bits.

[0026]

According to the above configuration, an i-bit input signal is converted into 2 ^j
Each block is divided into 2 ^k blocks (first encoder) (that is, i = 2 ^{j + k} ) and the first search of the first level bit is performed for each block. After that, the second search is performed by the second encoder to determine in which of the 2 ^k blocks the bit of the first level exists.

Thus, the first from the i-bit input signal
By dividing the level bit search method into two stages, the discharge time of the first and second encoders can be greatly shortened. That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits (i) of the input signal increases. Further, since the i-bit input signal is divided into 2 ^k blocks in units of 2 ^j bits, it is possible to reduce variations in the discharge time.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The bit search circuit of the present invention will be described in detail below with reference to the drawings. [A] FIG. 1 shows a 16-bit bit search circuit according to the first embodiment of the present invention.

This bit search circuit comprises five priority encoders 5a-5e, a selector 6 and a coupler 7.
It consists of The priority encoder 5a has a continuous 4-bit operand input signal D15 on the upper side.
~ D12 has been input. The priority encoder 5a encodes which bit of the operated input signals D15 to D12 is at "0" level, and outputs the result as a 2-bit output signal Ea. The priority encoder 5a also outputs a 1-bit flag output signal / Fa indicating whether or not the operated input signals D15 to D12 include "0" level bits.

That is, if at least one bit of the operated input signals D15 to D12 is "0" level, the flag output signal / Fa becomes "0" level. If all bits of the input signals D15 to D12 are "1" level, the flag output signal / Fa is "1" level.

The priority encoder 5b is supplied with continuous 4-bit processed input signals D11 to D8 on the upper side. The priority encoder 5b encodes which bit of the operated input signals D11 to D8 is at "0" level and outputs the result as a 2-bit output signal Eb. Further, the priority encoder 5b is provided with the operation input signals D11 to D.
It also outputs a 1-bit flag output signal / Fb indicating whether or not 8 includes a "0" level bit.

That is, if at least one bit of the input signals D11 to D8 is "0" level, the flag output signal / Fb is "0" level. When all the bits of the input signals D11 to D8 are "1" level, the flag output signal / Fb is "1" level.

The priority encoder 5c is supplied with 4-bit continuous input signals D7 to D4 on the lower side. The priority encoder 5c encodes which bit of the operated input signals D7 to D4 is at "0" level, and outputs the result as a 2-bit output signal Ec. Further, the priority encoder 5c is provided with the operation input signals D7 to D4.
1 indicating whether or not a bit of "0" level is included in
A bit flag output signal / Fc is also output.

That is, if at least one bit of the operated input signals D7 to D4 is at "0" level, the flag output signal / Fc becomes "0" level. If all the bits of the input signals D7 to D4 are "1" level, the flag output signal / Fc becomes "1" level.

The priority encoder 5d is supplied with 4-bit continuous input signals D3 to D0 on the lower side. The priority encoder 5d encodes which bit of the operated input signals D3 to D0 is at "0" level and outputs the result as a 2-bit output signal Ed. Further, the priority encoder 5d is provided with operated input signals D3 to D0.
1 indicating whether or not a bit of "0" level is included in
The bit flag output signal / Fd is also output.

That is, if at least one bit of the input signals D3 to D0 is "0" level, the flag output signal / Fd is "0" level. If all the bits of the input signals D3 to D0 are "1" level, the flag output signal / Fd becomes "1" level.

The priority encoder 5e has a flag output signal / F for the priority encoders 5a-5d.
a to / Fd are input respectively. The priority encoder 5e encodes which bit of the input signals / Fa to / Fd is at the "0" level, and outputs the result as a 2-bit output signal Ee.

The selector 6 has a priority encoder.
The output signals Ea to Ed of the das 5a to 5d are input.
The selector 6 receives the priority encoder based on the 2-bit output signal Ee of the priority encoder 5e.
One of the output signals Ea to Ed of the das 5a to 5d is selected and output.

The 2-bit output signal Ee of the priority encoder 5e and the 2-bit output signal E'of the selector 6 are input to the coupler 7. The coupler 7 connects the both output signals to each other with the output signal Ee on the upper side and the output signal E ′ on the lower side, and outputs the 4-bit output signal EOUT.

FIG. 2 shows the configuration of the priority encoders 5a to 5d shown in FIG. Since each priority encoder has the same configuration, the configuration will be described using the priority encoder 5a as an example.

The priority encoder 5a is composed of four selectors 10-3, 10-0 and an encoder stage 11. The operated input signal D15 is inputted to the selector 10-3, and the selector 10-2 is
The operated input signal D14 is input, the operated input signal D13 is input to the selector 10-1, and the selector 10-
The operated input signal D12 is input to 0.

Each selector has the same structure. Therefore, the selector 10-3 will be described. The selector 10-3 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source and drain of the MOS transistor N3 are connected to the carry line 8, and the gate of the MOS transistor N3 receives the operated input signal D15. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the NOR circuit 15 has an input signal D15 to be operated.
And the output signal of the AND circuit 14 is input, and the output signal is input to the encoder stage 11.

The encoder stage 11 is a selector 10
In response to the output signals of -3 to 10-0, a 2-bit output signal Ea indicating which bit of the input signals D15 to D12 is at "0" level is output, and the input signal to be operated is A 1-bit flag output signal / Fa indicating whether or not a bit of "0" level is included in D15 to D12 is output.

An N-channel MOS transistor M1 for discharge is connected to the lower bit side end of the carry line 8. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is at "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

The respective nodes are operated input signals D15, ... D.
According to the 12 levels, it is discharged to the "0" level (ground potential). FIG. 3 shows the configuration of the priority encoder 5e shown in FIG.

The priority encoder 5e is composed of four selectors 10-3, 10-0 and an encoder stage 11. An output signal / Fa of the priority encoder 5a is input to the selector 10-3, an output signal / Fb of the priority encoder 5b is input to the selector 10-2, and a priority signal is input to the selector 10-1. The output signal / Fc of the encoder 5c is input, and the output signal / Fd of the priority encoder 5d is input to the selector 10-0.

Each selector has the same structure. Therefore, the selector 10-3 will be described. The selector 10-3 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source / drain of the MOS transistor N3 is connected to the carry line 8, and the operated input signal D15 is input to the gate. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the output signal / Fa of the priority encoder 10-3 and the output signal of the AND circuit 14 are input to the NOR circuit 15, and the output signal is input to the encoder stage 11.

The encoder stage 11 is a selector 10
In response to the output signals of -3 and 10-0, a 2-bit output signal Ee indicating which bit of the output signals / Fa to / Fd of the four priority encoders is the "0" level is output. To do.

An N-channel MOS transistor M1 for discharge is connected to the end of the carry line 8 on the lower bit side. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, the control signal PRHL becomes "1" level and the control signal PRLH becomes "0" level, so that the MOS transistor M2 is turned on.
The MOS transistor M1 is turned off.

Each node has a corresponding input signal D15, ... D.
According to the 12 levels, it is discharged to the "0" level (ground potential). Next, the operation of the bit search circuit of FIGS. 1 to 3 will be described. Table 1 shows the operations of the priority encoders 5a to 5d.

[0063]

[Table 1] Table 2 shows the operation of the priority encoder 5e.

[0064]

[Table 2] Table 3 shows the operation of the selector 6.

[0065]

[Table 3]

First, the upper bit priority mode (backward mode)
Do search). The precharge signal / PR becomes "1" level, and each priority encoder 5a
Each node of carry line 8 of .about.5d is precharged to "1" level (power supply potential VCC). After that, the control signal PRHL becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on, and the MOS transistor M1 is turned off.

Further, the operated input signals D8 and D2 are "0".
Level, and other operated input signals D15 to D7,
Assume that D6 to D3 and D1 are at "1" level. At this time, as shown in Table 1, the priority encoder 5
The calculated input signal of a (when m = 15) is D15 =
"1", D14 = "1", D13 = "1", D12 =
Since it is "1", its output signal Ea is Q1 =
"0", Q0 = "0", flag output signal / Fa
Is a "1" level (miss hit x).

The operation input signal (when m = 11) of the priority encoder 5b is D11 = "1", D10.
= “1”, D9 = “1”, D8 = “0”, the output signal Eb becomes Q1 = “0”, Q0 = “0”, and the flag output signal / Fb becomes “0” level. (Hit O).

The operation input signal (when m = 7) of the priority encoder 5c is D7 = "1", D6 =
Since "1", D5 = "1", and D4 = "1", the output signal Ec becomes Q1 = "0", Q0 = "0",
The flag output signal / Fc becomes "1" level (miss hit x).

The operation input signal (when m = 3) of the priority encoder 5d is D3 = "1", D2 =
Since “0”, D1 = “1” and D0 = “1”, the output signal Ed is Q1 = “1”, Q0 = “0”,
The flag output signal / Fd becomes the "0" level (hit O).

The input signals of the priority encoder 5e are / Fa = "1" (miss hit x) and / Fb = "0" from the upper bit to the lower bit, respectively.
(Hit O), / Fc = "1" (miss hit x), / F
d = “0” (hit O).

Therefore, as shown in Table 2, the output signal (encode value) Ee of the priority encoder 5e is
X1 = “1” and X0 = “0”. As shown in Table 3, the selector 6 outputs this output signal (encode value) Ee.
Upon receiving (X1 = "1", X0 = "0"), the output signal Eb of the priority encoder 5b is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The output signal Ee of e is set to the upper bit side, and the output signal E ′ of the selector 6 is set to the lower bit side, and both output signals are connected. That is, the coupler 7 outputs "1", "0", "0", "0" as the 4-bit output signal EOUT.

This 4-bit output signal EOUT is "8" when expressed in decimal, and it is understood that the "0" level that appears first when searching from the upper bit side is the bit D8. That is, it is confirmed that the bit D8 is at "0" level.

Next, consider the lower bit priority mode (forward search). Precharge signal / PR is "1"
It becomes a level, and each priority encoder 5a-5d
Each node of the carry line 8 is precharged to the "1" level (power supply potential VCC). After this, the control signal P
RLH goes to "1" level, control signal PRHL goes to "0" level, MOS transistor M1 turns on, and MOS transistor M1 turns on.
The transistor M2 is turned off.

The operated input signals D8 and D2 are "0".
Level, and other operated input signals D15 to D7,
Assume that D6 to D3 and D1 are at "1" level. At this time, as shown in Table 1, the priority encoder 5
The calculated input signal of a (when m = 15) is D15 =
"1", D14 = "1", D13 = "1", D12 =
Since it is "1", its output signal Ea is Q1 =
"0", Q0 = "0", flag output signal / Fa
Is a "1" level (miss hit x).

The operation input signal (when m = 11) of the priority encoder 5b is D11 = "1", D10.
= “1”, D9 = “1”, D8 = “0”, the output signal Eb becomes Q1 = “0”, Q0 = “0”, and the flag output signal / Fb becomes “0” level. (Hit O).

The operated input signal of the priority encoder 5c (when m = 7) is D7 = "1", D6 =
Since "1", D5 = "1", and D4 = "1", the output signal Ec becomes Q1 = "0", Q0 = "0",
The flag output signal / Fc becomes "1" level (miss hit x).

The operated input signal (when m = 3) of the priority encoder 5d is D3 = "1", D2 =
Since “0”, D1 = “1” and D0 = “1”, the output signal Ed is Q1 = “1”, Q0 = “0”,
The flag output signal / Fd becomes the "0" level (hit O).

Further, the input signals of the priority encoder 5e are / Fa = "1" (miss hit x) and / Fb = "0" from the upper bit to the lower bit, respectively.
(Hit O), / Fc = "1" (miss hit x), / F
d = “0” (hit O).

Therefore, as shown in Table 2, the output signal (encode value) Ee of the priority encoder 5e is
X1 = “0” and X0 = “0”. As shown in Table 3, the selector 6 outputs this output signal (encode value) Ee.
In response to (X1 = "0", X0 = "0"), the output signal Ed of the priority encoder 5d is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The output signal Ee of e is set to the upper bit side, and the output signal E ′ of the selector 6 is set to the lower bit side, and both output signals are connected. That is, the coupler 7 outputs "0", "0", "1", "0" as the 4-bit output signal EOUT.

The 4-bit output signal EOUT is "2" when expressed in decimal, and it can be seen that the "0" level that appears first when searching from the lower bit side is the bit D2. That is, it is confirmed that the bit D2 is at "0" level.

According to the bit search circuit having the above configuration, 1
The 6-bit processed input signal is divided into 4 blocks in units of 4 bits, and the first "0" level bit search is performed for each block. After that, the second search is performed as to which one of the four blocks contains the "0" level bit.

In this way, the "0" level bit
By dividing the channel into two stages, the discharge time of each priority encoder can be shortened to a maximum of 1/4 as compared with the discharge time of the conventional 16-bit priority encoder. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal to be operated increases.

Further, in the conventional priority encoder, the discharge time greatly varies depending on the position of the bit of "0" level, but in the bit search circuit of the present invention, the bit search circuit of 16 bits is used. Since the input signal to be operated is divided into four blocks in units of 4 bits, variations in the discharge time can be made smaller than in the conventional case. [B] FIG. 4 shows a 16-bit bit search circuit according to the second embodiment of the present invention.

This bit search circuit is composed of three priority encoders 5a, 5b and 5e, a selector 6 and a coupler 7. The priority encoder 5a is supplied with 8-bit consecutive input signals D15 to D8 on the upper side. The priority encoder 5a encodes which bit of the operated input signals D15 to D8 is at "0" level,
The result is output as a 3-bit output signal Ea. The priority encoder 5a also outputs a 1-bit flag output signal / Fa indicating whether or not the operated input signals D15 to D8 include "0" level bits.

That is, if at least one bit of the operated input signals D15 to D8 is at "0" level, the flag output signal / Fa is at "0" level. If all bits of the input signals D15 to D8 are "1" level, the flag output signal / Fa becomes "1" level.

The priority encoder 5b is supplied with consecutive 8-bit operated input signals D7 to D0 on the lower side. The priority encoder 5b encodes which bit of the operated input signals D7 to D0 is at the "0" level, and outputs the result as a 3-bit output signal Eb. Further, the priority encoder 5b is provided with operated input signals D7 to D0.
1 indicating whether or not a bit of "0" level is included in
The bit flag output signal / Fb is also output.

That is, if at least one bit of the operated input signals D7 to D0 is at "0" level, the flag output signal / Fc is at "0" level. If all the bits of the input signals D7 to D0 are "1" level, the flag output signal / Fc becomes "1" level.

The priority encoder 5e has a flag output signal / F from the priority encoders 5a and 5b.
a and / Fb are input respectively. The priority encoder 5e encodes which bit of the input signals / Fa and / Fb is at "0" level, and outputs the result as a 1-bit output signal Ee.

The selector 6 has a priority encoder.
The output signals Ea and Eb of the das 5a and 5b are input.
The selector 6 receives the priority encoder 5e based on the 1-bit output signal Ee of the priority encoder 5e.
One of the output signals Ea and Eb of the das 5a and 5b is selected and output.

The 1-bit output signal Ee of the priority encoder 5e and the 3-bit output signal E'of the selector 6 are input to the coupler 7. The coupler 7 connects the both output signals to each other with the output signal Ee on the upper side and the output signal E ′ on the lower side, and outputs the 4-bit output signal EOUT.

FIG. 5 shows the configuration of the priority encoders 5a and 5b shown in FIG. Since each priority encoder has the same configuration, the configuration will be described using the priority encoder 5a as an example.

The priority encoder 5a is composed of eight selectors 10-7, 10-0 and an encoder stage 11. The operated input signal D15 is input to the selector 10-7, and the selector 10-6 has
The operated input signal D14 is input, and the operated input signal D13 is input to the selector 10-5. Similarly, the selectors 10-4 and 10-0 are connected to the operated input signal D1.
2, to D8 are input.

Each selector has the same structure. Therefore, the selector 10-7 will be described. The selector 10-7 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source and drain of the MOS transistor N3 are connected to the carry line 8, and the gate of the MOS transistor N3 receives the operated input signal D15. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the NOR circuit 15 has an input signal D15 to be operated.
And the output signal of the AND circuit 14 is input, and the output signal is input to the encoder stage 11.

The encoder stage 11 is the selector 10
Receiving the output signals of -7 and -10-0, it outputs a 3-bit output signal Ea indicating which bit of the input signals D15 to D8 is at the "0" level, and outputs the input signal A 1-bit flag output signal / Fa indicating whether or not a bit of "0" level is included in D15 to D8 is output.

An N-channel MOS transistor M1 for discharge is connected to the lower bit side end of the carry line 8. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is on.
The MOS transistor M2 is turned off.

In the upper bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

Each node has a corresponding input signal D15, ... D.
In accordance with the level of 8, the level is discharged to "0" level (ground potential). FIG. 6 shows the configuration of the priority encoder 5e shown in FIG.

The priority encoder 5e has two selectors 10-1, 10-0 and an encoder stage 1.
1 is comprised. The output signal / Fa of the priority encoder 5a is input to the selector 10-1,
The priority encoder 5b is provided in the selector 10-0.
Output signal / Fb is input.

Each selector has the same structure. Therefore, the selector 10-1 will be described. The selector 10-1 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source / drain of the MOS transistor N3 is connected to the carry line 8 and the gate of the MOS transistor N3 receives the operated input signal D15. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the output signal / Fa of the priority encoder 10-3 and the output signal of the AND circuit 14 are input to the NOR circuit 15, and the output signal is input to the encoder stage 11.

The encoder stage 11 is the selector 10
Upon receiving the output signals of -1, 10-0, a 1-bit output signal Ee indicating which bit of the output signals / Fa, / Fb of the two priority encoders is at the "0" level is output. .

An N-channel MOS transistor M1 for discharge is connected to the lower bit side end of the carry line 8. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level).
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state.
The MOS transistor M1 is turned off.

Each node has a corresponding input signal D15, ... D.
In accordance with the level of 8, the level is discharged to "0" level (ground potential). Next, the operation of the bit search circuit shown in FIGS. 4 to 6 will be described. Table 4 shows the priority encoders 5a and 5b in the higher bit priority designation mode.
It shows the operation of.

[0117]

[Table 4] Table 5 shows the operation of the priority encoder 5e.

[0118]

[Table 5] Table 6 shows the operation of the selector 6.

[0119]

[Table 6] Table 7 shows the operation of the priority encoders 5a and 5b in the lower bit priority designation mode.

[0120]

[Table 7]

First, the upper bit priority mode (backward mode)
Do search). The precharge signal / PR becomes "1" level, and each priority encoder 5
The nodes of the carry lines 8 of a and 5b are precharged to the "1" level (power supply potential VCC). After that, the control signal PRHL becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on, and the MOS transistor M1 is turned off.

The operated input signals D8 and D2 are "0".
Level, and other operated input signals D15 to D7,
Assume that D6 to D3 and D1 are at "1" level. At this time, as shown in Table 4, the priority encoder 5
The calculated input signal of a (when m = 15) is D15 to D
Since 9 = “1” and D8 = “0”, its output signal E
a becomes Q2 = "0", Q1 = "0", Q0 = "0", and the flag output signal / Fa becomes "0" level (hit O).

The operated input signals (when m = 7) of the priority encoder 5b are D7 to D3 = "1", D2.
= “0” and D1 to D0 = “1”, the output signal Eb is Q2 = “0”, Q1 = “1”, Q0 = “0”.
Therefore, the flag output signal / Fc becomes "0" level (hit O).

Further, the input signals of the priority encoder 5e are / Fa = "0" (hit O) and / Fb = "0" (hit O) from the upper bit to the lower bit, respectively.

Therefore, as shown in Table 5, the output signal (encode value) Ee of the priority encoder 5e is
X0 = “1”. As shown in Table 6, the selector 6 outputs the output signal (encode value) Ee (X0 =
In response to "1"), the output signal Ea of the priority encoder 5a is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The 1-bit output signal Ee of e is set to the high-order bit side, and the 3-bit output signal E ′ of the selector 6 is set to the low-order bit side, and both output signals are connected. That is, the coupler 7
Is "1" as the 4-bit output signal EOUT,
Outputs "0", "0", "0".

This 4-bit output signal EOUT is "8" when expressed in decimal, and it can be seen that the "0" level that appears first when searching from the upper bit side is the bit D8. That is, it is confirmed that the bit D8 is at "0" level.

Next, consider the lower bit priority mode (forward search). Precharge signal / PR is "1"
It becomes a level and each priority encoder 5a, 5b
Each node of the carry line 8 is precharged to the "1" level (power supply potential VCC). After this, the control signal P
RLH goes to "1" level, control signal PRHL goes to "0" level, MOS transistor M1 turns on, and MOS transistor M1 turns on.
The transistor M2 is turned off.

The operated input signals D8 and D2 are "0".
Level, and other operated input signals D15 to D7,
Assume that D6 to D3 and D1 are at "1" level. At this time, as shown in Table 7, priority encoder 5
The calculated input signal of a (when m = 15) is D15 to D
9 "1" and D8 = "0", the output signal Ea
Becomes Q2 = "0", Q1 = "0", Q0 = "0", and the flag output signal / Fa becomes "0" level (hit O).

The operation input signals (when m = 7) of the priority encoder 5b are D7 to D3 = "1", D2.
= “0” and D1 to D0 = “1”, the output signal Eb is Q2 = “0”, Q1 = “1”, Q0 = “0”.
Therefore, the flag output signal / Fb becomes "0" level (hit O).

Further, the input signals of the priority encoder 5e are / Fa = "0" (hit O) and / Fb = "0" (hit O) from the upper bit to the lower bit, respectively.

Therefore, as shown in Table 5, the output signal (encode value) Ee of the priority encoder 5e is
X0 = “0”. As shown in Table 6, the selector 6 outputs the output signal (encode value) Ee (X0 =
Upon receiving "0"), the output signal Eb of the priority encoder 5b is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The output signal Ee of e is set to the upper bit side, and the output signal E ′ of the selector 6 is set to the lower bit side, and both output signals are connected. That is, the coupler 7 outputs "0", "0", "1", "0" as the 4-bit output signal EOUT.

The 4-bit output signal EOUT is "2" when expressed in decimal, and it can be seen that the "0" level that appears first when searching from the lower bit side is the bit D2. That is, it is confirmed that the bit D2 is at "0" level.

According to the bit search circuit having the above configuration, 1
The 6-bit operated input signal is divided into two blocks in 8-bit units, and the first "0" level bit search is performed for each block. After that, the second search is performed as to which one of the two blocks contains the "0" level bit.

In this way, the "0" level bit
By dividing the channel into two stages, the discharge time of each priority encoder can be reduced to a maximum of 1/2 as compared with the discharge time of the conventional 16-bit priority encoder. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal to be operated increases.

Further, in the conventional priority encoder, the discharge time greatly varies depending on the position of the bit of "0" level, but in the bit search circuit of the present invention, 16 bits are used. Since the input signal to be operated is divided into two blocks in units of 8 bits, variations in the discharge time can be made smaller than in the conventional case. [C] FIG. 7 shows a 16-bit bit search circuit according to the third embodiment of the present invention.

This bit search circuit comprises nine priority encoders 5a-5i, a selector 6 and a coupler 7.
It consists of The priority encoder 5a has a continuous 2-bit operand input signal D1 on the upper side.
5 and D14 are input. Priority Enco-
The decoder 5a encodes which bit of the operated input signals D15 and D14 is at "0" level,
The result is output as a 1-bit output signal Ea. The priority encoder 5a also outputs a 1-bit flag output signal / Fa indicating whether or not the operated input signals D15 and D14 include "0" level bits.

That is, if at least one bit of the input signals D15 and D14 is "0" level, the flag output signal / Fa becomes "0" level. If both bits of the input signals D15 and D14 are "1" level, the flag output signal / Fa becomes "1" level.

The priority encoder 5b has two consecutive 2-bit operand input signals D13 and D12 on the upper side.
Has been entered. The priority encoder 5b is
Which bit of the operated input signals D13 and D12 is at "0" level is encoded, and the result is output as a 1-bit output signal Eb. Further, the priority encoder 5b is provided with the operated input signal D1.
Also, a 1-bit flag output signal / Fb indicating whether or not D12 includes a "0" level bit is output.

That is, if at least one bit of the operated input signals D13 and D12 is at "0" level, the flag output signal / Fb is at "0" level. If both bits of the input signals D13 and D12 are "1" level, the flag output signal / Fb is "1" level.

Similarly, the priority encoder 5c
Inputs 2-bit processed input signals D11 and D10 and outputs output signals Ec and / Fc. The priority encoder 5d is a 2-bit operated input signal D9, D.
8 is input and output signals Ed and / Fd are output. The priority encoder 5e inputs 2-bit operated input signals D7 and D6 and outputs output signals Ee and / Fe. The priority encoder 5f receives 2-bit operated input signals D5 and D4 and outputs output signals Ef and / Ff.
Is output. The priority encoder 5g inputs the 2-bit operated input signals D3 and D2 and outputs the output signal E.
Output g, / Fg. Priority encoder 5h
Inputs 2-bit processed input signals D1 and D0 and outputs output signals Eh and / Fh.

Further, the flag output signals / Fa to / Fh of the priority encoders 5a to 5h are input to the priority encoder 5i, respectively. The priority encoder 5i encodes which bit of the input signals / Fa to / Fh is at "0" level, and outputs the result as a 3-bit output signal Ei.

The selector 6 has a priority encoder.
The output signals Ea to Eh of the das 5a to 5h are input.
The selector 6 receives the priority encoder on the basis of the 3-bit output signal Ei of the priority encoder 5i.
One of the output signals Ea to Eh of the das 5a to 5h is selected and output.

A 3-bit output signal Ei of the priority encoder 5i and a 1-bit output signal E'of the selector 6 are input to the coupler 7. The coupler 7 connects both output signals to each other with the output signal Ei on the upper side and the output signal E ′ on the lower side, and outputs the 4-bit output signal EOUT.

FIG. 8 shows the configuration of the priority encoders 5a to 5h shown in FIG. Since each priority encoder has the same configuration, the configuration will be described using the priority encoder 5a as an example.

The priority encoder 5a includes two selectors 10-1, 10-0 and an encoder stage 1.
1 is comprised. The operated input signal D15 is input to the selector 10-1, and the operated input signal D14 is input to the selector 10-0.

Each selector has the same structure. Therefore, the selector 10-1 will be described. The selector 10-1 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source and drain of the MOS transistor N3 are connected to the carry line 8, and the gate of the MOS transistor N3 receives the operated input signal D15. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the NOR circuit 15 has an input signal D15 to be operated.
And the output signal of the AND circuit 14 is input, and the output signal is input to the encoder stage 11.

The encoder stage 11 is the selector 10
Received output signals of -1, 10-0 and operated input signal D
A 1-bit output signal Ea indicating which bit of 15 and D14 is at "0" level is output, and whether or not the operated input signals D15 and D14 include a "0" level bit. A 1-bit flag output signal / Fa indicating that is output.

An N-channel MOS transistor M1 for discharge is connected to the end of the carry line 8 on the lower bit side. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

Each node has a corresponding input signal D15, ... D.
In accordance with the level of 8, the level is discharged to "0" level (ground potential). FIG. 9 shows the configuration of the priority encoder 5i shown in FIG.

The priority encoder 5i is composed of eight selectors 10-7, 10-0 and an encoder stage 11. An output signal / Fa of the priority encoder 5a is input to the selector 10-7, and an output signal / Fb of the priority encoder 5b is input to the selector 10-6. Similarly, the output signals / Fc to / Fh of the priority encoders 5c to 5h are input to the selectors 10-5 to 10-0.

Each selector has the same structure. Therefore, the selector 10-7 will be described. The selector 10-7 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source / drain of the MOS transistor N3 is connected to the carry line 8, and the gate of the MOS transistor N3 receives the operated input signal D15. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the output signal / Fa of the priority encoder 5a and the output signal of the AND circuit 14 are input to the NOR circuit 15, and the output signal thereof is the encoder stage 11
Is input to

The encoder stage 11 is the selector 10
Receiving the output signals of -7 and -10-0, it outputs a 3-bit output signal Ei indicating which bit of the output signals / Fa to / Fh of the eight priority encoders is the "0" level. To do.

An N-channel MOS transistor M1 for discharge is connected to the lower bit side end of the carry line 8. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, since the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

Each node has a flag output signal / Fa, 〜 /
According to the level of Fh, it is discharged to the "0" level (ground potential). Next, the operation of the bit search circuit of FIGS. 7 to 9 will be described. Table 8 shows the operations of the priority encoders 5a to 5h.

[0169]

[Table 8] Table 9 shows the operation of the priority encoder 5i.

[0170]

[Table 9] Table 10 shows the operation of the selector 6.

[0171]

[Table 10]

First, the higher bit priority mode (backward mode)
Do search). The precharge signal / PR becomes "1" level, and each priority encoder 5a
Each node of the carry line 8 for .about.5 h is precharged to "1" level (power supply potential VCC). After that, the control signal PRHL becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on, and the MOS transistor M1 is turned off.

The operated input signals D8 and D2 are "0".
Level, and other operated input signals D15 to D7,
Assume that D6 to D3 and D1 are at "1" level. At this time, as shown in Table 8, the priority encoder 5
The calculated input signal of a (when m = 15) is D15, D
Since 14 = “1”, the output signal Ea is Q0 =
It becomes "0", and the flag output signal / Fa becomes "1" level (miss hit x).

The operated input signal (when m = 13) of the priority encoder 5b is D13, D12 = "1".
Therefore, the output signal Eb becomes Q0 = “0”, and the flag output signal / Fb becomes “1” level (miss hit ×).

The operated input signal (when m = 11) of the priority encoder 5c is D11, D10 = "1".
Therefore, the output signal Ec becomes Q0 = "0", and the flag output signal / Fc becomes "1" level (miss hit x).

The operated input signal (when m = 9) of the priority encoder 5d is D9 = "1", D8 =
Since it is "0", the output signal Ed is Q0 = "0".
Therefore, the flag output signal / Fd becomes "0" level (hit O).

Since the operated input signal (when m = 7) of the priority encoder 5e is D7, D6 = "1", the output signal Ee becomes Q0 = "0", and the flag output signal / Fd becomes "1" level (miss hit x).

Since the operated input signal (when m = 5) of the priority encoder 5f is D5, D4 = "1", its output signal Ef becomes Q0 = "0" and the flag output signal / Ff becomes "1" level (miss hit x).

The operated input signal (when m = 3) of the priority encoder 5g is D3 = "1", D2 =
Since it is "0", its output signal Eg is Q0 = "0".
Therefore, the flag output signal / Fg becomes "0" level (hit O).

Since the operation input signal (when m = 1) of the priority encoder 5h is D1 and D0 = "1", its output signal Ef becomes Q0 = "0", and the flag output signal / Fh becomes "1" level (miss hit x).

Therefore, as shown in Table 9, the flag signal input to the priority encoder 5i is / Fa =
"1", / Fb = "1", / Fc = "1", / Fd =
"0", / Fe = "1", / Ff = "1", / Fg =
"0" and / Fh = "1", and the output signal (encode value) Ei is X2 = "1", X1 = "0", X0 =
It becomes "0".

As shown in Table 10, the selector 6 outputs this output signal (encode value) Ei (X2 = "1", X1 =
In response to "0", X0 = "0"), the output signal Ed of the priority encoder 5d is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The 3-bit output signal Ei of i is set to the high-order bit side, and the 1-bit output signal E ′ of the selector 6 is set to the low-order bit side, and both output signals are connected. That is, the coupler 7
Is "1" as the 4-bit output signal EOUT,
Outputs "0", "0", "0".

This 4-bit output signal EOUT is "8" when expressed in decimal, and it is understood that the "0" level that appears first when searching from the upper bit side is the bit D8. That is, it is confirmed that the bit D8 is at "0" level.

Next, consider the lower bit priority mode (forward search). Precharge signal / PR is "1"
Level, each priority encoder 5a-5h
Each node of the carry line 8 is precharged to the "1" level (power supply potential VCC). After this, the control signal P
RLH goes to "1" level, control signal PRHL goes to "0" level, MOS transistor M1 turns on, and MOS transistor M1 turns on.
The transistor M2 is turned off.

The input signals D8 and D2 to be operated are "0".
Level, and other operated input signals D15 to D7,
Assume that D6 to D3 and D1 are at "1" level. At this time, as shown in Table 8, the priority encoder 5
The calculated input signal of a (when m = 15) is D15, D
Since 14 = “1”, the output signal Ea is Q0 =
It becomes "0", and the flag output signal / Fa becomes "1" level (miss hit x).

The operated input signal (when m = 13) of the priority encoder 5b is D13, D12 = "1".
Therefore, the output signal Eb becomes Q0 = “0”, and the flag output signal / Fb becomes “1” level (miss hit ×).

The operated input signal (when m = 11) of the priority encoder 5c is D11, D10 = "1".
Therefore, the output signal Ec becomes Q0 = "0", and the flag output signal / Fc becomes "1" level (miss hit x).

The operated input signal (when m = 9) of the priority encoder 5d is D9 = "1", D8 =
Since it is "0", the output signal Ed is Q0 = "0".
Therefore, the flag output signal / Fd becomes "0" level (hit O).

Since the operated input signal (when m = 7) of the priority encoder 5e is D7, D6 = "1", its output signal Ee becomes Q0 = "0" and the flag output signal / Fd becomes "1" level (miss hit x).

Since the operation input signal (when m = 5) of the priority encoder 5f is D5, D4 = "1", its output signal Ef becomes Q0 = "0" and the flag output signal / Ff becomes "1" level (miss hit x).

The operated input signal (when m = 3) of the priority encoder 5g is D3 = "1", D2 =
Since it is "0", its output signal Eg is Q0 = "0".
Therefore, the flag output signal / Fg becomes "0" level (hit O).

Since the operated input signal (when m = 1) of the priority encoder 5h is D1 and D0 = "1", its output signal Ef becomes Q0 = "0" and the flag output signal / Fh becomes "1" level (miss hit x).

Therefore, as shown in Table 9, the flag signal input to the priority encoder 5i is / Fa =
"1", / Fb = "1", / Fc = "1", / Fd =
"0", / Fe = "1", / Ff = "1", / Fg =
"0" and / Fh = "1", and the output signal (encode value) Ei is X2 = "0", X1 = "0", X0 =
It becomes “1”.

As shown in Table 10, the selector 6 outputs this output signal (encode value) Ei (X2 = "0", X1 =
In response to "0", X0 = "1"), the output signal Eg of the priority encoder 5g is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The 3-bit output signal Ei of i is set to the high-order bit side, and the 1-bit output signal E ′ of the selector 6 is set to the low-order bit side, and both output signals are connected. That is, the coupler 7
Is "0" as a 4-bit output signal EOUT,
It outputs "0", "1", and "0".

The 4-bit output signal EOUT is "2" when expressed in decimal, and it is understood that when the search is performed from the lower bit side, the first "0" level is the bit D2. That is, it is confirmed that the bit D2 is at "0" level.

According to the bit search circuit having the above configuration, 1
The 6-bit operated input signal is divided into 8 blocks in units of 2 bits, and the first "0" level bit search is performed for each block. After that, the second search is performed as to which one of the two blocks contains the "0" level bit.

As described above, the "0" level bit
By dividing the channel into two stages, the discharge time of each priority encoder can be shortened to a maximum of 1/8 of the discharge time of the conventional 16-bit priority encoder. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal to be operated increases.

Further, in the conventional priority encoder, the discharge time greatly varies depending on the position of the bit of "0" level, but in the bit search circuit of the present invention, 16 bits are used. Since the input signal to be operated is divided into 8 blocks in units of 2 bits, variations in the discharge time can be made smaller than in the conventional case.

[0201]

As described above, according to the bit search circuit of the present invention, the following effects can be obtained. An input signal of i (eg, i = 16) bits is 2 ^j (j is 1, 2)
Alternatively, 3) bit units are divided into 2 ^k (k is 3, 2 or 1) blocks, and the first "0" level bit search is performed for each block. After this,
A second ^{search is performed as} to which of the 2 ^k blocks contains "0" level bits.

As described above, by dividing the method of searching the "0" level bit from the i-bit input signal into two stages, the discharge time of the priority encoder can be greatly shortened. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal increases. Also, i
Since the bit input signal is divided into 2 ^k blocks in units of 2 ^j bits, it is possible to reduce variations in the discharge time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a bit search circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing priority encoders 5a to 5d of FIG.

3 is a circuit diagram showing a priority encoder 5e of FIG.

FIG. 4 is a block diagram showing a bit search circuit according to a second embodiment of the present invention.

5 is a circuit diagram showing priority encoders 5a and 5b of FIG.

FIG. 6 is a circuit diagram showing a priority encoder 5e shown in FIG.

FIG. 7 is a block diagram showing a bit search circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing priority encoders 5a to 5h of FIG.

FIG. 9 is a circuit diagram showing the priority encoder 5i of FIG.

FIG. 10 is a block diagram showing a conventional priority encoder.

[Explanation of symbols]

1-15 to 1-0 ... precharge discharge section, 2, 8 ... carry line, 3-16 to 3-0, 9-3 ... node 4 ... bit select encoder circuit, 5a-5i ... Priority Enco-
DA, 6, 10-7 to 10-0 ... Selector, 7 ... Coupler, 11 ... Encoder stage, 12, 13 ... OR circuit, 14 ... AND circuit, 15 ... NOR circuit, N3, M1, M2 ... N-channel type MOS transistor, P3, P '... P-channel type MOS transistor.

[Procedure amendment]

[Submission date] August 15, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Detailed explanation of the invention

[Correction method] Change

[Correction content]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit search circuit used in a microcomputer.

[0002]

2. Description of the Related Art FIG. 10 shows a dynamic 16-bit priority encoder which constitutes a conventional bit search circuit.

/ D15 to / D0 are input signals to be operated . Calculated input signal / Dn (n = 15, 14, to 0)
Are precharge / discharge units 1-n, respectively.
(N = 15, 14, ~ 0).

Precharge / discharge unit 1-n
Is an N-channel MOS transistor Nn (n = 15,
14, to 0) and P-channel MOS transistor Pn
(N = 15, 14, to 0).

The source and drain of the MOS transistor Nn are connected to the carry line 2, and the gate of the MOS transistor Nn receives the operated input signal / Dn . Calculated input signal /
Dn serves as a control signal for switching the MOS transistor Nn. The source of the MOS transistor Pn is connected to the power supply VCC, and the gate is connected to the precharge signal / P.
R is entered.

The drain of the MOS transistor Pn is connected to the node 3-n (n = 15, 14, ... 0). The node 3-n is the source / drain of the MOS transistor Nn of the precharge / discharge unit 1-n and the MOS transistor N of the precharge / discharge unit 1- (n-1). It is a connection point with the source / drain of (n-1).

However, the node 3-0 (that is, n = 0) is the source / drain of the MOS transistor of the precharge / discharge unit 1-0 and the source / drain of the discharge MOS transistor M1. -This is the connection point with the drain.
Also, the MO of the precharge / discharge unit 1-15
A connection point between the source / drain of the S transistor and the source / drain of the discharge MOS transistor M2 is designated as a node 3-16.

On the upper bit ( / D15 ) side, the source of the P-channel MOS transistor P'is:
It is connected to the power supply VCC and the gate is supplied with the precharge signal / PR. The drain of the MOS transistor P'is connected to the node 3-16.

Discharge MOS transistor M1
Is connected between one end of the carry line 2 on the lower bit ( / D0 ) side and the ground point GND. The source / drain of the discharge MOS transistor M2 is the upper bit ( / of the carry line 2).
It is connected between one end on the D15 ) side and the ground point GND.

Each node 3-n (n = 16, to 0) has a MOS when the precharge signal / PR becomes "0" level.
Since the transistors Pn (n = 15 to 0) and P'are turned on, they are precharged to the "1" level (power supply potential VCC).

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is on.
The MOS transistor M2 is turned off.

In the high-order bit priority mode, the control signal PRHL becomes "1" level and the control signal PRLH becomes "0" level, so that the MOS transistor M2 is turned on.
The MOS transistor M1 is turned off.

Each node 3-n (n = 16, to 0) is discharged to "0" level (ground potential) according to the level of the input signal / Dn (n = 15, to 0). -It is

In the bit select / encoder circuit 4,
The calculated input signal / Dn and the potential of the node 3-n of each precharge / discharge unit 1-n are input. The bit select / encoder circuit 4 outputs 4-bit encode output signals Q3 to Q0.

Further , the priority encoder having the above structure is
The carrier line is constituted by pass transistors. Therefore, the ratio of the area of the priority encoder to the entire chip area can be made relatively small. However, as the number of bits of the input signal increases, it takes time to discharge each node of the carry line.

Next, the operation of the priority encoder of FIG. 10 will be described.

The priority encoder has a function of determining which bit of the input signal / Dn to be operated is the "0" level.

First, consider the lower bit priority mode.

The precharge signal / PR goes to "0" level, and each node 3-n (n = 16, to 0) is precharged to "1" level (power supply potential VCC). After this,
The control signal PRLH becomes "1" level, the control signal PRHL becomes "0" level, the MOS transistor M1 is turned on, and the MOS transistor M2 is turned off.

Then, each node 3-n is discharged in accordance with the level of the input signal / Dn to be operated. For example, when only the most significant bit ( / D15 ) is at the "0" level and the other bits ( / D14 to / D0 ) are at the "1" level, nodes 3-0 to 3-15. It is gradually discharged until.

Next, consider the upper bit priority mode.

The precharge signal / PR goes to "0" level and each node 3-n (n = 16, to 0) is precharged to "1" level (power supply potential VCC). After this,
The control signal PRHL becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on, and the MOS transistor M1 is turned off.

Then, each node 3-n is discharged according to the level of the input signal / Dn to be operated. For example, when only the least significant bit ( / D0 ) is at the "0" level and the other bits ( / D15 to / D1 ) are at the "1" level, the nodes 3-15 to 3-0. It is gradually discharged until.

As described above, in the case of the lower bit priority mode, only the bit on the most significant bit side is at "0" level, and in the case of the higher bit priority mode, the bit on the least significant bit side. In the case that only one is at "0" level, there is a drawback that the discharge time becomes long.

This drawback is that the number of bits of the input signal / Dn to be operated is 32 bits (n = 31, to 0) and 64 bits (n
= 63, to 0), it becomes remarkable and becomes a bottleneck for high-speed arithmetic processing.

[0026]

As described above, in the priority encoder that constitutes the conventional bit search circuit, the discharge time becomes longer as the number of bits of the input signal to be operated increases, and this number of bits becomes larger. There is a drawback that the increase in the number becomes a bottleneck in high-speed arithmetic processing.

The present invention has been made to solve the above drawbacks, and an object thereof is to provide a bit search circuit capable of operating at high speed in a small area even if the number of bits of an input signal to be operated increases. That is.

[0028]

In order to achieve the above object, the bit search circuit of the present invention is configured such that continuous 2 ^j (j is a natural number) bits of an i-bit input signal are input.
Outputs a flag signal indicating whether it contains a first level bits Some of the 2 ^j bits, and the 2 ^j
2 ^k (where i = 2 ^{j + k} ) number of j-bit first encoded signals for specifying the first level bit when the bit includes the first level bit Of the first encoder and the flag signals of the respective first encoders are input, and the k-bit first encoder for specifying the first encoder including the bit of the first level based on the flag signal is input. A second encoder for outputting a two-encoder signal and a second encoder signal for the second encoder are input, and a first encoder for the first encoder specified by the second encoder signal is input. A selector for selecting and outputting one encode signal,
The second and first encoding signals of the second encoder are on the upper bit side, and the first and first encoding signals of the specified first encoder are on the lower bit side, and the first and second
And a concatenator for concatenating the encode signals and outputting a j + k-bit third encode signal for specifying a first level bit included in the i-bit input signal.

The first and second encoders have a function of selecting and designating an upper bit priority mode and a lower bit priority mode. In the upper bit priority mode, the i bit is selected. Of the i-bit input signals, the first level bit of the most significant bit side of the input signals is specified, and the least significant bit of the i-bit input signal is the least significant bit side of the i-bit input signal. Identify one level of bits.

[0030]

According to the above configuration, an i-bit input signal is converted into 2 ^j
Each block is divided into 2 ^k blocks (first encoder) (that is, i = 2 ^{j + k} ) and the first search of the first level bit is performed for each block. After that, the second search is performed by the second encoder to determine in which of the 2 ^k blocks the bit of the first level exists.

In this way, the first signal from the i-bit input signal
By dividing the level bit search method into two stages, the discharge time of the first and second encoders can be greatly shortened. That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits (i) of the input signal increases.

Further, since the i-bit input signal is divided into 2 ^k blocks in units of 2 ^j bits, variations in discharge time can be reduced.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The bit search circuit of the present invention will be described in detail below with reference to the drawings.

[A] FIG. 1 shows a 16-bit bit search circuit according to the first embodiment of the present invention.

This bit search circuit includes five priority encoders 5a-5e, a selector 6 and a coupler 7.
It consists of

The priority encoder 5a has a continuous 4-bit operand input signal / D15 to / D on the upper side.
12 has been entered. Priority encoder 5a
Encodes which bit of the operated input signals / D15 to / D12 is at "0" level, and outputs the result as a 2-bit output signal Ea. The priority encoder 5a has a 1-bit flag output signal / Fa indicating whether or not the operated input signals / D15 to / D12 include a "0" level bit.
Will also be output.

That is, the operated input signals / D15 to / D12
If at least one bit of these is "0" level,
The flag output signal / Fa becomes "0" level. Also,
If all the bits of the input signals / D15 to / D12 to be operated are "1" level, the flag output signal / Fa is
It becomes "1" level.

The priority encoder 5b has a continuous 4-bit operand input signal / D11 to / D on the upper side.
8 has been entered. Priority encoder 5b
Encodes which bit of the operated input signals / D11 to / D8 is at the "0" level, and outputs the result as a 2-bit output signal Eb. Also,
This priority encoder 5b is used for the input signal to be operated.
It also outputs a 1-bit flag output signal / Fb indicating whether or not / D11 to / D8 include a "0" level bit.

That is, if at least one bit of the operated input signals / D11 to / D8 is at "0" level, the flag output signal / Fb is at "0" level. In addition, all bits of the operated input signals / D11 to / D8 are "1".
If it is at the level, the flag output signal / Fb becomes the "1" level.

The priority encoder 5c has a continuous lower 4-bit operated input signal / D7 to / D4.
Has been entered. The priority encoder 5c is
It is encoded which bit of the operated input signals / D7 to / D4 is at "0" level, and the result is output as a 2-bit output signal Ec. In addition, the priority encoder 5c is provided with a processed input signal / D7.
It also outputs a 1-bit flag output signal / Fc indicating whether or not ~ 0 / D4 includes a "0" level bit.

That is, if at least one bit of the operated input signals / D7 to / D4 is at "0" level, the flag output signal / Fc becomes "0" level. If all the bits of the input signals / D7 to / D4 to be operated are "1" level, the flag output signal / Fc becomes "1" level.

The priority encoder 5d has a continuous lower 4-bit operated input signal / D3 to / D0.
Has been entered. The priority encoder 5d is
It is encoded which bit of the operated input signals / D3 to / D0 is at the "0" level, and the result is output as a 2-bit output signal Ed. Further, the priority encoder 5d is provided with a processed input signal / D3.
It also outputs a 1-bit flag output signal / Fd indicating whether or not the bits of " / D0 " include "0" level.

That is, if at least one bit of the operated input signals / D3 to / D0 is "0" level, the flag output signal / Fd is "0" level. If all bits of the input signals / D3 to / D0 to be operated are at "1" level, the flag output signal / Fd will be at "1" level.

The priority encoder 5e has a flag output signal / F for the priority encoders 5a to 5d.
a to / Fd are input respectively. The priority encoder 5e encodes which bit of the input signals / Fa to / Fd is at the "0" level, and outputs the result as a 2-bit output signal Ee.

The selector 6 has a priority encoder.
The output signals Ea to Ed of the das 5a to 5d are input.
The selector 6 receives the priority encoder based on the 2-bit output signal Ee of the priority encoder 5e.
One of the output signals Ea to Ed of the das 5a to 5d is selected and output.

The 2-bit output signal Ee of the priority encoder 5e and the 2-bit output signal E'of the selector 6 are input to the coupler 7. The coupler 7 connects the both output signals to each other with the output signal Ee on the upper side and the output signal E ′ on the lower side, and outputs the 4-bit output signal EOUT.

FIG. 2 shows the configuration of the priority encoders 5a to 5d shown in FIG. Since each priority encoder has the same configuration, the configuration will be described using the priority encoder 5a as an example.

The priority encoder 5a is composed of four selectors 10-3, 10-0 and an encoder stage 11.

The selector 10-3 supplies the calculated input signal /
D15 is input, the operated input signal / D14 is input to the selector 10-2, the operated input signal / D13 is input to the selector 10-1, and the operated input signal is input to the selector 10-0. / D12 has been input.

Each selector has the same structure. Therefore, the selector 10-3 will be described. The selector 10-3 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source / drain of the MOS transistor N3 is connected to the carry line 8, and the gate of the MOS transistor N3 receives the operated input signal / D15 . The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. In addition, the NOR circuit 15 includes an input signal / D1 to be operated.
5 and the output signal of the AND circuit 14 are input, and the output signal thereof is input to the encoder stage 11.

The encoder stage 11 is a selector 10
Received output signals of -3 to 10-0, input signal to be operated
A 2-bit output signal Ea indicating which bit of / D15 to / D12 is at "0" level is output, and "0" is included in the operated input signals / D15 to / D12.
A 1-bit flag output signal / Fa indicating whether or not a level bit is included is output.

An N-channel MOS transistor M1 for discharge is connected to the end of the carry line 8 on the lower bit side. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level).
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is on.
The MOS transistor M2 is turned off.

In the high-order bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

The respective nodes are operated input signals / D15 to //.
According to the level of D12 , it is discharged to the "0" level (ground potential).

FIG. 3 shows the configuration of the priority encoder 5e shown in FIG.

The priority encoder 5e is composed of four selectors 10-3, 10-0 and an encoder stage 11.

The output signal / Fa of the priority encoder 5a is input to the selector 10-3, and the selector 1
The output signal / Fb of the priority encoder 5b is input to 0-2, the output signal / Fc of the priority encoder 5c is input to the selector 10-1, and the priority encoder 5c is input to the selector 10-0. The output signal / Fd of the terminal 5d is input.

Each selector has the same structure. Therefore, the selector 10-3 will be described. The selector 10-3 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source and drain of the MOS transistor N3 are connected to the carry line 8, and the gate of the operated input signal / D15 is input. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the output signal / Fa of the priority encoder 10-3 and the output signal of the AND circuit 14 are input to the NOR circuit 15, and the output signal is input to the encoder stage 11.

The encoder stage 11 is a selector 10
In response to the output signals of -3 and 10-0, a 2-bit output signal Ee indicating which bit of the output signals / Fa to / Fd of the four priority encoders is the "0" level is output. To do.

An N-channel MOS transistor M1 for discharge is connected to the end of the carry line 8 on the lower bit side. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is at "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the high-order bit priority mode, the control signal PRHL becomes "1" level and the control signal PRLH becomes "0" level, so that the MOS transistor M2 is turned on.
The MOS transistor M1 is turned off.

The respective nodes are operated input signals / Fa to / F.
According to the level of d , it is discharged to "0" level (ground potential).

Next, the operation of the bit search circuit of FIGS. 1 to 3 will be described.

Table 1 shows priority encoders 5a to 5a.
5d shows the operation of 5d.

[0075]

[Table 1] Table 2 shows the operation of the priority encoder 5e.

[0076]

[Table 2] Table 3 shows the operation of the selector 6.

[0077]

[Table 3] First, upper bit priority mode (backward search)
think of.

The precharge signal / PR becomes "0" level, and each node of the carry lines 8 of the priority encoders 5a to 5d becomes "1" level (power supply potential VC).
C) is precharged. After this, the control signal PRHL
Becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on and the MOS transistor M1 is turned off.

Further, the operated input signals / D8 , / D2 are at "0" level, and the other operated input signals D15 to
It is assumed that D7 , D6 to D3 , D1 and D0 are at "1" level.

At this time, as shown in Table 1, the operated input signal of the priority encoder 5a (when m = 15)
/ D15 = “1”, / D14 = “1”, / D13 =
Since "1", / D12 = "1", its output signal E
a becomes Q1 = "0" and Q0 = "0", and the flag output signal / Fa becomes "1" level (miss hit x).

The operation input signal (when m = 11) of the priority encoder 5b is: / D11 = "1", / D
Since 10 = “1”, / D9 = “1”, / D8 = “0”, the output signal Eb is Q1 = “0”, Q0 =
It becomes "0", and the flag output signal / Fb becomes "0" level (hit O).

The operation input signals (when m = 7) of the priority encoder 5c are: / D7 = "1", / D6 =
Since "1", / D5 = "1", and / D4 = "1",
The output signal Ec becomes Q1 = "0" and Q0 = "0", and the flag output signal / Fc becomes "1" level (miss hit x).

The operation input signals (when m = 3) of the priority encoder 5d are: / D3 = “1”, / D2 =
Since "0", / D1 = "1", and / D0 = "1",
The output signal Ed becomes Q1 = "1", Q0 = "0", and the flag output signal / Fd becomes "0" level (hit O).

Further, the input signals of the priority encoder 5e are / Fa = "1" (miss hit x) and / Fb = "0" from the upper bit to the lower bit, respectively.
(Hit O), / Fc = "1" (miss hit x), / F
d = “0” (hit O).

Therefore, as shown in Table 2, the output signal (encode value) Ee of the priority encoder 5e is
X1 = “1” and X0 = “0”.

As shown in Table 3, the selector 6 outputs this output signal (encode value) Ee (X1 = "1", X0 =
Upon receiving "0"), the output signal Eb of the priority encoder 5b is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The output signal Ee of e is set to the upper bit side, and the output signal E ′ of the selector 6 is set to the lower bit side, and both output signals are connected. That is, the coupler 7 outputs "1", "0", "0", "0" as the 4-bit output signal EOUT.

This 4-bit output signal EOUT is "8" when expressed in decimal, and it is understood that the "0" level that appears first when searching from the upper bit side is bit / D8. . That is, it is confirmed that the bit / D8 is at "0" level.

Next, consider the lower bit priority mode (forward search).

The precharge signal / PR becomes "0" level, and each node of the carry lines 8 of the priority encoders 5a to 5d becomes "1" level (power supply potential VC).
C) is precharged. After this, the control signal PRLH
Becomes "1" level, the control signal PRHL becomes "0" level, the MOS transistor M1 is turned on, and the MOS transistor M2 is turned off.

Further, the operated input signals / D8 , / D2 are at "0" level, and the other operated input signals / D15.
~ / D7 , / D6 to / D3 , / D1, / D0 are assumed to be at "1" level.

At this time, as shown in Table 1, the operated input signal of the priority encoder 5a (when m = 15)
/ D15 = “1”, / D14 = “1”, / D13 =
Since "1", / D12 = "1", its output signal E
a becomes Q1 = "0" and Q0 = "0", and the flag output signal / Fa becomes "1" level (miss hit x).

The operation input signal of the priority encoder 5b (in the case of m = 11) is: / D11 = "1", / D
Since 10 = “1”, / D9 = “1”, / D8 = “0”, the output signal Eb is Q1 = “0”, Q0 =
It becomes "0", and the flag output signal / Fb becomes "0" level (hit O).

The operation input signals (when m = 7) of the priority encoder 5c are: / D7 = "1", / D6 =
Since "1", / D5 = "1", and / D4 = "1",
The output signal Ec becomes Q1 = "0" and Q0 = "0", and the flag output signal / Fc becomes "1" level (miss hit x).

The operated input signal (when m = 3) of the priority encoder 5d is: / D3 = "1", / D2 =
Since "0", / D1 = "1", and / D0 = "1",
The output signal Ed becomes Q1 = "1", Q0 = "0", and the flag output signal / Fd becomes "0" level (hit O).

The input signals of the priority encoder 5e are / Fa = "1" (misshit x) and / Fb = "0" from the upper bit to the lower bit, respectively.
(Hit O), / Fc = "1" (miss hit x), / F
d = “0” (hit O).

Therefore, as shown in Table 2, the output signal (encode value) Ee of the priority encoder 5e is
X1 = “0” and X0 = “0”.

As shown in Table 3, the selector 6 outputs the output signal (encode value) Ee (X1 = "0", X0 =
In response to "0", the output signal Ed of the priority encoder 5d is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The output signal Ee of e is set to the upper bit side, and the output signal E ′ of the selector 6 is set to the lower bit side, and both output signals are connected. That is, the coupler 7 outputs "0", "0", "1", "0" as the 4-bit output signal EOUT.

The 4-bit output signal EOUT is "2" when expressed in decimal, and when the search is performed from the lower bit side, it is understood that the first "0" level is the bit / D2. . That is, it is confirmed that the bit / D2 is at "0" level.

According to the bit search circuit having the above configuration, 1
The 6-bit processed input signal is divided into 4 blocks in units of 4 bits, and the first "0" level bit search is performed for each block. After that, the second search is performed as to which one of the four blocks contains the "0" level bit.

In this way, the "0" level bit server
By dividing the channel into two stages, the discharge time of each priority encoder can be shortened to a maximum of 1/4 as compared with the discharge time of the conventional 16-bit priority encoder. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal to be operated increases.

Further, in the conventional priority encoder, the discharge time greatly varies depending on the position of the bit of "0" level, but in the bit search circuit of the present invention, 16 bits are used. Since the input signal to be operated is divided into four blocks in units of 4 bits, variations in the discharge time can be made smaller than in the conventional case.

[B] FIG. 4 shows a 16-bit bit search circuit according to the second embodiment of the present invention.

This bit search circuit is composed of three priority encoders 5a, 5b and 5e, a selector 6 and a coupler 7.

The priority encoder 5a has a high-order continuous 8-bit operand input signal / D15 to / D.
8 has been entered. Priority encoder 5a
Encodes which bit of the operated input signals / D15 to / D8 is at "0" level and outputs the result as a 3-bit output signal Ea. Also,
This priority encoder 5a is used for the input signal to be operated.
It also outputs a 1-bit flag output signal / Fa indicating whether or not / D15 to / D8 include a "0" level bit.

That is, if at least one bit of the input signals / D15 to / D8 to be operated is at "0" level, the flag output signal / Fa is at "0" level. Also, all bits of the operated input signals / D15 to / D8 are "1".
If it is a level, the flag output signal / Fa becomes a "1" level.

The priority encoder 5b has a continuous lower 8-bit operated input signal / D7 to / D0.
Has been entered. The priority encoder 5b is
Which bit of the input signals / D7 to / D0 to be operated is at "0" level is encoded, and the result is output as a 3-bit output signal Eb. In addition, the priority encoder 5b is provided with a processed input signal / D7.
It also outputs a 1-bit flag output signal / Fb which indicates whether or not ~ / D0 includes a "0" level bit.

That is, if at least one bit of the operated input signals / D7 to / D0 is at "0" level, the flag output signal / Fc is at "0" level. If all the bits of the input signals / D7 to / D0 to be operated are at "1" level, the flag output signal / Fc will be at "1" level.

The priority encoder 5e has a flag output signal / F from the priority encoders 5a and 5b.
a and / Fb are input respectively. The priority encoder 5e encodes which bit of the input signals / Fa and / Fb is at "0" level, and outputs the result as a 1-bit output signal Ee.

The selector 6 has a priority encoder.
The output signals Ea and Eb of the das 5a and 5b are input.
The selector 6 receives the priority encoder 5e based on the 1-bit output signal Ee of the priority encoder 5e.
One of the output signals Ea and Eb of the das 5a and 5b is selected and output.

The 1-bit output signal Ee of the priority encoder 5e and the 3-bit output signal E'of the selector 6 are input to the coupler 7. The coupler 7 connects the both output signals to each other with the output signal Ee on the upper side and the output signal E ′ on the lower side, and outputs the 4-bit output signal EOUT.

FIG. 5 shows the configuration of the priority encoders 5a and 5b shown in FIG. Since each priority encoder has the same configuration, the configuration will be described using the priority encoder 5a as an example.

The priority encoder 5a is composed of eight selectors 10-7, 10-0 and an encoder stage 11.

The selector 10-7 supplies the calculated input signal /
D15 is input, the operated input signal / D14 is input to the selector 10-6, and the operated input signal / D13 is input to the selector 10-5. Similarly, selector 1
0-4 and -10-0 are the input signals / D12, ...
/ D8 is input.

Each selector has the same structure. Therefore, the selector 10-7 will be described. The selector 10-7 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source / drain of the MOS transistor N3 is connected to the carry line 8 and the gate of the operated input signal / D15 is inputted. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. In addition, the NOR circuit 15 includes an input signal / D1 to be operated.
5 and the output signal of the AND circuit 14 are input, and the output signal thereof is input to the encoder stage 11.

The encoder stage 11 is the selector 10
Received output signals of -7 and -10-0
A 3-bit output signal Ea indicating which bit of / D15 to / D8 is at the "0" level is output, and
A 1-bit flag output signal / Fa indicating whether or not a bit of "0" level is included in the operated input signals / D15 to / D8 is output.

An N-channel MOS transistor M1 for discharge is connected to the end of the carry line 8 on the lower bit side. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level).
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the high-order bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state.
The MOS transistor M1 is turned off.

Each node has an input signal / D15, ...
According to the level of / D8 , it is discharged to the "0" level (ground potential).

FIG. 6 shows the configuration of the priority encoder 5e shown in FIG.

The priority encoder 5e has two selectors 10-1, 10-0 and an encoder stage 1.
1 is comprised.

The output signal / Fa of the priority encoder 5a is input to the selector 10-1, and the selector 1
The output signal / Fb of the priority encoder 5b is input to 0-0.

Each selector has the same structure. Therefore, the selector 10-1 will be described. The selector 10-1 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source / drain of the MOS transistor N3 is connected to the carry line 8 and the gate of the operated input signal / D15 is input. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the output signal / Fa of the priority encoder 10-3 and the output signal of the AND circuit 14 are input to the NOR circuit 15, and the output signal is input to the encoder stage 11.

The encoder stage 11 is the selector 10
Upon receiving the output signals of -1, 10-0, a 1-bit output signal Ee indicating which bit of the output signals / Fa, / Fb of the two priority encoders is at the "0" level is output. .

An N-channel MOS transistor M1 for discharge is connected to the end of the carry line 8 on the lower bit side. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, since the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

The nodes are operated input signals / Fa, / F.
According to the level of b , it is discharged to the "0" level (ground potential).

Next, the operation of the bit search circuit of FIGS. 4 to 6 will be described.

Table 4 shows the operation of the priority encoders 5a and 5b in the higher bit priority designation mode.

[0141]

[Table 4] Table 5 shows the operation of the priority encoder 5e.

[0142]

[Table 5] Table 6 shows the operation of the selector 6.

[0143]

[Table 6] Table 7 shows the operation of the priority encoders 5a and 5b in the lower bit priority designation mode.

[0144]

[Table 7] First, upper bit priority mode (backward search)
think of.

The precharge signal / PR goes to "0" level, and each node of the carry lines 8 of the priority encoders 5a and 5b goes to "1" level (power supply potential VC).
C) is precharged. After this, the control signal PRHL
Becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on and the MOS transistor M1 is turned off.

The operated input signals / D8 , / D2 are at "0" level, and the other operated input signals / D15.
~ / D7 , / D6 to / D3 , / D1, / D0 are assumed to be at "1" level.

At this time, as shown in Table 4, the operated input signal of the priority encoder 5a (when m = 15)
Are / D15 to / D9 = "1" and / D8 = "0", the output signal Ea is Q2 = "0", Q1 =
"0", Q0 = "0", flag output signal / Fa
Becomes a “0” level (hit O).

The operated input signal (when m = 7) of the priority encoder 5b is: / D7 to / D3 = "1",
Since / D2 = “0” and / D1 to / D0 = “1”,
The output signal Eb has Q2 = "0", Q1 = "1", Q
0 = “0”, and the flag output signal / Fb becomes “0” level (hit O).

Further, the input signals of the priority encoder 5e are / Fa = "0" (hit O) and / Fb = "0" (hit O) from the upper bit to the lower bit, respectively.

Therefore, as shown in Table 5, the output signal (encode value) Ee of the priority encoder 5e is
X0 = “1”.

As shown in Table 6, the selector 6 receives the output signal (encode value) Ee (X0 = "1"), selects the output signal Ea of the priority encoder 5a, and outputs the output signal. Output as E '.

The connector 7 is a priority encoder 5
The 1-bit output signal Ee of e is set to the high-order bit side, and the 3-bit output signal E ′ of the selector 6 is set to the low-order bit side, and both output signals are connected. That is, the coupler 7
Is "1" as the 4-bit output signal EOUT,
Outputs "0", "0", "0".

This 4-bit output signal EOUT is "8" when expressed in decimal, and it is understood that the "0" level that appears first when searching from the upper bit side is bit / D8. . That is, it is confirmed that the bit / D8 is at "0" level.

Next, consider the lower bit priority mode (forward search).

The precharge signal / PR goes to "1" level, and each node of the carry lines 8 of the priority encoders 5a and 5b goes to "1" level (power supply potential VC).
C) is precharged. After this, the control signal PRLH
Becomes "1" level, the control signal PRHL becomes "0" level, the MOS transistor M1 is turned on, and the MOS transistor M2 is turned off.

The operated input signals / D8 , / D2 are at the "0" level, and the other operated input signals / D15.
~ / D7 , / D6 to / D3 , / D1, / D0 are assumed to be at "1" level.

At this time, as shown in Table 7, the input signal to be operated of the priority encoder 5a (when m = 15)
Are / D15 to / D9 = "1" and / D8 = "0", the output signal Ea is Q2 = "0", Q1 =
"0", Q0 = "0", flag output signal / Fa
Becomes a “0” level (hit O).

The operation input signals (when m = 7) of the priority encoder 5b are: / D7 to / D3 = “1”,
Since / D2 = “0” and / D1 to / D0 = “1”,
The output signal Eb has Q2 = "0", Q1 = "1", Q
0 = “0”, and the flag output signal / Fb becomes “0” level (hit O).

Further, the input signals of the priority encoder 5e are / Fa = "0" (hit O) and / Fb = "0" (hit O) from the upper bit to the lower bit, respectively.

Therefore, as shown in Table 5, the output signal (encode value) Ee of the priority encoder 5e is
X0 = “0”.

As shown in Table 6, the selector 6 receives the output signal (encode value) Ee (X0 = "0"), selects the output signal Eb of the priority encoder 5b, and outputs the output signal. Output as E '.

The connector 7 is a priority encoder 5
The output signal Ee of e is set to the upper bit side, and the output signal E ′ of the selector 6 is set to the lower bit side, and both output signals are connected. That is, the coupler 7 outputs "0", "0", "1", "0" as the 4-bit output signal EOUT.

The 4-bit output signal EOUT is "2" when expressed in decimal, and when the search is performed from the lower bit side, the first "0" level is bit / D2. . That is, it is confirmed that the bit / D2 is at "0" level.

According to the bit search circuit having the above configuration, 1
The 6-bit operated input signal is divided into two blocks in 8-bit units, and the first "0" level bit search is performed for each block. After that, the second search is performed as to which one of the two blocks contains the "0" level bit.

In this way, the "0" level bit
By dividing the channel into two stages, the discharge time of each priority encoder can be reduced to a maximum of 1/2 as compared with the discharge time of the conventional 16-bit priority encoder. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal to be operated increases.

Further, in the conventional priority encoder, the discharge time greatly varies depending on the position of the "0" level bit. Since the input signal to be operated is divided into two blocks in units of 8 bits, variations in the discharge time can be made smaller than in the conventional case.

[C] FIG. 7 shows a 16-bit bit search circuit according to the third embodiment of the present invention.

This bit search circuit comprises nine priority encoders 5a to 5i, a selector 6 and a coupler 7.
It consists of

The priority encoder 5a has two consecutive high-order 2-bit operand input signals / D15 , / D.
14 has been entered. Priority encoder 5a
Encodes which bit of the operated input signals / D15 , / D14 is at "0" level, and outputs the result as a 1-bit output signal Ea. The priority encoder 5a has a 1-bit flag output signal / Fa indicating whether or not the operated input signals / D15 , / D14 include a "0" level bit.
Will also be output.

That is, the input signals to be operated / D15 , / D14
If at least one bit of these is "0" level,
The flag output signal / Fa becomes "0" level. Also,
If the bits of the operated input signals / D15 , / D14 are both "1" level, the flag output signal / Fa is
It becomes "1" level.

The priority encoder 5b has a continuous 2-bit operand input signal / D13 , / D on the upper side.
12 has been entered. Priority encoder 5b
Encodes which bit of the operated input signals / D13 , / D12 is at "0" level, and outputs the result as a 1-bit output signal Eb. The priority encoder 5b has a 1-bit flag output signal / Fb indicating whether or not the operated input signals / D13 , / D12 include a "0" level bit.
Will also be output.

That is, the input signals to be operated / D13 , / D12
If at least one bit of these is "0" level,
The flag output signal / Fb becomes "0" level. Also,
If the bits of the operated input signals / D13 , / D12 are both at "1" level, the flag output signal / Fb is
It becomes "1" level.

Similarly, the priority encoder 5c
Inputs 2-bit processed input signals / D11 , / D10 and outputs output signals Ec, / Fc. The priority encoder 5d is a 2-bit operated input signal / D.
9 and / D8 are input and output signals Ed and / Fd are output. The priority encoder 5e inputs the 2-bit operated input signals / D7 , / D6 and outputs the output signals Ee, /
Output Fe. Priority encoder 5f is 2
Bit- operated input signals / D5 , / D4 are input and output signals Ef, / Ff are output. Priority Enco-
The da 5g receives the 2-bit processed input signals / D3 , / D2 and outputs the output signals Eg, / Fg. The priority encoder 5h is a 2-bit operand input signal / D.
1 and / D0 are input and output signals Eh and / Fh are output.

The flag output signals / Fa to / Fh of the priority encoders 5a to 5h are input to the priority encoder 5i. The priority encoder 5i encodes which bit of the input signals / Fa to / Fh is at "0" level, and outputs the result as a 3-bit output signal Ei.

The selector 6 has a priority encoder.
The output signals Ea to Eh of the das 5a to 5h are input.
The selector 6 receives the priority encoder on the basis of the 3-bit output signal Ei of the priority encoder 5i.
One of the output signals Ea to Eh of the das 5a to 5h is selected and output.

The 3-bit output signal Ei of the priority encoder 5i and the 1-bit output signal E'of the selector 6 are input to the coupler 7. The coupler 7 connects both output signals to each other with the output signal Ei on the upper side and the output signal E ′ on the lower side, and outputs the 4-bit output signal EOUT.

FIG. 8 shows the configuration of the priority encoders 5a-5h shown in FIG. Since each priority encoder has the same configuration, the configuration will be described using the priority encoder 5a as an example.

The priority encoder 5a includes two selectors 10-1, 10-0 and an encoder stage 1.
1 is comprised.

The selector 10-1 supplies the operated input signal D
15 is input, and the input signal / D14 to be operated is input to the selector 10-0.

Each selector has the same structure. Therefore, the selector 10-1 will be described. The selector 10-1 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source / drain of the MOS transistor N3 is connected to the carry line 8, and the gate of the MOS transistor N3 receives the operated input signal / D15 . The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. In addition, the NOR circuit 15 includes an input signal / D1 to be operated.
5 and the output signal of the AND circuit 14 are input, and the output signal thereof is input to the encoder stage 11.

The encoder stage 11 is the selector 10
Receiving the output signal of -1,10-0, operand input signal /
In addition to outputting a 1-bit output signal Ea indicating which bit of D15 , / D14 is at the "0" level,
A 1-bit flag output signal / Fa indicating whether or not a bit of "0" level is included in the operated input signals / D15 , / D14 is output.

An N-channel MOS transistor M1 for discharge is connected to the lower bit side end of the carry line 8. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to the carry line 8 is set to "1" level (power supply potential VC when the precharge signal / PR becomes "0" level.
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

Each node has an input signal / D15, ...
According to the level of / D8 , it is discharged to the "0" level (ground potential).

FIG. 9 shows the configuration of the priority encoder 5i shown in FIG.

The priority encoder 5i is composed of eight selectors 10-7, 10-0 and an encoder stage 11.

The output signal / Fa of the priority encoder 5a is input to the selector 10-7, and the selector 1
The output signal / Fb of the priority encoder 5b is input to 0-6. Similarly, the selectors 10-5,
-10 to 0, priority encoders 5c to 5h
Output signals / Fc to / Fh are input.

Each selector has the same structure. Therefore, the selector 10-7 will be described. The selector 10-7 includes, for example, a P-channel type MOS transistor P3, an N-channel type MOS transistor N3 and an OR.
It is composed of a circuit 12.13, an AND circuit 14 and a NOR circuit 15.

The source and drain of the MOS transistor N3 are connected to the carry line 8 and the gate of the operated input signal / D15 is input. The source of the MOS transistor P3 is connected to the power supply VCC, the drain is connected to the node 9-3, and the gate is a precharger.
Signal / PR is being applied.

The OR circuit 12 has a control signal / SL and a NOR signal.
The potential of the terminal 9-3 is input. The control signal / SH and the ground potential VSS are input to the OR circuit 13. The output signals of the OR circuits 12 and 13 are input to the AND circuit 14. Further, the output signal / Fa of the priority encoder 5a and the output signal of the AND circuit 14 are input to the NOR circuit 15, and the output signal thereof is the encoder stage 11
Is input to

The encoder stage 11 is the selector 10
Receiving the output signals of -7 and -10-0, it outputs a 3-bit output signal Ei indicating which bit of the output signals / Fa to / Fh of the eight priority encoders is the "0" level. To do.

An N-channel MOS transistor M1 for discharge is connected to the lower bit side end of the carry line 8. MOS transistor M
ON / OFF of 1 is controlled by the control signal PRLH. When the MOS transistor M1 is turned on, it is in the lower bit priority designation mode.

An N-channel MOS transistor M2 for discharge is connected to the end of the carry line 8 on the upper bit side. ON / OFF of the MOS transistor M2 is controlled by the control signal PRHL.
When the MOS transistor M2 is turned on, the high-order bit priority designation mode is set.

Each node of the MOS transistors connected to carry line 8 is set to "1" level (power supply potential VC when precharge signal / PR becomes "0" level).
C) is precharged.

In the lower bit priority mode, since the control signal PRLH is at "1" level and the control signal PRHL is at "0" level, the MOS transistor M1 is in the ON state,
The MOS transistor M2 is turned off.

In the higher bit priority mode, the control signal PRHL is at "1" level and the control signal PRLH is at "0" level, so that the MOS transistor M2 is in the ON state,
The MOS transistor M1 is turned off.

Each node has a flag output signal / Fa, 〜 /
According to the level of Fh, it is discharged to the "0" level (ground potential).

Next, the operation of the bit search circuit of FIGS. 7 to 9 will be described.

Table 8 shows priority encoders 5a to 5a.
It shows the operation of 5h.

[0205]

[Table 8] Table 9 shows the operation of the priority encoder 5i.

[0206]

[Table 9] Table 10 shows the operation of the selector 6.

[0207]

[Table 10] First, upper bit priority mode (backward search)
think of.

The precharge signal / PR goes to "0" level and each node of the carry lines 8 of the priority encoders 5a to 5h goes to "1" level (power supply potential VC).
C) is precharged. After this, the control signal PRHL
Becomes "1" level, the control signal PRLH becomes "0" level, the MOS transistor M2 is turned on and the MOS transistor M1 is turned off.

Further, the operated input signals / D8 , / D2 are at "0" level, and the other operated input signals / D15.
~ / D7 , / D6 to / D3 , / D1, / D0 are assumed to be at "1" level.

At this time, as shown in Table 8, the operated input signal of the priority encoder 5a (when m = 15)
, / D15 , / D14 = “1”, the output signal Ea becomes Q0 = “0”, and the flag output signal / F
a becomes a "1" level (miss hit x).

The operated input signals (when m = 13) of the priority encoder 5b are: / D13 , / D12 =
Since it is "1", its output signal Eb is Q0 = "0".
Therefore, the flag output signal / Fb becomes the "1" level (miss hit x).

The operation input signals (when m = 11) of the priority encoder 5c are: / D11 , / D10 =
Since it is "1", its output signal Ec is Q0 = "0".
Therefore, the flag output signal / Fc becomes "1" level (miss hit x).

The operated input signal (when m = 9) of the priority encoder 5d is: / D9 = "1", / D8 =
Since it is "0", the output signal Ed is Q0 = "0".
Therefore, the flag output signal / Fd becomes "0" level (hit O).

Since the operated input signal (when m = 7) of the priority encoder 5e is / D7 , / D6 = "1", its output signal Ee becomes Q0 = "0",
The flag output signal / Fe becomes "1" level (miss hit x).

Since the operated input signal (when m = 5) of the priority encoder 5f is / D5 , / D4 = "1", its output signal Ef becomes Q0 = "0",
The flag output signal / Ff becomes "1" level (miss hit x).

The operated input signal (when m = 3) of the priority encoder 5g is: / D3 = "1", / D2 =
Since it is "0", its output signal Eg is Q0 = "0".
Therefore, the flag output signal / Fg becomes "0" level (hit O).

Since the operated input signals (when m = 1) of the priority encoder 5h are / D1 and / D0 = "1", the output signal Eh thereof is Q0 = "0",
The flag output signal / Fh becomes "1" level (miss hit x).

Therefore, as shown in Table 9, the flag signal input to the priority encoder 5i is / Fa =
"1", / Fb = "1", / Fc = "1", / Fd =
"0", / Fe = "1", / Ff = "1", / Fg =
"0" and / Fh = "1", and the output signal (encode value) Ei is X2 = "1", X1 = "0", X0 =
It becomes "0".

As shown in Table 10, the selector 6 outputs this output signal (encode value) Ei (X2 = "1", X1 =
In response to "0", X0 = "0"), the output signal Ed of the priority encoder 5d is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The 3-bit output signal Ei of i is set to the high-order bit side, and the 1-bit output signal E ′ of the selector 6 is set to the low-order bit side, and both output signals are connected. That is, the coupler 7
Is "1" as the 4-bit output signal EOUT,
Outputs "0", "0", "0".

The 4-bit output signal EOUT is "8" when expressed in decimal, and it is understood that the "0" level that appears first when searching from the upper bit side is bit / D8. . That is, it is confirmed that the bit / D8 is at "0" level.

Next, consider the lower bit priority mode (forward search).

The precharge signal / PR becomes "0" level, and each node of the carry lines 8 of the priority encoders 5a to 5h becomes "1" level (power supply potential VC).
C) is precharged. After this, the control signal PRLH
Becomes "1" level, the control signal PRHL becomes "0" level, the MOS transistor M1 is turned on, and the MOS transistor M2 is turned off.

The operated input signals / D8 and / D2 are at "0" level, and the other operated input signals / D15 are
~ / D7 , / D6 to / D3 , / D1, / D0 are assumed to be at "1" level.

At this time, as shown in Table 8, the operated input signal of the priority encoder 5a (when m = 15)
, / D15 , / D14 = “1”, the output signal Ea becomes Q0 = “0”, and the flag output signal / F
a becomes a "1" level (miss hit x).

The operation input signals (when m = 13) of the priority encoder 5b are: / D13 , / D12 =
Since it is "1", its output signal Eb is Q0 = "0".
Therefore, the flag output signal / Fb becomes the "1" level (miss hit x).

The operation input signals (when m = 11) of the priority encoder 5c are: / D11 , / D10 =
Since it is "1", its output signal Ec is Q0 = "0".
Therefore, the flag output signal / Fc becomes "1" level (miss hit x).

The operation input signal (when m = 9) of the priority encoder 5d is: / D9 = “1”, / D8 =
Since it is "0", the output signal Ed is Q0 = "0".
Therefore, the flag output signal / Fd becomes "0" level (hit O).

The operated input signals (when m = 7) of the priority encoder 5e are / D7 , / D6 = “1”, so that the output signal Ee becomes Q0 = “0”,
The flag output signal / Fe becomes "1" level (miss hit x).

Since the operated input signal (when m = 5) of the priority encoder 5f is / D5 , / D4 = "1", its output signal Ef becomes Q0 = "0",
The flag output signal / Ff becomes "1" level (miss hit x).

The operation input signals (when m = 3) of the priority encoder 5g are: / D3 = "1", / D2 =
Since it is "0", its output signal Eg is Q0 = "0".
Therefore, the flag output signal / Fg becomes "0" level (hit O).

The operation input signals (when m = 1) of the priority encoder 5h are / D1 and / D0 = "1", so that the output signal Eh becomes Q0 = "0",
The flag output signal / Fh becomes "1" level (miss hit x).

Therefore, as shown in Table 9, the flag signal input to the priority encoder 5i is / Fa =
"1", / Fb = "1", / Fc = "1", / Fd =
"0", / Fe = "1", / Ff = "1", / Fg =
"0" and / Fh = "1", and the output signal (encode value) Ei is X2 = "0", X1 = "0", X0 =
It becomes “1”.

As shown in Table 10, the selector 6 outputs the output signal (encode value) Ei (X2 = "0", X1 =
In response to "0", X0 = "1"), the output signal Eg of the priority encoder 5g is selected and output as the output signal E '.

The connector 7 is a priority encoder 5
The 3-bit output signal Ei of i is set to the high-order bit side, and the 1-bit output signal E ′ of the selector 6 is set to the low-order bit side, and both output signals are connected. That is, the coupler 7
Is "0" as a 4-bit output signal EOUT,
It outputs "0", "1", and "0".

The 4-bit output signal EOUT is "2" when expressed in decimal, and when the search is performed from the lower bit side, the "0" level that appears first is bit / D2. . That is, it is confirmed that the bit / D2 is at "0" level.

According to the bit search circuit having the above configuration, 1
The 6-bit operated input signal is divided into 8 blocks in units of 2 bits, and the first "0" level bit search is performed for each block. After that, the second search is performed as to which one of the two blocks contains the "0" level bit.

[0238] Thus, the "0" level bit server
By dividing the channel into two stages, the discharge time of each priority encoder can be shortened to a maximum of 1/8 of the discharge time of the conventional 16-bit priority encoder. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal to be operated increases.

Further, in the conventional priority encoder, the discharge time greatly varies depending on the position of the bit of "0" level, but in the bit search circuit of the present invention, 16 bits are used. Since the input signal to be operated is divided into 8 blocks in units of 2 bits, variations in the discharge time can be made smaller than in the conventional case.

[0240]

As described above, according to the bit search circuit of the present invention, the following effects can be obtained.

An input signal of i (for example, i = 16) bits is converted into 2 ^k (j is 1, 2 or 3) bit units by 2 ^k (k is
It is divided into 3, 2 or 1) blocks, and the first "0" level bit search is performed for each block. After this, the second block of which of the 2 ^k blocks has the bit of the “0” level is
We are conducting the second search.

As described above, by dividing the method of searching the "0" level bit from the i-bit input signal into two steps, the discharge time of the priority encoder can be greatly shortened. . That is, it is possible to provide a bit search circuit that can operate at high speed in a small area even if the number of bits of the input signal increases.

Further, since the i-bit input signal is divided into 2 ^k blocks in units of 2 ^j bits, variations in discharge time can be reduced.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

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Claims (2)

[Claims] 1. Continuous 2 ^j of i-bit input signals
(J is a natural number) is input bits, the outputs a flag signal indicating whether it contains a first level bit Some 2 ^j bits, and first Some of the 2 ^j bits
2 ^k (where i = 2 ^{j + k} ) first encoders for outputting a j-bit first encoded signal for specifying the bit of the first level when the bit of the level is included And a flag signal of each first encoder is input, and a k-bit second encode signal for specifying the first encoder including the bit of the first level based on this flag signal is supplied. A second encoder to output and a second encoder signal from the second encoder are input,
The first encoding specified by the second encoding signal
A selector for selecting and outputting the first encode signal of the decoder, a second encode signal of the second encoder on the upper bit side, and a first encoder of the specified first encoder The encode signal is set to the lower bit side, and the first and second
A concatenator for concatenating the encode signals and outputting a j + k-bit third encode signal for specifying a first level bit included in the i-bit input signal. Bit search circuit. 2. The bit search circuit according to claim 1, wherein the first and second encoders have a function of selecting and designating an upper bit priority mode and a lower bit priority mode. However, in the high-order bit priority mode, the first level bit existing on the most significant bit side of the i-bit input signal is specified, and in the low-order bit priority mode, the i-bit A bit search circuit characterized in that a first level bit existing on the least significant bit side is specified from among input signals.