JPH08293789A - Generation circuit for internal clock signal - Google Patents

Abstract

PURPOSE: To provide an internal clock signal generation circuit by which a correct internal clock signal can be obtained even in the case where an external clock signal is of small amplitude. CONSTITUTION: In the internal clock signal generation circuit (PLL, etc.), it is constituted so as to be provided with an amplitude converting means 10 which converts the internal clock signal into the internal clock signal of the amplitude similar to the external clock signal, and inputs that converted internal clock signal to a phase comparing means 100. By converting the internal clock signal into the internal clock signal of the small amplitude similar to the external clock signal, the internal clock signal locked exactly to the external clock signal can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (hereinafter referred to as PLL) and a delay locked loop (hereinafter referred to as D).
It is called LL. ) Internal clock signal generation circuit, and more particularly to an internal clock signal generation circuit used for an interface for small amplitude.

[0002]

2. Description of the Related Art Conventionally, TTL (Transistor-Transistor Logic) has been mainly used as an interface standard for memory LSIs. The TTL level is input / output of 2.4 V or more with respect to the logic "1", and 0.
It is specified that the input is 8V or less and the output is 0.4V or less. However, LVTTL (Low Voltage), which is a lower voltage of TTL, comes with the lowering of the power supply voltage (5.0V → 3.3V).
TTL) has come into use. In the case of LVTTL, the level regulation is distinguished into a determination level (AC spec) and a final level (DC spec) at which a signal reaches. In the AC spec, an input / output of 2.0 V or more with respect to a logic “1”, a logic Input / output of 0.8 V or less for "0", input / output of 2.4 V or more for logic "1", input of 0.8 V or less for logic "0", 0. It is defined as an output of 4V or less.

However, as the operating frequency of the microprocessor rises, the operating speed limit of the TTL and LVTTL interfaces is approaching. For example, 100pF
The problem that the required access time is exceeded due to the delay time when charging / discharging a certain load capacity to 2.4V / 0.4V, and overshoot and undershoot of the output signal due to high-speed switching The problem that the output waveform is distorted due to shooting, ringing, etc. and the judgment level is broken down has been highlighted. Therefore, GTL (Gunning) is a high-speed interface that suppresses signal amplitude.
Transceiver Logic) and HSTL (High Speed Transcei)
ver Logic) etc. have been proposed.

Further, as described above, with the increase in the speed of the microprocessor, the problem of increasing the speed of the internal clock signal is becoming unavoidable from the viewpoint of the performance of the entire system. There has been proposed an internal clock signal generation circuit using a PLL for receiving an internal or external clock signal and generating an internal clock signal synchronized with the external clock signal.

FIG. 9 shows a block diagram of a basic circuit configuration of a conventional PLL. In FIG. 9, 1a and 1b are input buffers having the same internal configuration as each other, 2a and 2b are clock buffers having the same internal configuration as each other, 3 is a phase detector, 4 is a charge pump, 5 is a charge pump 4. Is a loop filter that outputs the signal VCOIN by filtering the output of VCOIN, 6a is a voltage controlled oscillator that receives the signal VCOIN, 100 is a phase comparison means, and 101 is a voltage controlled oscillation means.

Next, the structure will be described. The output of the voltage controlled oscillator 6a is connected to the inputs of the clock buffer 2a and the clock buffer 2b. Clock buffer 2
The output of b is connected to the input of the phase detector 3 via the input buffer 1b. The external clock signal is also connected to the input of the phase detector 3 via the input buffer 1a. The output of the phase detector 3 (signal / UP and signal DOWN) is connected to the input of the charge pump 4. The output of the charge pump 4 is connected to the input of the loop filter 5. The output of the loop filter 5 is connected to the input of the power supply controlled oscillator 6a.

From the input buffer 1a, the input buffer 1b, the phase detector 3 and the charge pump 4, the phase comparison means 10 is provided.
Configure 0. The voltage-controlled oscillator 1 includes the clock buffer 2a, the clock buffer 2b, and the voltage-controlled oscillator 6a.
Configure 01. The output signal of the input buffer 1a is the signal E
CLK. The output signal of the input buffer 1b is the signal RC
Let it be LK. The output signal of the loop filter 5 is the control signal V
COIN. The output end of the clock buffer 2a is a node 7c, and the output end of the clock buffer 2b is a node 7c.
b. The signals at nodes 7b and 7c are internal clock signals. An external clock signal having a small amplitude is input to the input of the input buffer 1a.

FIG. 10 shows a circuit example of the phase detector 3. FIG. 11 shows an example of a circuit in which the loop filter 5 is connected to the charge pump 4. The voltage controlled oscillator 6a is shown in FIGS.
The circuit example of is shown. The voltage controlled oscillator 6a is composed of a ring oscillator circuit in which a plurality of stages of the current mirror circuit shown in FIG. 12 and the inverter shown in FIG. 13 are connected, and the output signal from the ring oscillator circuit is the clock buffers 2a and 2b.
It is output as an internal clock signal via b.

Next, the operation will be described. Phase detector 3
When the signal ECLK and the signal RCLK are input, the phases of the two signals are compared, and the phase of the signal ECLK is the signal RCL.
The signal / UP is output when the phase of K is advanced, and the signal DOWN is output when the phase of K is delayed. Charge pump 4
When the signal / UP and the signal DOWN are input, the digital amount is converted into the analog amount, and the signal / UP and the signal DOWN are input.
A current corresponding to the phase difference is output by flowing a current into or out of the loop filter 5 for the time corresponding to the phase difference. The loop filter 5 filters the output of the charge pump 4 and outputs the control signal VCOIN. The voltage controlled oscillator 6a generates an oscillation signal controlled by the control signal VCOIN and outputs an internal clock signal to the nodes 7c and 7b.

The external clock signal is output as a signal ECLK via the input buffer 1a. The internal clock signal of the node 7b also receives the signal RCLK
Is output as In this way, similarly to the path configuration of the external clock signal → the input buffer 1a → the phase detector 3, modeling of the path configuration of the internal clock signal → the input buffer 1b → the phase detector 3 is performed for the internal clock signal, A signal RCLK in which the signal level and transition time of the internal clock signal are matched with the external clock signal is generated. Signal RCLK and signal EC obtained by performing this modeling
By inputting LK to the phase detector 3, the phases of two signals of the same level are compared with each other, so that an accurate phase difference can be detected.

[0011]

However, there is a problem in the above-mentioned configuration in the currently proposed high-speed interface with suppressed signal amplitude. GTL and HS
In a high-speed interface such as TL, the amplitude of the signal input to the input buffer and the signal output from the output buffer is suppressed. FIG. 14 shows a schematic diagram of a general system using the GTL interface. In FIG.
VTT = via resistors 91a and 91b whose both ends are 50Ω
LOGIC 95a, 95 to the wiring terminated to 1.2V
Three devices b and 95c are connected. Open drain N-channel transistors 93a, 93b, 9
3c serves as a driver, and differential comparators 94a, 94b, 9
4c is a receiver. Reference signal V of differential comparator
REF is specified as 0.8V. When the device outputs a logical "0", the driver is turned on, and a signal amplitude of 1 V or less can be obtained by the voltage drop caused by the driving current of the transistor flowing through the terminating resistor. When the device outputs a logic "1", the driver transistor remains off and the signal level remains VTT = 1.2V. When inputting to the device, the receiver compares and amplifies the minute voltage on the wiring and the reference signal VREF and transmits the signal inside the device. In the case of GTL, the output level is regulated to 0.4 V or less for logic "0" and 1.2 V for logic "1". The input level is defined as logic "0".
0.75V or less, 0.8 for logic "1"
It is over 5V.

In an LSI to which such a high speed interface is applied, an internal clock signal generating circuit shown in FIG.
When such a PLL is used, the external clock signal has a small amplitude, whereas the internal clock signal does not have a small amplitude but a normal amplitude. On the other hand, the input buffer 1a and the input buffer 1 used in the input stage of the phase comparison means 100.
b has a determination level for small amplitude. Therefore, when the internal clock signal and the external clock signal having different amplitudes are input to the phase comparison means 100, a new phase difference is generated by the determination of the input of the input buffer 1a or the input buffer 1b, and the phase difference is caused by the signals ECLK and RCLK. Therefore, an accurate phase difference cannot be detected, and an erroneous phase difference is detected.

As described above, in the conventional LSI, the PL
For an internal clock signal generation circuit such as L, GTL or HS
When a high-speed interface such as TL is used, the internal clock signal is not accurately modeled, a wrong phase difference is detected, and an accurate internal clock signal cannot be generated.

The present invention has been made in order to solve the above problems, and provides an internal clock signal generation circuit capable of obtaining an accurate internal clock signal even when the external clock signal has a small amplitude. With the goal.

[0015]

According to a first aspect of the present invention, the problem solving means receives an external clock signal having a relatively small amplitude and is locked to the phase and frequency of the external clock signal and has a relatively large amplitude. An internal clock signal generation circuit using a phase-locked loop for outputting an internal clock signal, comprising: voltage-controlled oscillation means for generating and outputting the internal clock signal of relatively large amplitude; and the internal clock signal of relatively large amplitude. In response to this, an amplitude converting means for reducing the amplitude of the internal clock signal having a relatively large amplitude to generate and outputting an internal clock signal having a relatively small amplitude comparable to the external clock signal; External clock signal having a relatively small amplitude and the internal clock signal having a relatively small amplitude, and receiving the external clock signal having a relatively small amplitude. The relatively small amplitude internal clock signal to the phase comparator, and a phase comparison means for controlling said voltage controlled oscillation means based on the phase comparison.

The problem solving means according to claim 2 of the present invention is
An internal clock signal generation circuit using a delay locked loop for receiving an external clock signal of relatively small amplitude and outputting an internal clock signal of relatively large amplitude locked to the phase and frequency of the external clock signal,
The voltage control delay means for generating and outputting the internal clock signal having a relatively large amplitude, and the internal clock signal having a relatively large amplitude are received to reduce the amplitude of the internal clock signal having a relatively large amplitude. Amplitude converting means for generating and outputting an internal clock signal having a relatively small amplitude similar to that of an external clock signal, the external clock signal having a relatively small amplitude and the internal clock signal having a relatively small amplitude, The external clock signal having a relatively small amplitude and the internal clock signal having a relatively small amplitude are compared in phase, and the phase comparison means controls the voltage control delay means based on the phase comparison.

In the problem solving means according to claim 3 of the present invention, in the amplitude converting means, the first current electrode is connected to the first power source side, and the control electrode is a first receiving a reference signal. A transistor, a first current electrode connected to a second current electrode of the first transistor, a second current electrode connected to a second power supply side, and a control electrode connected to a second transistor receiving the reference signal. A second current electrode of the first transistor and a first current electrode of the second transistor.
The output of the voltage controlled oscillation means and the input of the phase comparison means are connected to a connection node with the current electrode.

In the problem solving means according to claim 4 of the present invention, in the amplitude converting means, the first current electrode is connected to the first power source side, and the control electrode is a first receiving a reference signal. A transistor, a first current electrode connected to a second current electrode of the first transistor, a second current electrode connected to a second power supply side, and a control electrode connected to a second transistor receiving the reference signal. A second current electrode of the first transistor and a first current electrode of the second transistor.
The output of the voltage control delay means and the input of the phase comparison means are connected to a connection node with the current electrode.

In the problem solving means according to claim 5 of the present invention, the amplitude converting means includes means for applying a first voltage, means for applying a second voltage, and the internal clock having a relatively large amplitude. Switch means for receiving a signal and selectively switching between the first voltage and the second voltage based on the relatively large amplitude internal clock signal to output the relatively small amplitude internal clock signal. With.

In the means for solving the problem according to claim 6 of the present invention, the means for applying the first voltage comprises a transistor array in which a plurality of transistors in which one current electrode and a control electrode are connected are connected in series. One end of the transistor array is connected to a power supply, and the other end is provided with a power supply voltage down means for outputting the first voltage.

In the problem solving means according to claim 7 of the present invention, the switch means has an inverter for receiving the internal clock signal having a relatively large amplitude, and a first current electrode connected to the first voltage. A second current electrode connected to the second voltage and a control electrode receiving the output of the inverter.

[0022]

In the internal clock signal generating circuit according to the first aspect of the present invention, the amplitude converting means compares the internal clock signals having a relatively large amplitude so as to have the same amplitude as the external clock signal having a relatively small amplitude. Converting (modeling) to an internal clock signal with small dynamic amplitude. Next, the external clock signal and the modeled internal clock signal are phase-compared by the phase comparison means to detect an accurate phase difference, and the voltage-controlled oscillation means is controlled to have the same phase as the external clock signal. Generates an internal clock signal.

In the internal clock signal generating circuit according to the second aspect of the present invention, the amplitude converting means compares the internal clock signals having a relatively large amplitude so as to have the same amplitude as the external clock signal having a relatively small amplitude. Converting (modeling) to an internal clock signal with small dynamic amplitude. Next, the external clock signal and the modeled internal clock signal are phase-compared by the phase comparison means to detect an accurate phase difference, and the voltage control delay means is controlled to have the same phase as the external clock signal. Generates an internal clock signal.

In the internal clock signal generating circuit according to the third aspect of the present invention, the voltage controlled oscillation means has the following formula: [potential of the first current electrode of the first transistor−Vt of the first transistor].
Even if an internal clock signal having an amplitude of [h level] is to be output, the potential of the connection node between the second current electrode of the first transistor and the first current electrode of the second transistor is [ Reference signal potential + Vt
h]. On the other hand, even if the voltage controlled oscillating means attempts to output the internal clock signal having the amplitude of the potential level of the second current electrode of the second transistor, the potential of the connection node is [the reference signal Potential-Vth]. That is, the internal clock signal is clamped into an internal clock signal having a relatively small amplitude.

In the internal clock signal generating circuit according to the fourth aspect of the present invention, the voltage control delay means has an internal clock signal having an amplitude of [potential of the first current electrode of the first transistor−Vth level of the first transistor]. , The second transistor is turned on and the second current electrode of the first transistor and the first transistor of the second transistor are turned on.
The potential of the connection node with the current electrode is [the potential of the reference signal + V
th]. On the other hand, even if the voltage control delay unit tries to output the internal clock signal having the amplitude of the potential level of the second current electrode of the second transistor, the potential of the connection node is [the reference signal Potential-Vth]. That is, the internal clock signal is clamped into an internal clock signal having a relatively small amplitude.

In the internal clock signal generating circuit according to the fifth aspect of the present invention, the switch means selectively outputs the first voltage and the second voltage based on the internal clock signal having a relatively large amplitude. Thus, the internal clock signal having a relatively large amplitude is converted into the internal clock signal having a relatively small amplitude.

In the internal clock signal generation circuit according to the sixth aspect of the present invention, the transistor array steps down the power source to generate the first clock signal.
To generate the voltage.

In the internal clock signal generation circuit according to the seventh aspect of the present invention, the internal clock signal having a relatively large amplitude is waveform-shaped by the inverter, and the output thereof turns on or off the transistor to turn the first voltage and the first voltage. The voltage of 2 is selectively switched to output an internal clock signal having a relatively small amplitude.

[0029]

【Example】

{First Embodiment} A first embodiment will be described. FIG.
FIG. 3 is a block diagram of an internal clock signal generation circuit having a PLL structure capable of obtaining an accurate internal clock signal even when the external clock signal has a small amplitude according to the first embodiment of the present invention. In FIG. 1, 10 is an amplitude converting means, 11 is an n-channel FET, 12 is a p-channel FET, and other symbols correspond to the symbols in FIG.

Next, the structure will be described. As shown in FIG. 1, the source of the FET 11 is connected to the power supply Vcc,
The drain of T11 is connected to the source of the FET 12 and the output of the clock buffer 2b, and the gate of the FET 11 is FE.
It receives the reference signal VREF together with the gate of T12.
The drain of the FET 12 is grounded. The FET 11 and the FET 12 constitute the amplitude converting means 10. Other configurations are the same as those of the PLL shown in FIG.

Next, the operation will be described. P of this embodiment
The main operation of the LL is the same as that of the PLL shown in FIG. The external clock signal has a small amplitude, and this external clock signal is input to the input buffer 1a having the determination level corresponding to the small amplitude and supplied to the normal LSI at the power supply level (Vcc).
Up to GND) and is supplied to the phase detector 3 inside the LSI (inside the chip). The internal clock signal of node 7b has a normal amplitude. Next, the internal clock signal of the node 7b is converted into an amplitude of the same level as the external clock signal by the amplitude converting means 10, and the internal clock signal of a small amplitude is output to the node 7a.

The operation of the amplitude converting means 10 will be described in detail. Reference signal VR is applied to the gates of FET 11 and FET 12.
Since EF (for example, 0.8V) is added, the internal clock signal that is about to change from the GND level to the Vcc level is clamped to a small amplitude centered around the reference signal VREF = 0.8V. Even if the voltage controlled oscillator 101 tries to output an internal clock signal having an amplitude of [power supply Vcc-Vth level of FET 11], the potential of the node 7a becomes [reference signal VREF + FET1 because the FET 12 is turned on.
2 Vth]. On the other hand, the voltage controlled oscillator 1
Even if 01 tries to output the internal clock signal having the amplitude of GND level, the potential of the node 7a rises to [reference signal VREF-Vth of FET 11] because the FET 11 is turned on. As a result, the internal clock signal having the normal amplitude from the GND level to the Vcc level is used as the reference signal V.
It can be clamped to a signal with a small amplitude of REF ± Vth.

In this way, modeling is performed in which the amplitude of the internal clock signal of the node 7b is set to the same level as the amplitude of the external clock signal, and the external clock signal and the internal clock signal having the same amplitude level are compared by the phase comparison means 100.
Is input to On the other hand, the input buffer 1a and the input buffer 1b used in the input stage of the phase comparison means 100 have a judgment level for small amplitude. For this reason, when the internal clock signal and the external clock signal having different amplitudes are input to the phase comparison means 100, the input judgment of the input buffer 1a and the input buffer 1b is deviated as described in the conventional technique. In the example, this does not occur, the phase difference can be accurately detected, and an erroneous phase difference is not detected.
Further, the amplitude of the internal clock signal at node 7c need not be changed.

As described above, when the PLL shown in FIG. 1 is used, even if the external clock signal has a small amplitude, the internal clock signal for phase comparison is converted into a small amplitude, so that the correct phase of the internal clock signal can be obtained. It is fed back, the accurate phase difference can be detected, and the internal clock signal having the same phase as the external clock signal can be generated.

{Second Embodiment} A second embodiment will be described. This embodiment is a further advance of the PLL shown in FIG. 1. When the external clock signal has a small amplitude, a buffer circuit similar to the output buffer circuit for converting the internal clock signal into a small amplitude level of GTL or HSTL is used. It is possible to obtain an internal clock signal for accurate phase comparison by converting to a small amplitude.

As described above, in high-speed interfaces such as GTL and HSTL, the amplitude of the signal input to the input buffer circuit and the signal output from the output buffer circuit are suppressed. In the case of GTL, the definition of the input level is 0.75 V or less for logic "0" and 0.85 V or more for logic "1". On the other hand, the regulation of the output level is 0.4 V or less for the logic "0" and 1.2 V for the logic "1".

This output level is realized by the buffer circuit shown in FIG. In FIG. 2, 24 is a resistor and 25 is an n-channel FET. The output buffer circuit shown in FIG. 2 is configured such that the drain of the FET 25 is grounded, the source of the FET 25 is connected to one end of the resistor 24, and the other end of the resistor 24 is connected to the termination voltage VTT. Then, the amplitude converting means 10 shown in FIG. 1 is removed, and the nodes 7a and 7b are removed.
The space is opened, the node 7a is connected to the source of the FET 25, and the node 7b is connected to the gate of the FET 25. With such a configuration, in the PLL, an internal clock signal for phase comparison having a normal amplitude is converted into a small amplitude by the buffer circuit shown in FIG. 2, and thereafter modeling is performed by the same input buffer 1b as the input buffer 1a. Therefore, the accurate phase difference can be detected. However, in the buffer circuit shown in FIG.
Is an external power supply, and the terminating resistor 24 is also an external resistor, which cannot be realized by a circuit inside the LSI.

Therefore, a PLL as shown in FIG. 3 is used. FIG. 3 is a block diagram of an internal clock signal generation circuit having a PLL structure according to the second embodiment of the present invention. In FIG. 3, 20 is an amplitude converting means, 21n is a p-channel FET,
Reference numeral 21 is a transistor array which is a power supply voltage step-down means composed of n FETs 21n, 22 is an n-channel FET, 23 is an inverter, and other reference numerals correspond to the reference numerals in FIG. The source of the first FET 21n counted from the power supply Vcc is connected to the power supply Vcc, and the gate of the FET 21n is the drain of the FET 21n and the second FET 21.
n sources. FET21 with the same connection
A transistor array 21 is formed by connecting n n transistors. The drain of the FET 21n, which is the nth transistor, is connected to the source of the FET 22 and the node 7a.
The drain of 22 is grounded, and the gate of the FET 22 is connected to the output of the inverter 23. The input of the inverter 23 is connected to the node 7b. Transistor row 2
1, the FET 22, and the inverter 23, the amplitude conversion means 2
Configure 0. Further, the FET 22 and the inverter 23 constitute a switching means. Other PLL shown in FIG.
The configuration is the same as that of the PLL shown in FIG.

Next, the operation will be described. P shown in FIG.
The main operation of the LL is the same as that of the PLL shown in FIG. 1. In the PLL shown in FIG. 1, the amplitude of the internal clock signal of the node 7b is converted by the amplitude converting means 10 and the node 7a is operated.
Output to the node 7b in the PLL shown in FIG.
The amplitude of the internal clock signal is converted by the amplitude converting means 20 and output to the node 7a.

The operation of the amplitude converting means 20 will be described in detail. In the PLL shown in FIG. 3, when the potential of the node 7b is at "H" level, the FET 22 is turned off, so that the potential of the node 7a is determined by the transistor array 21. In the amplitude converting means 20, the potential of the node 7d becomes [Vcc-Vth], and the potential of the node 7a becomes [Vcc- (n × Vth)]. Therefore, the potential of the node 7a can be set to a desired potential depending on the number of the transistor rows 21, so that the "H" level amplitude can be suppressed.

On the other hand, when the potential of the node 7b is "L" level, the FET 22 is turned on, so the potential of the node 7a is determined by the ratio of the on resistance of the transistor array 21 and the on resistance of the FET 22. Therefore, the potential of the node 7a can be set to a desired potential by adjusting the ratio of the on-resistances by the gate size of the transistor array 21 and the FET 22, etc., so that the "L" level amplitude can be suppressed. As a result, the amplitude of the internal clock signal of the node 7a can be suppressed, and the GTL shown in FIG.
It is possible to obtain a signal with a small amplitude similar to the output level of the HSTL output buffer circuit.

As described above, when the PLL shown in FIG. 3 is used, even if the external clock signal has a small amplitude, the internal clock signal for phase comparison is converted into a small amplitude, so that the correct phase of the internal clock signal can be obtained. It is fed back, the accurate phase difference can be detected, and the internal clock signal having the same phase as the external clock signal can be generated.

{Third Embodiment} Next, a third embodiment will be described. In this embodiment, the PLL shown in FIG. 1 is further advanced. When the internal clock signal is generated by the DLL using the voltage control delay means instead of the voltage control oscillation means, the external clock signal has a small amplitude. However, it is so designed that an accurate internal clock signal can be obtained.

FIG. 4 is a block diagram showing the structure of a general DLL which is the basis of the internal clock signal generation circuit in the third embodiment of the present invention. Reference numeral 6b in FIG. 4 corresponds to the voltage control delay element, and other reference numerals correspond to the reference numerals in FIG. As shown in FIG. 4, the configuration of this DLL is a configuration in which the voltage controlled oscillator 6a of FIG. 9 is replaced with a voltage controlled delay element 6b, and a signal ECLK other than the control signal VCOIN is further input to the voltage controlled delay element 6b. The input buffer 1a, the input buffer 1b, the phase detector 3, and the charge pump 4 constitute the phase comparison means 102. The voltage control delay means 103 is composed of the clock buffer 2a, the clock buffer 2b, and the voltage control delay element 6b.

5 and 6 show the voltage control delay element 6b.
An example of a circuit is shown. The voltage control delay element 6b is composed of the current mirror circuit shown in FIG. 5 and the inverter row connected in multiple stages shown in FIG.

Next, the operation of the voltage control delay element 6b will be described. Depending on the potential of the output VCOIN of the loop filter 5, VINP and VI of the current mirror circuit of FIG.
The potential of NN is determined, and by inputting VINP and VINN to the input IN of the inverter row in FIG.
The internal clock signal delayed by a certain time from CLK is obtained at the output OUT. After that, the phase of the fed back internal clock signal is again compared with the phase of the external clock signal, and the phases of the two signals match (lock), that is, the DLL outputs the internal clock signal locked to the external clock signal. .

Next, the operation of the DLL shown in FIG. 4 will be described.
The operation of the voltage control delay element 6b is as described above.
Input buffer 1a, input buffer 1b, phase detector 3,
The operation of the charge pump 4, the loop filter 5, the clock buffer 2a, and the clock buffer 2b is the PLL of FIG.
The operation is the same as that described in. The external clock signal is output as the signal ECLK via the input buffer 1a.
The internal clock signal of node 7b is also output as signal RCLK via input buffer 1b. In this way, similarly to the path configuration of the external clock signal → the input buffer 1a → the phase detector 3, modeling of the path configuration of the internal clock signal → the input buffer 1b → the phase detector 3 is performed for the internal clock signal, Signal RCL in which the signal level and transition time of the internal clock signal are matched with the external clock signal
Generate K. Signal R obtained by performing this modeling
By inputting the CLK and the signal ECLK to the phase detector 3, the phases of two signals of the same level are compared with each other, so that the accurate phase difference can be detected.

However, the L to which the high speed interface is applied
In SI, when the DLL shown in FIG. 4 is used as the internal clock signal generation circuit, the external clock signal has a small amplitude, whereas the internal clock signal does not have a small amplitude but a normal amplitude. On the other hand, the input buffer 1a and the input buffer 1b used in the input stage of the phase comparison means 102 have a judgment level for small amplitude. Therefore, when the internal clock signal and the external clock signal having different amplitudes are input to the phase comparison means 102, a new phase difference is generated due to the determination of the input of the input buffer 1a or the input buffer 1b.
Since the phase difference is included in the signals ECLK and RCLK,
An accurate phase difference cannot be detected, and an incorrect phase difference is detected.

FIG. 7 is a block diagram of an internal clock signal generation circuit having a DLL structure capable of obtaining an accurate internal clock signal even when the external clock signal has a small amplitude according to the third embodiment of the present invention. Reference numeral 10 in FIG. 7 corresponds to the amplitude converting means, and other reference numerals correspond to the reference numerals in FIG.

Next, the structure will be described. As shown in FIG. 7, the amplitude converting means 10 is connected between the clock buffer 2b and the input buffer 1b of the DLL of FIG. 4 by the same connection as the PLL shown in FIG. Amplitude conversion means 10
The internal configuration of is similar to the configuration of the amplitude converting means 10 in FIG.

Next, the operation will be described. D shown in FIG.
The main operation of the LL is the same as that of the DLL shown in FIG. The external clock signal has a small amplitude, and this external clock signal is input to the input buffer 1a having the determination level corresponding to the small amplitude and supplied to the normal LSI at the power supply level (Vcc).
Up to GND) and is supplied to the phase detector 3 inside the LSI (inside the chip). The internal clock signal of node 7b has a normal amplitude. Next, the internal clock signal of the node 7b is converted into an amplitude of the same level as the external clock signal by the amplitude converting means 10, and the internal clock signal of a small amplitude is output to the node 7a. The internal clock signal is locked to the external clock signal by the operation of the voltage control delay element 6b described above. The operation of the amplitude converting means 10 is similar to that described in the first embodiment.

In this way, modeling is performed so that the amplitude of the internal clock signal at the node 7b is the same level as the amplitude of the external clock signal, and the external clock signal and internal clock signal having the same amplitude level are compared by the phase comparison means 102.
Is input to On the other hand, the input buffer 1a and the input buffer 1b used in the input stage of the phase comparison means 102 have a judgment level for small amplitude. For this reason, when the internal clock signal and the external clock signal having different amplitudes are input to the phase comparison means 102, the input determination of the input buffer 1a or the input buffer 1b is shifted as described in the conventional technique. In the example, this does not occur, the phase difference can be accurately detected, and an erroneous phase difference is not detected. Further, the amplitude of the internal clock signal at node 7c need not be changed.

As described above, when the DLL shown in FIG. 7 is used, even if the external clock signal has a small amplitude, the internal clock signal for phase comparison is converted into a small amplitude, so that the correct phase of the internal clock signal can be obtained. It is fed back, the accurate phase difference can be detected, and the internal clock signal having the same phase as the external clock signal can be generated.

{Fourth Embodiment} Finally, a fourth embodiment will be described. This embodiment is a further development of the DLL shown in FIG. 7. When the DLL generates an internal clock signal, the internal clock signal is changed to GTL or HS.
A buffer circuit similar to the output buffer circuit that outputs a small amplitude level of TL can be converted into a small amplitude to obtain an accurate internal clock signal for phase comparison.

FIG. 8 is a block diagram of an internal clock signal generating circuit having a DLL structure capable of obtaining an accurate internal clock signal even when the external clock signal has a small amplitude according to the fourth embodiment of the present invention. Reference numeral 20 in FIG. 8 denotes an amplitude converting means, the inside of the amplitude converting means 20 corresponds to each symbol in FIG. 3, and each other symbol in FIG. 8 corresponds to each symbol in FIG. 7. The DLL shown in FIG. 8 has a configuration in which the amplitude converting means 10 shown in FIG. 7 is replaced with the amplitude converting means 20 shown in FIG. The internal configuration of the amplitude converting means 20 is the same as the internal configuration of the amplitude converting means 20 shown in FIG.

Next, the operation will be described. D shown in FIG.
LL operation The main operation is the same as the DLL operation shown in FIG. In the DLL shown in FIG. 7, the amplitude of the internal clock signal of the node 7b is converted by the amplitude converting means 10 and output to the node 7a. In the DLL shown in FIG. 8, the amplitude of the internal clock signal of the node 7b is converted into the amplitude converting means. It is converted by 20 and output to the node 7a. Also,
The operation of the amplitude converting means 20 is similar to that described in the second embodiment of FIG.

As described above, when the DLL shown in FIG. 8 is used, even if the external clock signal has a small amplitude, the internal clock signal for phase comparison is converted into a small amplitude so that the accurate phase of the internal clock signal can be obtained. It is fed back, the accurate phase difference can be detected, and the internal clock signal having the same phase as the external clock signal can be generated.

Incidentally, FIG. 1 described in the first and third embodiments
And FET 11 and FET of the amplitude converting means 10 shown in FIG.
12 may be replaced with a bipolar transistor. Similarly, FIG. 3 described in the second and fourth embodiments.
And the transistor array 21 of the amplitude converting means 20 shown in FIG.
Each of the n FETs and the FET 22 may be replaced with a bipolar transistor.

[0059]

According to the first aspect of the present invention, in the internal clock signal generation circuit (PLL) using the voltage controlled oscillation means, the internal clock signal is modeled to have a small amplitude similar to that of the external clock signal, thereby achieving accurate There is an effect that an internal clock signal can be obtained.

According to the second aspect of the present invention, in the internal clock signal generation circuit (DLL) using the voltage control delay means, the internal clock signal is modeled to have the same small amplitude as that of the external clock signal, so that the accurate internal clock signal is obtained. There is an effect that a signal can be obtained.

According to the third aspect of the present invention, in the internal clock signal generating circuit (PLL), the internal clock signal is converted into the same small amplitude as the external clock signal by using the first transistor and the second transistor. It has the effect that it can be modeled by clamping to.

According to claim 4 of the present invention, in the internal clock signal generation circuit (DLL), the internal clock signal is converted into a small amplitude similar to that of the external clock signal by using the first transistor and the second transistor. It has the effect that it can be modeled by clamping to.

According to claim 5 of the present invention, the internal clock signal is converted into a small amplitude similar to the external clock signal for modeling by selectively outputting the first voltage and the second voltage by the switch means. There is an effect that can be.

According to the sixth aspect of the present invention, since the first voltage can be generated by stepping down the power supply supplied to the internal clock signal generation circuit, the first voltage different from the power supply is used to generate the internal clock signal. The effect is that there is no need to supply from outside the circuit.

According to claim 7 of the present invention, there is an effect that the switch means can be easily constructed by using the inverter and the transistor.

[Brief description of drawings]

FIG. 1 is a block diagram of an internal clock signal generation circuit having a PLL configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an output buffer circuit of a GTL interface.

FIG. 3 is a block diagram of an internal clock signal generation circuit having a PLL configuration according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a general configuration of a DLL which is a basis of a third embodiment of the present invention.

FIG. 5 is a diagram showing a current mirror circuit.

FIG. 6 is a diagram showing an inverter array connected in multiple stages.

FIG. 7 is a block diagram of an internal clock signal generation circuit having a DLL configuration according to a third embodiment of the present invention.

FIG. 8 is a block diagram of an internal clock signal generation circuit having a DLL structure according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram of a configuration of a conventional PLL.

FIG. 10 is a diagram showing a circuit example of a phase detector.

FIG. 11 is a diagram showing a circuit example of a charge pump and a loop filter.

FIG. 12 is a diagram showing a current mirror circuit.

FIG. 13 is a diagram showing a ring oscillator circuit.

FIG. 14 is a schematic diagram of a general system using a GTL interface.

[Explanation of symbols]

1a, 1b input buffer, 2a, 2b clock buffer, 3 phase detector, 4 charge pump, 5 loop filter, 6a voltage controlled oscillator, 6b voltage controlled delay element, 7a, 7b, 7c, 7d node, 10
Amplitude conversion means, 11, 12 FETs, 21 transistor rows, 21n, 22 FETs, 23 inverters, 24
Resistance, 25 FET, 100 Phase comparison means, 101
Voltage controlled oscillation means, 102 Phase comparison means, 103
Voltage control delay means.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Konishi 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation ULS Development Laboratory

Claims (7)

[Claims] 1. An internal clock signal generation circuit using a phase locked loop for receiving an external clock signal having a relatively small amplitude and outputting an internal clock signal having a relatively large amplitude locked to the phase and frequency of the external clock signal. A voltage-controlled oscillator for generating and outputting the internal clock signal having a relatively large amplitude; and receiving the internal clock signal having a relatively large amplitude to reduce the amplitude of the internal clock signal having a relatively large amplitude. Amplitude conversion means for generating and outputting an internal clock signal having a relatively small amplitude which is equal to that of the external clock signal, and the external clock signal having a relatively small amplitude and the internal clock signal having a relatively small amplitude. And phase-comparing the relatively small amplitude external clock signal and the relatively small amplitude internal clock signal. A phase comparison means for controlling the voltage controlled oscillation means based on the phase comparison,
Internal clock signal generation circuit equipped with. 2. An internal clock signal generation circuit using a delay locked loop for receiving an external clock signal having a relatively small amplitude and outputting an internal clock signal having a relatively large amplitude locked to the phase and frequency of the external clock signal. A voltage control delay means for generating and outputting the internal clock signal having a relatively large amplitude; and receiving the internal clock signal having a relatively large amplitude, and reducing the amplitude of the internal clock signal having a relatively large amplitude. Amplitude conversion means for generating and outputting an internal clock signal having a relatively small amplitude which is equal to that of the external clock signal, and the external clock signal having a relatively small amplitude and the internal clock signal having a relatively small amplitude. Then, the phase ratio of the external clock signal having a relatively small amplitude and the internal clock signal having a relatively small amplitude is received. An internal clock signal generation circuit comprising: a phase comparison unit that controls the voltage control delay unit based on the phase comparison. 3. In the amplitude conversion means, a first current electrode is connected to a first power supply side, a control electrode is a first transistor for receiving a predetermined reference signal, and a first current electrode is the first transistor. Is connected to the second current electrode of the transistor, and the second current electrode is connected to the second power supply side,
The control electrode includes a second transistor that receives the reference signal, and the output of the voltage controlled oscillator is provided at a connection node between the second current electrode of the first transistor and the first current electrode of the second transistor. The internal clock signal generating circuit according to claim 1, wherein the input of the phase comparison means is connected to the input of the phase comparison means. 4. The amplitude converting means has a first current electrode connected to a first power source side, a control electrode being a first transistor for receiving a predetermined reference signal, and a first current electrode being the first transistor. Is connected to the second current electrode of the transistor, and the second current electrode is connected to the second power supply side,
The control electrode includes a second transistor that receives the reference signal, and the output of the voltage control delay unit is provided at a connection node between the second current electrode of the first transistor and the first current electrode of the second transistor. The internal clock signal generation circuit according to claim 2, wherein the input of the phase comparison means is connected to the input of the phase comparison means. 5. The amplitude converting means receives the first voltage, the second voltage, and the internal clock signal having the relatively large amplitude, and receives the relatively large amplitude. 3. A switch means for selectively switching the first voltage and the second voltage based on an internal clock signal to output the internal clock signal having a relatively small amplitude. Internal clock signal generator. 6. The means for applying the first voltage comprises a transistor array in which a plurality of transistors, each of which has one current electrode and one control electrode connected to each other, are connected in series, and one end of the transistor array is connected to a power supply. The first from the other end
6. The internal clock signal generating circuit according to claim 5, further comprising a power supply voltage step-down means for outputting the voltage. 7. The switch means includes an inverter receiving the internal clock signal having a relatively large amplitude, a first current electrode connected to the first voltage, and a second current electrode connected to the second voltage. 6. The internal clock signal generation circuit according to claim 5, further comprising a transistor connected to the control electrode, the control electrode receiving the output of the inverter.