JPH08293769A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit with which an output buffer circuit is formed for shortening rise time regardlessly of the drive ability of an output buffer. CONSTITUTION: This circuit is constituted as the output buffer circuit equipped with a pulse generating circuit 4 provided with a differentiation circuit 1, an inverter 2 and a PMOS transistor 3 and an output circuit 9 which is provided with a buffer 5, an inverter 6, an NMOS transistor 7 and 8 and forms a TTL interface buffer. Concerning such an output buffer circuit, a pulse signal 103 generated by the differentiation circuit 1 is outputted from the pulse generating circuit 4 while receiving the input of a rising signal 101, and a rise signal 104 having the same polarity as this rise signal 101 is outputted from the output circuit 9 similarly while receiving the input of the rise signal 101. Then, these pulse signal 103 and rise signal 104 are instantaneously combined and outputted at the output terminal of the output buffer circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit used as an output buffer.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit forming this type of output buffer, in order to cope with the high-speed operation required for the output signal output from the output buffer, the rise time of the output signal and As a method of shortening the fall time, generally, a method of increasing the driving capability of the output stage of the output buffer to shorten the rise time and the fall time is adopted.

[0003]

In the conventional semiconductor integrated circuit forming the output buffer described above, there is a method of improving the driving capability of the output buffer as a method of shortening the rise time and the fall time of the output signal. It is used. This results in an increase in the amount of output current in the output stage of the semiconductor integrated circuit forming the output buffer, which necessitates an increase in the transistor size of the semiconductor integrated circuit and increases its current consumption. There is a drawback that.

An object of the present invention is to form an output buffer capable of shortening the rise time and fall time of an output signal and suppressing the consumption current to a predetermined level, regardless of the driving capability of the output buffer. It is to realize a semiconductor integrated circuit.

[0005]

A semiconductor integrated circuit according to the present invention includes a pulse generation circuit which receives a predetermined rising input signal, generates a pulse signal corresponding to the rising timing of the rising input signal, and outputs the pulse signal. A pulse signal that is configured to include an output buffer that receives the rising input signal and functions as a buffer for the rising input signal, and that is output from the pulse generation circuit;
The output buffer circuit is formed as an output buffer circuit that combines the output signal of the output buffer with a predetermined output terminal and outputs the synthesized signal.

The pulse generating circuit differentiates the rising input signal and outputs a pulse signal, a first inverter that inputs the pulse signal, inverts the pulse signal, and outputs the pulse signal, and the source has a high potential. A drain transistor connected to a power source and connected to the output end, and a pulse signal output from the first inverter is input to the gate and output to the output end. A buffer for receiving and outputting the rising input signal; a drain connected to the high-potential power supply and a source connected to the output terminal for inputting an output signal of the buffer to a gate and outputting to the output terminal; N of 1
A MOS transistor, a second inverter that receives the rising input signal and inverts and outputs the signal, and a drain connected to the output terminal and a source connected to a low potential power source to output the output signal of the second inverter. A second NMOS transistor that inputs to the gate and outputs to the output terminal may be provided.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an output buffer circuit formed in an embodiment of the present invention. As shown in FIG. 1, the output buffer circuit in this embodiment is
A pulse generating circuit 4 including a differentiating circuit 1, an inverter 2 and a PMOS transistor 3, and an output circuit 9 including a buffer 5, an inverter 6, and NMOS transistors 7 and 8 to form a TTL interface buffer are configured. Further, FIG. 2 is a circuit diagram of the output buffer circuit 1
In the example, in response to the input of the rising signal 101,
A pulse signal 103 output from the pulse generation circuit 4,
5 is an operation timing chart showing a rising signal 104 output from the output circuit 9 and a rising output signal 105 generated by combining and adding the pulse signal 103 and the rising signal 104. FIG.

In FIG. 1, the rising signal 101 is
Differentiating circuit 1 included in pulse generating circuit 4 and output circuit 9
Is input to the buffer 5 and the inverter 6 included in. In the differentiating circuit 1, the rising edge of the rising signal 101 is differentiated to generate the pulse signal 102, which is inverted in the inverter 2 and input to the gate of the PMOS transistor 3. In the PMOS transistor 3,
The pulse signal is level-up, inverted, and output as the positive pulse signal 103. On the other hand, the output circuit 9
, The rising signal 101 is input to the gate of the NMOS transistor 7 via the buffer 5, and on the other hand, the rising signal 101 is inverted by the inverter 6
It is input to the gate of the MOS transistor 8. NMOS
The transistor 7 and the NMOS transistor 8 receive the positive-polarity rising signal output from the buffer 5 and the reverse-polarity rising signal output from the inverter 6, respectively, so that the NMOS transistor 7 becomes conductive and the NMOS transistor 8 becomes conductive. The non-conduction state is established, and the positive rising signal 104 is output from the output circuit 9. The pulse signal 103 output from the pulse generation circuit 4 and the rising signal 104 output from the output circuit 9 are instantaneously combined and added at the output end of the output buffer circuit, and as a result, the rising time is shortened. A rising output signal 105 is obtained.

As an example, NEC-issued "CMOS6 /
6A / 6V family CMOS gate array design edition ", if the load capacitance at the output end of the output buffer of this embodiment is 15 pF, the output circuit 9 forming the TTL interface buffer has a drive capacity of 9 mA. Yes,
When the driving capability of the PMOS transistor 3 included in the pulse generation circuit 4 is also 9 mA, as shown in FIG. 2, the rising signal 104 output from the output circuit 9 changes from 0.3V to 2.7V. The rise time until the level is raised is about 0.76 nsec (not shown), and the pulse signal 103 output from the PMOS transistor 3 has a peak value of 1.5 of the pulse signal.
The rising time to reach V is about 0.58 nsec as shown in FIG. The time required for the rising output signal 105 generated by combining the rising signal 104 and the pulse signal 103 to reach 2.7 V is about 0.48 nsec as shown in FIG. That is, the rising signal 104 and the pulse signal 10
As shown in FIG. 2, the rise time is about 0.3 from the output end of the output buffer circuit by the instant synthesis of 3.
The rising output signal 105 shortened by about 8 nsec is output.

[0011]

As described above, the present invention is applied to a semiconductor integrated circuit forming an output buffer circuit, and outputs an output signal corresponding to a predetermined rising signal input and the rising signal input. By instantaneously combining the pulse signal generated at the rising timing with the output terminal of the output buffer circuit, the rising time of the output signal is 50% regardless of the driving capability of the output stage.
The effect is that it can be shortened to some extent.

Further, since the rise time of the output signal is shortened regardless of the driving capability of the output stage of the output buffer circuit, the current consumption of the output buffer circuit is suppressed to a predetermined level. .

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an operation timing chart of input / output signals in the present embodiment.

[Explanation of symbols]

 1 Differentiation Circuit 2, 6 Inverter 3 PMOS Transistor 4 Pulse Generation Circuit 5 Buffer 7, 8 NMOS Transistor 9 Output Circuit 101 Rising Signal 102, 103 Pulse Signal 104 Rising Signal 105 Rising Output Signal

Claims (2)

[Claims] 1. A pulse generation circuit which receives a predetermined rising input signal and generates and outputs a pulse signal corresponding to the rising timing of the rising input signal, and the rising input signal which receives the rising input signal. And an output buffer functioning as a buffer for the output buffer circuit for forming a pulse signal output from the pulse generation circuit and an output signal of the output buffer at a predetermined output terminal and forming an output buffer circuit. And a semiconductor integrated circuit. 2. A differentiation circuit, wherein the pulse generation circuit differentiates the rising input signal and outputs a pulse signal,
A first inverter that inputs and inverts and outputs the pulse signal, and a pulse signal output from the first inverter, whose source is connected to a high-potential power supply and whose drain is connected to the output terminal, to the gate. A PMOS transistor for inputting and outputting to the output end, the output buffer receiving the rising input signal and outputting, and a drain connected to the high potential power supply and a source connected to the output end. First connected to input the output signal of the buffer to the gate and output to the output end
, An NMOS transistor, a second inverter that inputs and inverts and outputs the rising input signal, and a drain connected to the output terminal and a source connected to a low potential power source, and an output signal of the second inverter. 2. A semiconductor integrated circuit according to claim 1, further comprising: a second NMOS transistor which inputs to the gate and outputs to the output end.