JPH08293562A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: To provide a semiconductor memory device which is composed of new-type static random access memory cells lessened in occupation area and formed on a semiconductor substrate. CONSTITUTION: A word line WL of a memory cell is composed of a pair of first wirings (50a, 50b), and a power supply wiring VCC of the memory cell is composed of a pair of second wirings (56c, 56f). By this setup, a word line is divided as above, whereby a pair of transfer insulated gate field effect transistors (T3 , T4 ) and a pair of drive insulated gate field effect transistors (T1 , T2 ) are arranged adjacent to each other, a shared region (storage anode) of them is lessened in area, a power supply wiring can be arranged on the word lines as it is divided, and the memory cell is markedly lessened in area occupied by itself.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a static random access memory device having high integration, ultra low power consumption and high soft error resistance, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Insulated gate type field effect transistor (I
A conventional highly integrated static random access memory cell using a GFET (hereinafter abbreviated as the most general MOS transistor) crosses two driving MOS transistors (T1, T2) as shown in the equivalent circuit of FIG. A flip-flop circuit formed by connecting and a high resistance element for supplying a minute current to the storage nodes N1 and N2 for holding information connected to the two storage nodes N1 and N2 of the flip-flop circuit. Transfer MOS transistors (T) for performing "writing" and "reading" of information connected to R1 and R2 and the storage nodes N1 and N2.
3 and T4), the power supply voltage VCC and the ground potential are supplied to the flip-flop circuit, and the transfer M
The data lines 1 and 1'are connected to the OS transistor, and the common gate is the word line 2. As is well known, the operation of such a static random access memory cell activates a word line to transfer M.
Information of "High" or "Low" is stored in the storage nodes N1 and N2 from the data line through the OS transistor, or conversely, the state of the storage node is read.

FIG. 7 is a plan view of the prior art of the static random access memory cell described above, which is described, for example, in Nikkei Electronics magazine May 21, 1984, pages 181 to 199. Below, FIG.
The related art will be described in more detail with reference to.

In FIG. 7, gate electrodes 7c and 7d are gate electrodes of the driving MOS transistors T1 and T2,
The gate electrode 5a is a common gate electrode for the transfer MOS transistors T3 and T4. Driving MOS transistor T
The high-concentration n-type impurity region 3d to be the drain of 1 is common to the n-type impurity region of the transfer MOS transistor T3, and the high-concentration n-type impurity region 3e to be the drain of the driving MOS transistor T2 is the gate electrode 5b. Is electrically connected to the n-type impurity region 3c of the transfer MOS transistor T4, and the gate electrode 5c of the drive MOS transistor T2 is common to the transfer MOS transistor T3 and the drive MOS transistor T1.
To achieve cross-connection of the flip-flop circuits of the static random access memory cell.

Further, the contact holes 6 are formed in the gate electrodes 5b and 5c.
The high resistance polysilicon film 7 has holes a and 6b.
c and 7d are connected to the gate electrodes 5a and 5c through the low resistance polysilicon films 7a and 7b. Further, the low resistance polysilicon film 7e serves as a common power supply line connected to the high resistance polysilicon film.

The aluminum electrodes 9a and 9b are two data lines in the memory cell, and are electrically connected to the high concentration n-type impurity regions 3a and 3b of the transfer MOS transistors T4 and T3 through the connection holes 8a and 8b. Connected to each other. The problems of the conventional static memory cell are described.

Α-rays generated when a small amount of uranium (U) or thorium (Th) contained in a material such as a resin for sealing a memory chip or a wiring material such as aluminum collapses in the memory cell. When incident on the storage node portion in the "High" state, an electron-hole pair is generated along the range of the α-ray, and is attracted to the storage node by the electric field in the depletion layer to change the potential of the storage node. As a result, if the potential fluctuation has a sufficient value for flipping the flip-flop, the information in the memory is destroyed. This is a phenomenon called a soft error. The soft error can be reduced by increasing the accumulated charge amount of the storage node or by reducing the area of the pn junction formed in the storage node portion and decreasing the collected charge amount. it can. However, in order to reduce the area of the pn junction of the storage node portion in the conventional memory cell structure, there are the following problems.

(1) For example, the storage node formed of the drain region of the driving MOS transistor T1 shown in FIG. 7 will be described. In order to prevent the connection hole 4b from overlapping with the gate electrodes 5a and 5b due to mask misalignment or the like. It is necessary to have a margin, and moreover, the gate electrodes 5a and 5b
Since the gate electrode 5c must be connected to the high-concentration n-type impurity region 3a, the gate electrode 5a of the transfer MOS transistor T3 and the drive MOS transistor T1
The distance of the gate electrode 5b of the memory cell cannot be reduced to the minimum size that can be processed, and P- of the memory node portion of the memory cell is
This was an obstacle to the reduction of the N-junction area.

(2) In order to operate the memory cell stably when the power supply voltage is lowered, the ratio of the current drive capability of the drive MOS transistor and the transfer MOS transistor is set to 3
It is known that the above is effective. For this reason, conventionally, the channel width of the driving MOS transistor has been made three times or more larger than the channel width of the transfer MOS transistor. However, when the transfer MOS transistor and the drive MOS transistor are arranged close to each other as shown in FIG. 8, the distances a and b from the position where the channel width is changed to the respective gate electrodes 5d and 5e are shortened and the masking Since the channel widths w1 and w2 of the transfer and drive MOS transistors change due to the misalignment, the stability of the memory cell operation deteriorates. In particular, when the channel width ratio is large or when the photolithography technique using light is used, the actual pattern becomes ambiguous (having sharp corners and roundness) as shown in FIG. It becomes more and more prominent.

[0010]

A major problem in the conventional semiconductor memory device is that the memory cell occupies a large area.

An object of the present invention is to provide a semiconductor memory device in which a novel static random access memory cell having a small occupied area of the memory cell is formed on a semiconductor substrate.

Another object of the present invention is to provide a semiconductor memory in which a static random access memory cell, which is capable of stable memory cell operation by reducing the occupied area of the memory cell and increasing the capacity, is formed on a semiconductor substrate. To provide a device.

[0013]

According to one aspect of the present invention, a word line WL in a memory cell is composed of a pair of first wirings, and a power supply wiring Vcc in the memory cell is composed of a pair of second wirings. It

[0014]

By dividing the word line, the pair of insulated gate field effect transistors for transfer and the pair of insulated gate field effect transistors for driving are brought close to each other to reduce their shared region (storage node), and The power supply wiring can be separately arranged on each word line, and the occupied area of the memory cell can be significantly reduced.

[0015]

EXAMPLES The present invention will be described in more detail with reference to specific examples.

(Embodiment 1) FIGS. 1 to 3 are plan views of a static random access memory cell related to the present invention.

FIG. 1 shows an active region 10 of a plan view of a memory cell for 9 bits, a gate electrode 11 (of an insulated gate field effect transistor for driving), and a connection hole 14, and the gate electrode The active regions 10 other than 11 (specifically, the portion surrounded by the field oxide film as the insulating isolation region) are high-concentration n-type impurity regions.

2 and 3 show details of the 1-bit cell portion, and FIG. 4 shows an equivalent circuit thereof. Further, FIG. 5 shows a cross-sectional structure taken along the line AA ′ in FIGS. 2 and 3.

The present embodiment is a static random access memory including a flip-flop circuit composed of a pair of inverters using stacked complementary MOS transistors, and includes a driving MOS transistor and a transfer MOS transistor on a silicon substrate. Therefore, the area of the pn junction of the storage node is reduced, cross-connection of the flip-flop circuit is achieved by the second-layer polysilicon film, and the second-layer polysilicon film is laminated. PMO
It is used for the gate electrode of the S transistor.

FIG. 2 is a plan view showing n-channel driving MOS transistors, transfer MOS transistors, ground wirings, word lines and data lines.
Indicates the portion of the p-channel MOS transistor.

2 to 3 and 5, n-channel driving MOS transistors (T1, T2) and n
Channel transfer MOS transistors (T3, T4) are n
Is formed in a p-type well (p-type impurity island region) 22 formed in a type silicon substrate 21, and each of the gate electrodes 11a, 11b, 11c and 11d is n.
This is a first-layer polysilicon film to which a type impurity is added. Here, the driving MOS transistor T1 and the transfer M
OS transistor and driving MOS transistor T2
And the transfer MOS transistor T4 share the high-concentration n-type impurity regions 10b and 10d, respectively, and form storage nodes N1 and N2 of the memory cell shown in FIG. Here, in the high concentration n-type impurity region 10b, the pn junction area is reduced in a self-aligning manner by arranging the gate electrodes 11a and 11b close to each other. Similarly, the pn junction area is reduced in a self-aligning manner. Further, an insulating film 26 is formed on the gate electrodes 11a, 11b, 11c and 11d, and a spacer insulating film 25 is formed on the side wall of the gate electrode 11a, 11b, 11c, 11d. The polysilicon films 16a and 16b of the layer and the high-concentration n-type impurity regions 10b and 10d are the silicon oxide film 27,
And 28 are connected to the gate electrodes 11a, 11b, 11c and 11d so as to be insulated in a self-aligned manner. Further, the third polysilicon films 16a and 16b are the gate electrodes 11 of the other driving MOS transistors.
c and 11b are cross-connected through connection holes 15b and 15a, respectively. Further, at least a part of the third-layer polysilicon films 16a and 16b serve as the gate electrodes of the polysilicon PMOS transistors T7 and T8 shown in FIG. 4 formed by stacking, and at least the upper portion thereof. Is the polysilicon PMOS transistor T7,
A gate insulating film 29 of T8 is formed, and a fourth-layer polysilicon film which becomes the channel regions 18c and 18d of the polysilicon PMOS transistors T7 and T8 is formed at least on the gate insulating film 29. Therefore, the gate electrodes 16a and 16b of the stacked polysilicon PMOS transistors T7 and T8 are located below the channel regions 18c and 18d.

Further, the drain regions 18a and 18b of the polysilicon PMOS transistors T7 and T8 are formed in the same layer as the channel regions 18c and 18d, that is, in the fourth-layer polysilicon film, and their drains are formed. The regions 18a and 18b are connected to the other polysilicon P of the flip-flop circuit via the connection holes 17b and 17a.
It is connected to the gate electrodes 16b and 16a of the MOS transistors, and cross connections of flip-flop circuits are formed.

On the other hand, the above-mentioned laminated polysilicon PM
Like the channel regions 18c and 13d, the common source region 18e of the OS transistors T7 and T8 is formed in the polysilicon film of the fourth layer and serves as a common power supply wiring in the memory. A constant voltage is supplied to the source of the polysilicon PMOS transistor. The high-concentration n-type impurity region 10c is a common source region of the driving MOS transistors T1 and T2, and the connection hole 14
Similarly to a and 14b, the gate electrodes 11b and 11c are insulated from the gate electrodes 11b and 11c in a self-aligned manner by the insulating film 26 on the gate electrodes 11b and 11c and the spacer insulating film 25 on the side wall.
A ground wiring 13a made of a second-layer polysilicon film is connected to the high-concentration n-type impurity region 10c via a connection hole 12a, and the source potentials of all the driving MOS transistors in the memory are grounded by the ground wiring. It is fixed at the electric potential.

Transfer MOS transistors T3 and T4
Each of the gate electrodes 11a and 11d becomes a word line, and the high concentration n-type impurity regions 10a and 10 which are active regions are formed.
e is a silicon oxide film 27, 28 and polysilicon P
Aluminum electrodes 20a and 20b to be the data lines 1 and 1'of the memory cell are connected through connection holes 19a and 19b formed on the gate insulating film 29 of the MOS transistor.

The driving MOS transistor T is
The gate electrodes 11a, 11b, 11c, and 11d of T1 and T2 are polysilicon films to which n-type impurities are added, but in order to reduce the signal delay of the word line, low resistance such as tungsten, molybdenum, and titanium is used. It may be a melting point metal, or a compound of these refractory metal and silicon (silicide) or a composite film of polysilicon and silicide (polycide). Here, it is preferable that n-type impurities are added to the gate electrodes 16b and 11c at a high concentration, and at least the third-layer polysilicon films 16a and 16b connected to these gate electrodes are n-type. It is preferable that the impurity of (3) is added at a high concentration. Further, the third-layer polysilicon films 16a and 16b do not necessarily have to be polysilicon, and like the above gate electrode, a low-melting point refractory metal, a compound of high-melting point metal and silicon (silicide), or polysilicon and silicide. The composite film (polycide) or the like may be used. Further, the third-layer polysilicon films 16a and 16b
In addition, for example, a titanium nitride film (T
iN) or a composite film thereof, the gate electrode 11
It is not always necessary to add n-type impurities to b and 11c at a high concentration, and p-type impurities may be added.

The complementary MOS (CMO) described above is used.
S) In the structure of a static random access memory cell having a transistor, as is well known, the equivalent circuit shown in FIG. 4 is formed, and pn junctions D1 and D2 with a large leak current are formed. It doesn't matter.

Next, the manufacturing process of this embodiment will be described with reference to FIGS.

10 to 16 are cross-sectional views of each manufacturing process of the static random access memory cell according to this embodiment, which are taken along the line A- in the plan views of FIGS.
The cross section along line A'is shown. In this embodiment, all MOS transistors formed on the surface of the silicon substrate used for the memory cell are n-channel MO in the p-type well 22.
It is an S transistor, and a complementary MOS (CMOS) circuit using a double well is used as a memory peripheral circuit.

However, a single structure of p-type well or N-type well may be used, and a well of the same conductivity type as the substrate may be another well of the opposite conductivity type so that a plurality of power supply voltages can be supplied to the memory peripheral circuit. There may be three or more types of well structures surrounded by and electrically isolated from the substrate. The conductivity type of the silicon substrate may be either n-type or p-type.

Further, in the present embodiment, only the manufacturing process of the memory cell portion will be described, but a known technique can be used for the manufacturing method of the peripheral CMOS circuit.

First, an impurity concentration of 1016 to 1017 cm ~ 3, is applied to the n-type silicon substrate 21 having a specific resistance of about 10 Ωcm by a known method such as ion implantation of boron and thermal diffusion.
After forming a p-type well 22 having a depth of 2 to 3 μm, a p-type channel stopper layer and a silicon oxide film (field oxide film) 23 having a thickness of 300 to 500 nm for element isolation are formed by a selective oxidation method. The gate oxide film 24 having a thickness of 5 to 20 nm is formed in the active region of the MOS transistor.
To form. Here, when forming the field oxide film 23, a channel stopper layer for preventing N inversion is usually formed under the field oxide film in the p-type well 22, but a drawing omitting it is used here. Further, the impurity concentration distribution in the well may be such that the impurity concentration increases in the depth direction, and in this case, the ion implantation energies for forming the p-well have a plurality of types [FIG. 10].

Next, after performing ion implantation for adjusting the threshold voltage of the MOS transistor, the 200 nm-thickness polysilicon film 11 is subjected to low pressure chemical vapor deposition (LPCVD).
Method) and n-type impurities such as phosphorus are introduced by vapor phase diffusion, followed by insulating film 2 such as a silicon nitride film.
6 is deposited to a thickness of 200 nm by the LPCVD method, and the insulating film 2 is formed by photolithography and dry etching.
6 and the polysilicon film 11 are processed into a pattern of gate electrodes 11a to 11d, and using these gate electrodes as a mask for ion implantation, an implantation amount of about 10 ¹⁵ / cm ² is used to implant n-type impurity ions such as arsenic. Do 90
By annealing in a nitriding atmosphere at 0 ° C, the depth of
High concentration n-type impurity regions 10a to 10e of 1 to 0.2 μm
To form. Here, it is desirable that the thickness of the gate electrodes 11a to 11d and the insulating film 26 such as a silicon nitride film formed on the gate electrodes 11a to 11d is set to an optimum thickness according to the processing dimensions and the dry etching conditions. The insulating film 26 may be a silicon oxide film, but an insulating film such as a tantalum oxide film (Ta2O5) having a smaller dry etching rate than other silicon oxide films is suitable. Further, the impurity addition to the polysilicon of the gate electrode may be carried out by an ion implantation method or a method of introducing it at the time of forming the polysilicon film [FIG.
1].

Next, after depositing a silicon oxide film having a thickness of 200 to 400 nm by the LPCVD method, the spacer insulating film 2 is formed on the sidewalls of the etching gate electrodes 11a to 11d by dry etching by anisotropic dry etching.
5 is formed, and then the silicon oxide film 2 having a thickness of 100 nm is formed.
7 was deposited by the LPCVD method, and although not shown in the cross-sectional view, contact holes [12 in FIG.
a] is opened by photolithography and dry etching, then a second-layer polysilicon film 13a having a thickness of 100 nm is deposited, and an n-type impurity such as arsenic is ion-implanted at 10 ¹⁹ to 10 ²⁰ / cm ^3. Then, the ground wiring 13a is patterned by photolithography and dry etching. Here, the spacer insulating film 25 may be a silicon oxide film or another insulating film like the insulating film 26. When the connection hole 12a is opened, the spacer insulating film 25, is formed on the sidewalls of the gate electrodes 11b, 11c.
Since the insulating film 26 is provided on the upper portion, the gate electrodes 11b and 11c can be insulated in a self-aligned manner with respect to the connection holes by adjusting the dry etching conditions appropriately.
In that case, since the connection hole 12a and the gate electrodes 11b and 11c can be arranged close to each other, the memory cell area can be reduced. The ground wiring 13a is preferably made of a low resistance material such as a tungsten silicide film or a polycide film [FIG. 12].

Next, a silicon oxide film 28 is deposited to a thickness of 100 nm by the LPCVD method, and the connection hole 14 is formed on the silicon oxide films 27 and 28 on the high concentration n-type impurity region 10d.
The opening b is opened by using photolithography and dry etching. At this time, since the spacer insulating film 25 is provided on the side walls of the gate electrodes 11c and 11d and the insulating film 26 is provided on the upper side, the gate electrodes 11c and 11d are self-assembled with respect to the connection hole 14b by adjusting the dry etching conditions appropriately. It can be insulated in a consistent manner [Fig. 13].

Next, a contact hole 15a is formed in the insulating film 26 and the silicon oxide films 27 and 28 on the gate electrode 11b by photolithography and dry etching, and the LPC is formed.
Third-layer polysilicon film 1 of 100 nm thickness using VD
After depositing 6b, the third layer polysilicon film 1 is formed by ion implantation of arsenic at 80 KeV and 5 × 10 ¹⁵ / cm ² .
After n-type impurities are added to 6b and activated by a predetermined annealing, it is processed into a desired shape by photolithography and dry etching. Here, it is preferable that a thin silicon oxide film is formed on the polysilicon film 16b during the ion implantation. In addition, the polysilicon film 16
Depending on the thickness of b, it is preferable that the amount of ion implantation and the energy are optimized. The connection hole 14b opened in the previous step [FIG. 13] and the connection hole 15a opened in this step may be formed by the same photolithography and dry etching. In that case, the number of manufacturing steps can be reduced [FIG. 14].

Further, an insulating film 29 such as a silicon oxide film
Is deposited to a thickness of 10 to 50 nm by the LPCVD method,
Annealing is performed at 900 ° C. for about 10 minutes in a nitrogen atmosphere. Subsequently, the connection holes 17a and 17b shown in FIG. 3 are opened in the insulating film 29 by photolithography and dry etching, and the thickness is 10 to 50 nm by the LPCVD method.
The fourth-layer polysilicon film 18 is deposited, and then processed into a desired shape by photolithography and dry etching. Next, a silicon oxide film having a thickness of 5 nm is formed on the polysilicon film 18, and then the channel region 18 of the polysilicon PMOS transistor is formed by photolithography.
A photoresist is formed on the area to be d, and the implantation energy is set to 25 using the photoresist as a mask for ion implantation.
After removing the photoresist by performing ion implantation of BF2 ions with keV and an implantation amount of 10 ¹⁴ to 10 ¹⁵ / cm ² ,
Annealing is performed in a nitrogen atmosphere at 850 ° C. for about 10 minutes to activate the impurity ions, and the source, drain, and channel regions 18e, 18 of the polysilicon PMOS transistor are activated.
a and 18d are formed respectively. Here, the gate insulating film 29 of the polysilicon PMOS transistor may be formed by oxidizing the polysilicon film 16b, or may be formed by using a silicon nitride film, a composite film of a silicon nitride film and a silicon oxide film, or other silicon oxide film having a relative dielectric constant. An insulating film having a high rate can also be used. Furthermore, the ion implantation for forming the source, drain, and channel regions of the polysilicon PMOS transistor may be performed before patterning the fourth-layer polysilicon film. In addition, polysilicon P
It suffices that the gate insulating film 29 of the MOS transistor be at least under the fourth-layer polysilicon films 18a, 18d, 18e, and the insulating film 29 other than under the fourth-layer polysilicon film is etched as shown in FIG. You can remove it. Further, the ion implantation of BF2 for forming the source and drain regions of the polysilicon PMOS transistor may be 10 ¹⁴ / cm ² or less in order to reduce the leak current between the source and drain. In this case, in order to reduce the resistance of the source and drain, it is preferable that the ion-implanted portion be a silicide layer using a refractory metal such as tungsten.

Next, a composite silicon oxide film 30 of a silicon oxide film having a thickness of 100 nm and a silicon oxide film having a thickness of 300 nm, for example, containing phosphorus is deposited to alleviate the step in the memory cell, and the connection hole 19b is formed. After opening, an aluminum film is deposited to a thickness of about 1 μm by sputtering, and an aluminum electrode 206 is formed by photolithography and dry etching.
Is processed into a pattern [Fig. 15]. After that, a normal passivation process and a packaging process are performed to complete the process. As the electrode wiring material, tungsten or the like may be used.

Embodiment 2 This embodiment relates to a method of increasing the area of the ground wiring in a self-aligning manner in the static random access memory cell in Embodiment 1. 18 and 19 are plan views showing a static random access memory cell according to this embodiment, which correspond to FIGS. 1 and 2, respectively. Further, FIG. 20 is A- of FIG. 18 and FIG.
It is a figure which shows the cross-section in the A'line. 18 and 20, the high-concentration n-type impurity region 10 forming the storage node of the flip-flop circuit of the memory cell.
b and 10d are connected to the third-layer polysilicon films 16a and 16b which are insulated in a self-aligned manner from the second-layer polysilicon film 13b which is the ground wiring. Therefore, the polysilicon film 13b of the second layer is formed of the contact holes 14a,
Since they can be arranged independently of the positions of 14b and 15a, 15b, the area of the contact wiring can be increased. Further, this embodiment will be described in detail with reference to FIGS. 21 to 25.

21 to 25 are sectional views showing a manufacturing process of a portion in which the second and third polysilicon films are insulated in a self-aligned manner.

First, the steps up to forming the n-channel MOS transistor and the ground wiring 13b on the n-type silicon substrate 21 are carried out except that the pattern shape of the ground wiring, that is, the second-layer polysilicon film is different. This is exactly the same as FIGS. 10 to 16 of Example 1 [FIG. 21].

Next, a thickness of 100 n is obtained by using the LPCVD method.
m silicon oxide film 28 is deposited, and then the high concentration n-type impurity region 10 is formed by photolithography and dry etching.
silicon oxide film 27 on d, second-layer polysilicon film,
The connection hole 14b is opened in the silicon oxide film 28 [FIG.
2].

Next, an insulating film 31 such as a silicon nitride film is deposited by LPCVD to a thickness of 50 nm. Here, the thickness of the insulating film 31 depends on the diameter of the connection hole 14b and the insulating film 2.
6. An appropriate value may be selected within the range of 10 nm to 100 nm according to the thickness of the silicon oxide film 28 and the dry etching conditions. Alternatively, the insulating film 31 may be a silicon oxide film, a composite film of a silicon oxide film and a silicon nitride film, or the like [FIG. 23].

Then, the insulating film 31 on the bottom surface of the connection hole 14b and the portion other than the connection hole 14b is etched by dry etching having strong anisotropy such as reactive ion etching, and only the side wall of the opened connection hole 14b is etched. Then, the insulating film 31 is left, and the second layer polysilicon film 13b is insulated in a self-aligned manner (FIG. 24).

Next, the steps after the step of forming the third layer polysilicon [FIG. 25] may be exactly the same as in the first embodiment.

According to this embodiment, the second-layer polysilicon film, which serves as the ground wiring, and the third-layer polysilicon film, which serves as the gate electrode of the polysilicon PMOS transistor and the wiring at the cross connection, are contacted in a self-aligned manner. Since it is cut off, the area of the overlapping portion of the second-layer polysilicon film 13b and the third-layer polysilicon film 16b can be effectively increased, so that the storage node and the ground as shown in FIG. Capacitance elements c1 and c2 having a large capacitance value can be formed at the potential, and the soft error rate of a fine static random access memory can be reduced. Further, the gate electrode 11c of the driving MOS transistor and the second-layer polysilicon film 1
The area of the overlapping portion of 3b can be increased, and the capacitive elements c3 and c4 as shown in the figure can be formed.
Similar to 1 and c2, the soft error rate of the fine static random access memory can be reduced. The capacitance values of the capacitors c1, c2, c3, and c4 are the same as those of the insulating film 2
If a material having a larger relative dielectric constant than that of the silicon oxide film is used for 6, 31 and the silicon oxide film 28, the capacitance value can be further increased without increasing the memory cell area. Examples of the material include a tantalum oxide film which is a composite film of a silicon oxide film and a silicon oxide film in addition to the silicon nitride film.

Further, according to the present embodiment, the wiring width of the ground wiring 13b can be widened without increasing the memory cell area, so that the driving MO in the memory cell shown in FIG.
In supplying the ground potential to the source of the S transistor,
Even if a large current flows through the memory cell, the ground potential supplied to the memory cell can be stabilized, and the memory cell can be prevented from malfunctioning due to the influence of noise or the like mixed in the power supply wiring due to the decrease in the power supply voltage.

The ground wiring method according to this embodiment can be applied to other embodiments having a ground wiring structure using polysilicon.

Embodiment 3 This embodiment relates to the static random access memory cell in Embodiment 1 in which a high concentration n-type impurity region is used for the ground wiring. 27 to 28 are views showing the planar structure of the static random access memory cell according to the present embodiment, and like the first embodiment, FIG. 27 shows the driving and transfer MOS transistors, the ground wiring, and the data section. FIG. 28 shows a part of a polysilicon PMOS transistor. Further, FIG. 29 is a diagram showing a cross-sectional structure taken along the line AA ′ in FIGS. 27 and 28. 27 and 29, the high-concentration n-type impurity region 10c 'is a common source of the two drive MOS transistors T1 and T2 in the memory cell and is also used as a common ground wiring in the memory. The ground potential is supplied to the source of the drive MOS transistor of each memory cell. Further, the high-concentration n-type impurity regions 10b, 1 forming the storage node of the flip-flop circuit of the memory cell
0d is formed in a minute area as in the first embodiment,
A connection hole 1 is formed on the high concentration n-type impurity regions 10b and 10d.
4a 'and 14b' are opened and the second-layer polysilicon films 32a 'and 32b are connected to serve as the gate electrodes of the polysilicon PMOS transistors T6 and T5, respectively. Silicon film 32a,
The reference numeral 32b is connected to the gate electrodes 11c and 11b of the other driving MOS transistor of the flip-flop circuit through the connection holes 15b 'and 15a' to achieve cross connection. Further, the second-layer polysilicon film 32a,
Connection holes 33a and 33b are opened in 32b, and third-layer polysilicon films 34b and 34a, which are the drain regions of the polysilicon PMOS transistors T5 and T6, are connected, respectively, to achieve cross-connection of flip-flop circuits. ing. Further, the third-layer polysilicon film 34e, which is a common source region of the polysilicon PMOS transistors T5 and T6, is a common power supply line for each memory cell.
Third layer polysilicon film 3 to be the channel region of 5, T6
4c and 34d are second-layer polysilicon films 32, respectively.
An insulating film 29 'is sandwiched between a and 32b.
Incidentally, as in this embodiment, the high concentration n-type impurity region 10c 'is formed.
When using as a ground wiring, the resistance of the ground wiring can be made sufficiently small by forming the silicide layer 35 of a refractory metal such as tungsten or titanium in a part of the high concentration n-type impurity region 10 ', and the resistance of the memory cell can be reduced. Malfunction can be prevented.

According to the present invention, the number of layers of the polysilicon film can be reduced, and therefore, the steps of the memory cell can be reduced, so that the number of manufacturing steps can be reduced and the manufacturing yield can be improved.

Embodiment 4 This embodiment is a static random access memory cell in Embodiment 1, and is a well-known LDD (Lighly Doped) for a channel MOS transistor formed on a silicon substrate.
Drain) structure. FIG. 30 is a view showing the cross-sectional structure of the static random access memory cell according to this embodiment. In FIG. 30, low-concentration n-type impurity regions 36 of 10 ¹⁷ to 10 ¹⁹ / cm ² are formed in a self-aligned manner at the source and drain ends of the n-channel MOS transistor formed on the surface of the silicon substrate 21.
That is, the high concentration n-type impurity regions 10c, 10d,
10e is formed so that the area of the PN junction becomes minute in a self-aligning manner using the spacer insulating film 25 as a mask for ion implantation. A publicly known method can be used for manufacturing the MOS transistor having the LDD structure. It is not always necessary to form the low concentration n-type impurity region in the source region of the driving MOS transistor.

According to this embodiment, the long-term fluctuation of the performance of the n-channel MOS transistor formed on the surface of the silicon substrate can be reduced, and malfunction of the static random access memory device can be prevented.

This embodiment can be applied to all insulated gate field effect transistors formed on the silicon substrate of other embodiments.

Fifth Embodiment This embodiment relates to a method of arranging a drive MOS transistor and a transfer MOS transistor in the static random access memory cell of the first embodiment. 31 to 32 are views showing the planar structure of the static random access memory cell according to the present embodiment. As with the first embodiment, FIG. 31 shows the drive and transfer MO cells.
The S transistor, the ground wiring, and the data line are shown, and FIG. 32 shows the polysilicon PMOS transistor. 31 and 32, the connection holes 41a and 41 are formed in the high-concentration n-type impurity regions 37b and 37e forming the storage node of the flip-flop circuit of the memory cell.
The third-layer polysilicon films 42a and 42b are connected to each other via b, and the third-layer polysilicon films 42a and 42b are connected.
42b also operates as the gate electrodes of the polysilicon PMOS transistors T6 and T5, and is further connected to the gate electrodes 38b and 38d of the driving MOS transistors T2 and T1 through the connection holes 41c and 41d, respectively, to cross-connect the flip-flop circuit. Is forming. Here, the connection hole 41a
And 41c and 41b and 41d are opened in the same process, but the connection holes 41a and 41b may be opened in the same process, and the connection holes 41c and 41d may be opened in a different process, as in the first embodiment. Further, the connection holes 41a and 41c and the connection hole 41b
And 41d may each be opened by a single connection hole. Further, the connection hole 3 is formed in the high-concentration n-type impurity regions 37c and 37f which are the source regions of the driving MOS transistors T1 and T2.
Second polysilicon film 40a through 9b and 39a
The second-layer polysilicon film 40a serves as a connection wiring in the memory and supplies the ground potential to the source of the driving MOS transistor of each memory cell.

According to this embodiment, since the channel width of the driving MOS transistor can be made sufficiently wider than the channel width of the transfer MOS transistor, the range of the power supply voltage operating as the static random access memory device is wide. Therefore, it is possible to prevent the memory from malfunctioning even when the power supply voltage drops.

Embodiment 6 This embodiment relates to a method of reducing the pn junction area of the storage node of the flip-flop circuit of the memory cell in the static random access memory cell in Embodiment 5. FIG. 33 is a view showing the cross-sectional structure of the static random access memory cell according to this embodiment. In FIG. 33, a silicon oxide 47 is formed under the high-concentration n-type impurity region 37b forming the storage node of the flip-flop circuit of the memory cell, and the pn formed by the high-concentration n-type impurity region 37b is formed. The junction is only on the side surface of the high-concentration n-type impurity region 37b.

The method of forming the above-mentioned silicon oxide 47 is carried out with oxygen at a doping amount of, for example, 10 ¹⁸ / cm ^{2 so that} the range of ion implantation is 0.2 to 0.3 μm from the surface of the silicon substrate. This can be achieved by performing ion implantation only on the portion that becomes the storage node and performing annealing at 1100 ° C. for 2 hours in a nitriding atmosphere. The silicon oxide 47 region may be formed over the entire memory region or may be formed over the entire memory region and peripheral circuit region. The silicon oxide 47 is preferably formed before forming the MOS transistor.

According to this embodiment, since the pn junction area of the storage node of the flip-flop circuit of the memory cell is extremely small, the amount of electron-hole pairs generated by the irradiation of α-rays is reduced and the soft error is reduced. It is possible to realize a highly integrated, low power consumption static random access memory that has extremely high tolerance and does not malfunction even when the power supply voltage drops.

Embodiment 7 This embodiment relates to the static random access memory cell in Embodiment 1 in which the gate electrode of the driving MOS transistor and the gate electrode of the transmission MOS transistor are formed in different layers. 34 and 35 are views showing a planar structure of the static random access memory cell according to the present embodiment, and FIG. 36 is a view showing a sectional structure of AA ′ shown in the planar structure diagrams of FIGS. 34 to 35. Is. 34 and 36, the gate electrodes 49a and 49b of the drive MOS transistors T1 and T2 are the first-layer polysilicon film, and the transfer MOS transistor T
The gate electrodes 50a and 50b of T3 and T4 are polysilicon films of the second layer. The third-layer polysilicon film serves as the ground wiring 52a, and the fourth-layer n-type polysilicon films 54a and 54b are the gate electrode of the polysilicon PMOS transistor and the gate electrode 49.
a and 49b and the high concentration n-type impurity regions 48b and 48e are cross-connected by connection holes 53a and 53b, respectively. Further, the train regions 56a and 56d of the polysilicon PMOS transistor and the channel regions 56b,
56e and the source regions 56c and 56f are the polysilicon film of the fifth layer,
a and 56d are connection holes 55a and 55b in the other gate electrodes 54b and 54a made of the fourth layer polysilicon film.
Are cross-connected through. Also, polysilicon PM
The source regions 56c and 56f of the OS transistor are independent power supply lines.

When the number of layers of the polysilicon film is large as in this embodiment, the step difference of the memory cell increases, so that the connection between the aluminum electrodes 58a and 58b and the high-concentration n-type impurity regions 48a and 48b. A tungsten plug may be used for this. The low resistance material described in the first embodiment is preferable for the gate electrode of the transfer MOS transistor. Further, in this embodiment, the gate electrode of the driving MOS transistor is formed of the first-layer polysilicon film and the gate electrode of the transfer MOS transistor is formed of the second-layer polysilicon film. It is also possible to form the electrode by the first layer polysilicon and form the gate electrode of the driving MOS transistor by the second layer polysilicon film.

According to this embodiment, since the transfer MOS transistor and the drive MOS transistor can be arranged close to each other, the memory cell area can be reduced.

Embodiment 8 This embodiment relates to a method of reducing the resistance of the ground wiring in the static random access memory cell in Embodiment 7. 37 to 38 are views showing a planar structure of a static random access memory cell according to the present invention. 37 to 38, the drive MO
Connection holes 57c and 57d are formed in the n-type fifth layer polysilicon films 61a and 61b through the connection holes 51a and 51b in the high-concentration n-type impurity regions 48c and 48f which are the source regions of the S transistors T1 and T2. The first-layer aluminum electrode 62b is connected to the ground electrode via the ground electrode. On the other hand, the data lines are connected holes 57a, 57b, 63a, 63.
b, the second-layer aluminum electrodes 64a and 64b are formed via the first-layer aluminum electrodes 62a and 62b. The gate electrodes 54a 'and 54b' of the polysilicon PMOS transistor are formed on the third-layer polysilicon film as source regions 56c ', 56f', channel regions 56b, 56e 'and drain regions 56a', 5 '.
6d 'is formed of the fourth layer polysilicon film.

According to this embodiment, since the resistance of the ground wiring can be reduced, it is possible to prevent malfunction of the static random access memory device.

Example 9 This example is a static random access memory cell in Example 7 and relates to the structure of the ground wiring. FIG. 30 is a sectional view of a static random access memory cell according to the present invention. In the figure, the p-type well 22 is formed in the n-type well 66 in the p-type silicon substrate 65, and the p-type well 22 is electrically separated from the p-type silicon substrate 65. Further, the ground potential is supplied to the n-type well 66, and the driving MO
High-concentration n-type impurity region 4 serving as the source of the S transistor
8c is connected to the n-type well 66 through the n-type polysilicon 67 embedded in the groove whose side wall is insulated by the insulating film 68.

According to this embodiment, since the step difference of the memory cell can be reduced, the manufacturing yield by photolithography is improved. The end of the n-type well in the memory cell is shown in FIG.
It is preferable to use the twin well n-type well 69 used for the peripheral circuit such as 0.

The structure of grounding described in this embodiment can be applied to other embodiments.

Embodiment 10 This embodiment relates to the static random access memory cell in Embodiment 1 and relates to the structure of the connection portion of the data line. FIG. 41 is a diagram showing the cross-sectional structure of the static random access memory cell according to the present embodiment. In FIG. 41, the second-layer polysilicon film 13 is formed in the high-concentration n-type impurity region 10e of the transfer MOS transistor.
c is connected, and further, an aluminum electrode to be a data line is connected to the second-layer polysilicon film.

According to this embodiment, since the depth of the connection hole for the aluminum electrode of the data line can be left and the connection hole can be arranged on the gate electrode 11d, the memory cell integration can be achieved. You can increase the degree.

The aluminum wiring method described in this embodiment can be applied to other embodiments.

Embodiment 11 This embodiment relates to a method of reducing the parasitic capacitance of the data line in the static random access memory cell in Embodiment 1.

FIG. 42 is a view showing the sectional structure of the static random access memory cell according to this embodiment.
In FIG. 42, the first-layer aluminum electrode 20b 'is connected to the second-layer polysilicon film 13c connected to the high-concentration n-type impurity region 10e, and the second-layer aluminum electrode 71b to be a data line is further formed. Are connected.

According to this embodiment, the parasitic capacitance can be reduced because the thickness of the silicon oxide film 70 between the layers below the second layer aluminum electrode, which will be the data line, is large, and the memory device can operate at high speed. Become.

The aluminum wiring method described in this embodiment can be applied to other embodiments.

[Embodiment 12] This embodiment relates to a method of increasing the current drive capability of a polysilicon PMOS transistor in the static random access memory cell in Embodiment 1. FIG. 43 is a diagram showing the cross-sectional structure of the static random access memory cell according to the present embodiment. In FIG. 43, the thickness of the channel region 72d polysilicon film of the polysilicon PMOS transistor is in the range of 1 to 30 nm. In this case, since the source region 72d serves as a wiring for supplying a common power supply voltage, in order to prevent a decrease in potential supplied to each memory cell due to an increase in resistance value, the thickness of the polysilicon film in the source region 72d is at least the channel. It should be thicker than the region 72d. The source region 72e may be formed of a two-layer polysilicon film. Further, as shown in FIG. 44, a silicide layer 25 of a refractory metal such as tung ten may be formed on the polysilicon film 72e in the source region.

According to this embodiment, in the complementary MOS inverter used in the flip-flop circuit of the static random access memory cell, the current driving capability is increased due to the thinning effect of the channel portion of the polysilicon PMOS transistor. Moreover, the operation of the memory cell becomes stable, and the malfunction of the static type random access memory device can be prevented.

The polysilicon PM described in this embodiment is used.
The structure of the OS transistor is the polysilicon P of the other embodiment.
It can be applied to all MOS transistors.

Embodiment 13 This embodiment relates to another method for increasing the current driving capability of the polysilicon PMOS transistor of Embodiment 12. FIG. 45 is a diagram showing a sectional structure of a static random access memory cell according to the present invention.
In FIG. 45, the gate insulating film 29 of the polysilicon PMOS transistor is thinner in the channel portion than in other portions. The thin portion of the insulating film 29 has a thickness of 5 to 10 nm.

According to the present embodiment, the current driving capability can be increased by the thinning effect of the gate insulating film of the polysilicon PMOS transistor while reducing the leak current that normally occurs at the drain end in the polysilicon transistor. It is possible to provide a static random access memory with low power consumption and no malfunction. The structure of the polysilicon PMOS transistor of this embodiment can be applied to all the polysilicon PMOS transistors of other embodiments.

Embodiment 14 This embodiment relates to the static random access memory cell in Embodiment 1 in which high resistance polysilicon is used as a load element. 46 to 47 are views showing the planar structure of the static random access memory cell according to the embodiment, and the equivalent circuit diagram thereof is the same as the equivalent circuit diagram shown in FIG. 46 to 47,
The wiring for supplying the power supply voltage to the memory cell is the fourth-layer polysilicon film 144e to which arsenic is added, and the fourth-layer polysilicon film 144e further includes a fourth-layer polysilicon which is a high-resistance polysilicon. Eye polysilicon 144b, 144
d is connected, and the fourth layer of low resistance polysilicon 1
44a and 144c and connection holes 43b and 43a, respectively, are connected to the third layer polysilicon films 142b and 142a, which are storage nodes, and a minute current is supplied from the power supply voltage to the storage node of each memory cell. ing. In order to reduce the electric field effect on the high resistance polysilicon, the film thickness of the third and fourth polysilicon films is 1
It is preferable that the thickness is 00 nm or more. According to this embodiment, a highly integrated static random access memory can be provided.

Embodiment 15 This embodiment relates to a static random access memory cell in Embodiment 1 and a method for forming a pm junction in a storage node portion. 48 to 50 are cross-sectional views showing the manufacturing process of the storage node portion of this embodiment, and the process until the gate electrodes 11c and 11d of the MOS transistor are formed is the same as that of the first embodiment. Gate electrode 11c, 1
After processing 1d, a photoresist 74 is formed in a portion to be a storage node portion, and 10 ¹⁵ / c is formed in the same manner as the step of forming a normal high concentration n-type impurity region in a portion other than the storage node portion.
After implanting n-type impurity ions such as arsenic with a dose of about m ² and removing the photoresist 74, 9
By annealing in a nitrogen atmosphere at 00 ° C., the high concentration n-type impurity regions 10a to 10 having a depth of 0.1 to 0.2 μm are formed.
e is formed (FIG. 48).

Next, a silicon oxide film having a thickness of 200 to 400 nm is deposited by the LPCVD method and then etched by anisotropic dry etching to form the gate electrode 1.
A spacer insulating film 25 is formed on the side walls of 1c and 11d [FIG. 49].

After that, the third-layer polysilicon film 16b is formed.
The steps up to dry etching are the same as those of the first embodiment shown in FIGS. 12 to 14, and the third layer polysilicon film is deposited or processed after the third layer polysilicon film 16b is deposited. From the film 16b to the n-type impurity, the p-type well 22
Predetermined annealing is performed so that the high concentration n-type impurity region 10d 'can be formed by diffusion inside (FIG. 50). Subsequent steps are the same as those in FIG. 15 and FIG. 16 of the first embodiment.

According to the present embodiment, the high-concentration n-type impurity region 10d 'of the storage node portion is formed by impurity diffusion from the region whose area is reduced by the spacer insulating film 25, so that the pn junction area of the storage node portion is formed. Can be reduced, and the soft error resistance of the static random access memory can be improved. The method of forming the storage node portion described in this embodiment can be applied to other embodiments.

Embodiment 16 In this embodiment, the static random access memory according to the present invention is used as the cache memory of a high performance workstation. FIG. 51 is a system configuration diagram (flock diagram) of the high performance workstation according to the present embodiment. In FIG. 51, a high-capacity dynamic random access memory (DRAM) is used as the main memory of the high-performance workstation, and a high-speed static random access memory (SRAM) according to the present invention is used as the cache memory. It is used.

According to this embodiment, the data can be accessed by the high-speed cache memory without directly accessing the large-capacity main memory, which enables extremely high-speed operation. Although the present embodiment is applied to the cache memory, it can also be applied to the main memory. Further, although it is not limited to a high-performance workstation, a personal computer or memory capable of battery operation by taking advantage of the ultra-low power consumption of the cache memory of a large-sized computer, the main memory of a general-purpose computer, and the static random access memory according to the present invention. It can also be applied to the memory of handy devices such as cards.

Embodiment 7 This embodiment relates to another method of reducing the pn junction area of the storage node of the flip-flop circuit of the memory cell in the static random access memory cell in Embodiment 6. FIG. 52 is a diagram showing a cross-sectional view of a static random access memory cell in this example. In FIG. 52, the high-concentration n-type impurity region 37b to be the np junction of the storage node is separated by the thick field oxide film 23 ', and the area of the pn junction is reduced. Further, the high concentration n-type impurity region 37b separated by the field oxide film 23 'is a polysilicon PMOS.
It is connected by the gate electrode 42a of the transistor.

According to this embodiment, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0087]

According to the present invention, in a static random access memory cell, the area of a pn junction of a storage node of a flip-flop circuit is miniaturized in a self-aligned manner, and a stacked capacitive element is formed at the storage node. In addition, since the flip-flop circuit can be configured with a complementary inverter of a laminated structure and the cross-connecting portions of the flip-flop circuit can be connected in a self-aligned manner, α-rays can be formed in an extremely small memory cell area. It is possible to provide a semiconductor memory device that does not malfunction due to irradiation or a decrease in power supply voltage and can operate at high speed.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a sectional view of an embodiment of the present invention.

FIG. 3 is a sectional view of an embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the present invention.

FIG. 5 is a sectional view of an embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of a conventional technique.

FIG. 7 is a plan view of the related art.

FIG. 8 is a partial plan view of a conventional technique.

FIG. 9 is a partial plan view of the related art.

FIG. 10 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 11 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 12 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 13 is a cross-sectional view in a manufacturing process of an example of the present invention.

FIG. 14 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 15 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 16 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 17 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 18 is a plan view of another embodiment of the present invention.

FIG. 19 is a sectional view of another embodiment of the present invention.

FIG. 20 is a sectional view of another embodiment of the present invention.

FIG. 21 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 22 is a sectional view in the manufacturing process of an example of the present invention.

FIG. 23 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 24 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 25 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 26 is an equivalent circuit diagram of another embodiment of the present invention.

FIG. 27 is a plan view of another embodiment of the present invention.

FIG. 28 is a plan view of another embodiment of the present invention.

FIG. 29 is a sectional view of another embodiment of the present invention.

FIG. 30 is a sectional view of another embodiment of the present invention.

FIG. 31 is a plan view of another embodiment of the present invention.

FIG. 32 is a plan view of another embodiment of the present invention.

FIG. 33 is a sectional view of another embodiment of the present invention.

FIG. 34 is a plan view of another embodiment of the present invention.

FIG. 35 is a sectional view of another embodiment of the present invention.

FIG. 36 is a sectional view of another embodiment of the present invention.

FIG. 37 is a plan view of another embodiment of the present invention.

FIG. 38 is a plan view of another embodiment of the present invention.

FIG. 39 is a sectional view of another embodiment of the present invention.

FIG. 40 is a sectional view of another embodiment of the present invention.

FIG. 41 is a sectional view of another embodiment of the present invention.

FIG. 42 is a sectional view of another embodiment of the present invention.

FIG. 43 is a sectional view of another embodiment of the present invention.

FIG. 44 is a sectional view of another embodiment of the present invention.

FIG. 45 is a sectional view of another embodiment of the present invention.

FIG. 46 is a plan view of another embodiment of the present invention.

FIG. 47 is a plan view of another embodiment of the present invention.

FIG. 48 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 49 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 50 is a cross-sectional view in the manufacturing process of the embodiment of the present invention.

FIG. 51 is a block diagram showing an embodiment of the present invention.

FIG. 52 is a sectional view of another embodiment of the present invention.

[Explanation of symbols]

1, 1 '... data line, 2 ... word line, 3a, 3b, 3c, 3e, 3d, 3f, 3g, 3g',
10c ', 10d', 37a, 37b, 37c, 37
d, 48a, 48b, 48c, 48d, 48e, 48f
... High-concentration n-type impurity region, 4a, 4b, 4c, 6a, 6b, 8a, 8b, 12a,
14, 14a, 14a '14b, 14b', 15a, 1
5a ', 15b, 15b' 17a, 17b, 19a, 1
9b, 33a, 33b, 39a, 39b, 41a, 41
b, 41c, 41d, 43a, 43b, 45a, 45
b, 51a, 51b, 53a, 55a, 55b, 57
a, 57b, 57c, 57d, 63a, 63b ... Connection holes, 5a, 5b, 5c, 5d, 5d ', 5e, 5e',
11, 11a, 11b, 11c, 11d, 38a, 38
b, 38c, 38d, 49a, 49b ... Gate electrode (first layer polysilicon film), 7a, 7b, 7e ... Second layer low resistance polysilicon film, 7c, 7d ... Second layer high resistance polysilicon Membrane, 9a, 9b, 20a, 20b, 46a, 46b, 58
a, 58b ... Data line (first layer aluminum electrode), 20b ', 62a, 62b, 62c ... First layer aluminum electrode, 13a, 13b, 40a ... Ground wiring (second layer polysilicon film), 16a , 16b, 42a, 42b, 54a'54b '...
Polysilicon PMOS gate electrode / interconnection (third layer polysilicon film), 18a, 18b, 44a, 44c, 56a ', 56d'
... polysilicon PMOS drain region (fourth layer polysilicon film), 18c, 18d, 44b, 44d, 56b'56e ',
72d ... Polysilicon PMOS channel region (fourth layer polysilicon film), 18e, 44e, 56c ', 56f', 72e ... Polysilicon PMO source region (fourth layer polysilicon film), 21 ... N-type silicon substrate, 22 ... P-type well, 23, 23 '... Field oxide film, 24, 24' ... Gate oxide film, 25, 25 '... Spacer insulating film, 26, 26', 31, 68 ... Insulating film, 27, 28, 30 , 59, 70 ... Silicon oxide film, 29, 29 '... Polysilicon PMOS gate insulating film, 32a, 32b ... Polysilicon PMOS gate electrode / interconnection (second layer polysilicon film), 34a, 34b ... Polysilicon PMOS Drain region (third layer polysilicon film), 34c, 34d ... Polysilicon PMOS channel region (third layer poly film) Recon film), 34e ... Polysilicon PMOS source region (third layer polysilicon film), 35 ... Silicide layer, 36 ... Low concentration n-type impurity region, 47 ... Silicon oxide, 50a, 50b ... Gate electrode (second) 52a ... Ground wiring (third layer polysilicon film), 54a, 54b ... Polysilicon PMOS gate electrodes (fourth layer polysilicon film), 56a, 56d ... Polysilicon PMOS drain region ( Fifth layer polysilicon film), 56b, 56e ... Polysilicon PMOS channel region (fifth layer polysilicon film), 56c, 56f ... Polysilicon PMOS source region (fifth layer polysilicon film), 60 ... Tungsten Plugs 61a, 61b ... Fifth layer n-type polysilicon film, 64a, 64b, 71b ... Second layer aluminum Electrode (data line), 65 ... P type silicon substrate, 66 ... N type well, 67 ... N type buried polysilicon, 69 ... Twin well n type well, 13c ... Second layer n type polysilicon film, 73 ... Silicide film, 142a, 142b ... Third layer n-type polysilicon film, 144a, 144c ... Fourth layer n-type low resistance polysilicon film, 144b, 144d ... Fourth layer high resistance polysilicon film, 144e ... Power supply Wiring (fourth layer polysilicon film), 10 ... Active region, 74 ... Photoresist.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naotaka Hashimoto 1-280 Higashi Koikeku, Kokubunji City, Tokyo Stock Company Hitachi Central Research Institute (72) Inventor Takashi Hashimoto 1-280 Higashi Koikeku, Kokubunji, Tokyo Stock Company Within Hitachi Central Research Laboratory (72) Inventor Akihiro Shimizu 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ultra LSI Engineering Co., Ltd. (72) Inventor Koichiro Ishibashi Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory, 1-chome, 280 (72) Inventor, Katsuro Sasaki, Higashi Koikeku, Kokubunji, Tokyo, 1-chome, Ltd. 72, Ltd. Central Research Laboratory, Hitachi, Ltd. (72), Katsuhiro Shimoto, 1 Chome 280 Stock Company Hitachi Central Research Laboratory (72) Inventor Department Eiji Tokyo Kokubunji Higashikoigakubo 1-chome 280 address Co., Ltd. Hitachi, center within the Institute

Claims (4)

[Claims] 1. A flip-flop having, on a semiconductor substrate, a pair of first insulated gate field effect transistors for driving and a pair of second insulated gate field effect transistors for transfer whose gates are connected to word lines. A plurality of memory cells forming a circuit are provided, and the semiconductor substrate is provided with a first memory cell.
A semiconductor memory device in which a potential wiring and a second potential wiring are provided, and the memory cell is electrically connected to the first potential wiring and the second potential wiring, and the word line in the cell is a pair. A semiconductor memory device comprising a first wiring, and the first potential wiring in the cell is composed of a pair of second wirings. 2. The semiconductor memory device according to claim 1, wherein the first potential wiring is a power source wiring and the second potential wiring is a ground wiring. 3. The pair of first wirings are separated from each other, and the longitudinal direction thereof extends in the first direction, and the second potential wiring intersects the pair of first wirings and extends in the second direction. 2. The semiconductor memory device according to claim 1, further comprising a third wiring formed of an existing first wiring portion and a second wiring portion extending in the first direction. 4. A flip-flop having, on a semiconductor substrate, a pair of first insulated gate field effect transistors for driving and a pair of second insulated gate field effect transistors for transfer whose gates are connected to word lines. A semiconductor memory in which a plurality of memory cells forming a circuit are provided, a power supply wiring and a ground wiring are provided in the semiconductor substrate, and the memory cells are electrically connected to the first potential wiring and the second potential wiring. In the device, the word line in the cell is composed of a pair of word lines, and the word lines are spaced apart from each other on the main surface of the semiconductor substrate and extend in the first direction. The longitudinal direction of the gate of the field effect transistor extends along the first direction on the main surface of the semiconductor substrate between the pair of word lines, and the word in the cell Is composed of a pair of first wirings, and the ground wiring in the cell extends along the first direction on the main surface of the semiconductor substrate between the pair of word lines. apparatus.