JPH08293163A - Data detector - Google Patents

Abstract

PURPOSE: To obtain a high error correction rate from a digital circuit by provid ing a timing position detecting means that detects a position of a timing signal. CONSTITUTION: This device reproduces digital data demodulated from an analog signal in accordance with (d, k) rule. A comparator circuit 11 receives a signal RS reproduced by a reproducing system 10 and compares the signal RS with a specified threshold value TH and outputs a digital signal P with a shorter pulse width when the RS signal level is equal to the threshold value. Base on the signal P, VPLL 12 outputs a signal CLK of which a period corresponds to one bit of the digital signal to synchronizing circuits 141-143 as a synchronizing clock. A timing position detecting means consists of three pairs of delay circuits 131 133 and synchronizing circuits 141-143 and detects the timing position in a period of the digital data. An error judging part 152 detects that the data D1-D3 stored in the storage part 151 do not satisfy (d, k) rule and the error correcting part 153, in the case that the data include any error, outputs a control signal for correcting the data error to the storage 151.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for detecting the data of a signal that has passed through a transmission path, and more particularly to a data detecting apparatus for binarizing the signal that has passed.

[0002]

2. Description of the Related Art A reception signal obtained by passing a PCM signal through a transmission line and a reproduction signal of a digital recording device such as an optical disc device are obtained as analog values, which are PCM.
Various data detecting devices that binarize the original data in synchronization with the clock component of the signal have been developed with the improvement of the performance of the transmission line and the recording device. In recent years, as the performance of devices has been improved, the transfer rate has been improved in the transmission path and the recording density has been improved in the digital recording device, and various data detection devices have been developed to effectively use the transmission band. Is coming.

When detecting data, an erroneous digital data reproduction signal may be output due to distortion or noise. Specifically, in forming pits of an optical disc, it is difficult to form the size of smaller pits more stably, and when realizing high recording density, it is often smaller than the original size. Also in reproduction signal processing, waveform equalization reduces intersymbol interference in reproduction waveforms with such small pits or small pit intervals, but there is a limit to this equalization at high recording density. Yes, the reproduced signal with smaller pits or pit intervals becomes smaller than the original code interval, and the d constraint (d-cons) of the "(d, k) rule"
The error which becomes the digital data reproduction signal which does not satisfy traint) increases. The (d, k) rule is, for example, as in "Television Society Journal Vol.44, No10, pp.1369-1375 (1990)", in the (d, k; m, n; r) rule, The conversion of m-bit data into an n-bit code is defined as one unit, and the code data after modulation is determined in a maximum of r units. The attributes of the code data string after modulation are "1" and "1". The number of consecutive "0" s between "and" is greater than or equal to d and less than or equal to k, and this rule is simplified and expressed as (d, k).

A data detecting device for correcting such an error is described in Japanese Patent Laid-Open No. 6-243593. The data detecting device of this system will be described below. The reproduced signal obtained through the reproducing system in this conventional example is a digital data recording signal obtained by adding NRZI modulation to digital data modulated by the (d, k) rule having an arbitrary data pattern and recorded on an optical disc. It was obtained by reproduction.

A reproduction signal obtained through the reproduction system is converted into a binary signal. This binary signal is synchronized with the clock component of the reproduced signal to obtain a synchronized binary signal. From this synchronized binary signal, a synchronized short pulse signal having an inversion interval shorter than a predetermined time that disturbs the d constraint is detected. Whether the center position on the time axis of the short pulse binary signal before the synchronization of the synchronized short pulse signal is closer to the front side or the rear side of the sampling timing existing before and after the short pulse binary signal. Determine. The logic of the synchronized binary signal at the sampling timing closer to either the front side or the rear side is inverted and corrected.

[0006]

However, the above-mentioned conventional technique has the following problems. That is, since analog signal processing is used to determine the error position,
The circuit configuration becomes complicated. In addition, there is a problem that it is difficult to guarantee a certain degree of accuracy due to variations in the stability of elements forming the analog circuit.

The present invention has been made in order to solve the above problems, and an object of the present invention is to output a correct reproduced signal and a highly reliable signal with a simple circuit configuration by digital signal processing. It is to provide a data detection device capable of reproducing.

[0008]

A data detecting apparatus according to the present invention is a data detecting apparatus for reproducing digital data modulated from an analog signal according to a (d, k) rule, wherein the analog signal has a threshold value. A timing extraction unit that generates a timing signal that represents a crossing timing, a clock generation unit that generates a clock signal having a cycle corresponding to one bit of the digital data from the timing signal, and a position of the timing signal in the cycle. It is provided with a timing position detecting means for detecting and an error correcting means for correcting an error of the digital data according to the detected position, thereby achieving the above object.

In one embodiment, the timing position detecting means delays the timing signals by different delay amounts to generate N delay timing signals (N is a natural number of 2 or more), and a delay circuit. And N synchronization circuits that respectively generate N data signals according to the N delay timing signals by synchronizing the N delay timing signals with the clock signal. The error correction means corrects an error in the digital data based on the N data signals.

In one embodiment, the timing position detecting means delays the clock signal by different delay amounts to generate N (N is a natural number of 2 or more) delayed clock signals, respectively, and the delay circuit, And N synchronization circuits for respectively generating N data signals according to the N delayed clock signals by synchronizing the timing signals with the delayed clock signals. The means corrects an error in the digital data based on the N data signals.

In one embodiment, the timing position detecting means delays the timing signal by delaying the timing signal by a certain delay amount to generate a delayed timing signal, and delays the clock signal by a certain delay amount. A delay circuit for generating a clock signal and N data signals corresponding to the delayed timing signal and the delayed clock signal by synchronizing the timing signal and the delayed timing signal with the clock signal and the delayed clock signal And a synchronization circuit for generating the error, and the error correction means corrects an error in the digital data based on the N data signals.

In one embodiment, the timing position detecting means generates three delay timing signals, and the timing represented by the delay timing signals is T / 3 each when the cycle of the clock signal is T. It has been shifted.

In one embodiment, the timing position detecting means generates three delayed clock signals, and the timing represented by the delayed clock signals is T / 3 each when the cycle of the clock signal is T. It has been shifted.

In one embodiment, the error correction means includes a first counter that counts the number of irregular occurrences of a bit "1" in which the number of consecutive "1" s of the digital data is less than a predetermined number, and A second counter that counts the number of occurrences of irregular bits "0" in which the number of consecutive "0" s of digital data is less than a predetermined number, the number of occurrences of irregular bits "1", and the number of bits "0""
And threshold control means for changing the threshold according to the number of irregular occurrences.

[0015] In one embodiment, the threshold value control means includes the irregular bit "1" and the bit "0".
The step of changing the threshold value is changed in accordance with the difference in the irregular counts.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The same reference numerals indicate the same components.

(Embodiment 1) FIG. 1 is a block diagram of a first embodiment of a data detecting apparatus according to the present invention. Figure 2
3 is a timing chart in the first embodiment. Figure 2
(A) shows digital data of the NRZ (non return to zero) system modulated by the (d, k) rule having an arbitrary data pattern. FIG. 2B shows the NRZI (non return to zero inver) of the digital data shown in FIG.
The digital data converted to the ted system is shown. This N
The digital data of the RZI method is recorded on, for example, an optical disc with "1" as a mark. 2 (c) is
It is a figure which shows the waveform of the signal reproduced from the optical disk by the reproduction system 10 of FIG. In the following description, it is assumed that d is equal to 2 in the above (d, k) rule.

The comparison circuit 11 receives the signal RS ((c) in FIG. 2) reproduced by the reproduction system 10 and compares it with a predetermined threshold value TH. When the level of the signal RS is equal to the threshold value TH, the comparison circuit 11 outputs the signal P ((d) in FIG. 2) which is a digital signal having a short pulse width. PLL (p
The hase locked loop 12 receives the signal P, and based on the signal P, outputs a signal CLK ((e) in FIG. 2) whose one cycle corresponds to one bit of digital data to the synchronizing circuits 141 to 143 as a synchronizing clock. . The PLL 12 can be composed of, for example, a voltage controlled oscillator, an integrator, and a comparator.

The delay circuits 131 to 133 are equivalent to the comparison circuit 11
The signals P output from the
/ 3), Td, and (Td + T / 3), and delays the signal P and outputs it as the signals DP1 to DP3 to the synchronization circuits 141 to 143. 2 (f) to (h) show signals DP1 to DP3.
Shows the waveform of. Here, the time Td represents a reference delay time for correcting the delay amount in the PLL 12 and the delay circuits 131 to 133, and the time T represents one cycle of the signal CLK.

The synchronizing circuit 141 sets the signal D1 to "1" at the timing when the signal CLK first becomes "1 (high level)" after the rising edge of the signal DP1, and after the time T, "0 ( Low level) ". Synchronization circuits 142 and 143 also receive signals DP2 and DP3, respectively, operate in the same manner as synchronization circuit 141, and output signals D2 and D3. 2 (i) to (k)
Indicate the waveforms of the signals D1 to D3, respectively.

FIG. 3 is a timing chart of the signal DP1, the signal CLK and the signal D1. When the rising edge of the signal DP1 is located between the times t1 and t2 (period Tw), the signal D1 changes from “0” to “1” at the time t2, and from “1” to “0” at the time t3. "
Changes to The range indicated by the period Tw is hereinafter referred to as "detection window".

FIG. 4 is a timing chart when the rising edge of the signal P is located in the period 1 of the detection window. Here, "period 1" means the detection window (that is, the signal CL
Of the periods on the time axis corresponding to the period (starting at the rising edge of K and ending at the next rising edge), it is the first T / 3 period. Similarly, in the following, "period 2" and "period 3" are the T / 3 period immediately after the period 1 and the last T period in the area corresponding to the detection window, respectively.
/ 3 period. In the following, for the sake of simplicity, the expression “a signal is located in a certain period” is used instead of the expression “a signal rising edge is located in a certain period”.

As shown in FIG. 4A, when the signal P is located in the period 1 of the detection window, the signals DP1 to DP3 are the same as those in FIG.
(C) to (e). FIG. 4B shows the signal CL
K is shown. As shown in (f) to (h) of FIG. 4, signals D1 to D
3 is output at a timing synchronized with the signal CLK based on the signals DP1 to DP3. Therefore, the signals D1 to
When D3 is "0", "1" and "1", respectively, it can be determined that the signal P is located in the period 1 of the detection window.

FIG. 5 is a timing chart when the signal P is located in the period 2 of the detection window. Similarly, signal D1
When ~ D3 are "1", "1", and "1", respectively, it can be determined that the signal P is located in the period 2 of the detection window. FIG. 6 is a timing chart when the signal P is located in the period 3 of the detection window. Similarly, signals D1 to D3
, Respectively, are "1", "1" and "0", it can be determined that the signal P is located in the period 3 of the detection window. When the signal P is not located in the detection window period, the signal D
2 becomes "0".

The determination circuit 15 has a storage unit 151, an error determination unit 152, and an error correction unit 153. The storage unit 151 stores the data represented by the signals D1 to D3. The error determination unit 152 detects that the stored data does not satisfy the (d, k) rule (the data includes an error), and outputs a control signal indicating whether the stored data satisfies the (d, k) rule to the error correction unit. Output to 153. Error correction unit 15
3 receives the control signal output from the error determination unit 152, and if the data includes an error, the storage unit outputs the control signal for correcting the error of the data stored in the storage unit 151 based on a predetermined logic. Output to 151.

In the following description, successive rising edges of the signal CLK are defined as time points t (n-4) and t (n-).
3), t (n-2), t (n-1) and t (n). For the sake of simplicity, in the following, for example, “data represented by the signal D1 at time t (n)” is expressed as “data D1 (n)”.

The storage unit 151 stores data D1 (n-4) to
The data D1 (n), the data D2 (n-4) to D2 (n), and the data D3 (n-4) to D3 (n) are stored. When the data represented by the signal D2 does not satisfy the d constraint, in other words, a part of the data D2 includes a pattern that does not satisfy the predetermined rule that the digital data modulated by the predetermined method should have. Then, it is judged that the data is incorrect. Here, consider a case where the (d, k) rule when d = 2 is not satisfied. Therefore, the storage unit 151
When the number of “0” s between “1” and “1” of the data D2 is 0 or 1, the data D2 is
Judge that it contains an error. Specifically, the data D2 (n-
4) to D2 (n) are "01010" or "011"
When the pattern "0" is included, the data D2 is determined to include an error.

When the data D2 (n-4) to D2 (n) are "0", "1", "0", "1" and "0", respectively, the data D2 (n-1) and Either D2 (n) is erroneous, or data D2 (n-4) and D2 (n-3) is erroneous.
The error correction unit 153 uses in which period of the detection window the signal P at times t (n-3) and t (n-1) is located in order to determine which case.
That is, the error correction unit 153 uses the data D1 (n-3),
D3 (n-3), D1 (n-1) and D3 (n-1)
Data D2 based on a predetermined logic described later.
(N-1) and D2 (n) are incorrect or data D
It determines whether 2 (n-4) and D2 (n-3) are in error, and outputs a control signal for performing error correction of data to the storage unit 151. The storage unit 151 includes the error correction unit 1.
The control signal output from 53 is received and error correction is performed. Specifically, the storage unit 151 receives data representing the error position of the data as a control signal, and performs error correction by inverting the data at the error position.

How to obtain the above-mentioned predetermined logic will be described below with reference to FIG. FIG. 7 is a diagram showing a preceding pulse and a subsequent pulse. These pulses are
It is not synchronized by the signal CLK. Assuming that the time between the preceding pulse and the front end of the detection window is A and the time between the subsequent pulse and the rear end of the detection window is B, if A <B, it is determined that the preceding pulse is erroneous, and if A> B. Judge that the following pulse is incorrect. If A = B, it cannot be determined, and therefore either the preceding pulse or the following pulse may be erroneous.

FIG. 8 is a diagram for explaining how to obtain a predetermined logic when the delay circuits 131 to 133 are used. As shown in FIG. 8, when the preceding pulse is located in the period 1 of the detection window and the subsequent pulse is located in the period 2 of the detection window, A <B is satisfied, and therefore the preceding pulse is determined to be erroneous. . D1 (n-3) = 0 and D3 (n-3) = 1 when the preceding pulse is located in period 1 of the detection window, and D1 (n-3) = 1 when the following pulse is located in period 2 of the detection window.
1 (n-1) = D3 (n-1) = 1. If the preceding pulse is erroneous, the location of the data error is D2
(N-4) and D2 (n-3). Therefore,
If D1 (n-3) = 0, D3 (n-3) = 1, and D
When 1 (n-1) = D3 (n-1) = 1, it can be determined that the error positions are D2 (n-4) and D2 (n-3). Since the positions of the preceding pulse and the succeeding pulse in the detection window are three in each of the periods 1 to 3,
There are 3 × 3 = 9 combinations. For each case, the above-mentioned predetermined logic is obtained in the form of a table by obtaining the error position. Table 1 is a table showing a predetermined logic when the delay circuits 131 to 133 are used.

[0031]

[Table 1]

In Table 1, when "*" is added, it is arbitrary whether the error is caused by the preceding pulse and the following pulse. In Table 1, the one with the higher correction rate is selected based on the measured results. Where "correction rate"
Is the rate at which errors that do not satisfy the d constraint can be corrected.

Data D2 (n-3) to D2 (n)
Are “0”, “1”, “1”, and “0”, respectively, the error determination unit 152 determines that the data D2 (n−3)
It is determined that all of D2 (n) to D2 (n) are in error, and an error determination output indicating that the data D2 (n-3) to D2 (n) is in error is output to the error correction unit 153.

The error correction unit 153 corrects the data having an error among the data stored in the storage unit 151 based on the error determination output from the error determination unit 152. Storage unit 1
Finally, 51 sequentially outputs D2 (n-4) as a digital data reproduction signal RD (n-4) (see FIG. 2).
(l)).

According to the first embodiment, three delay circuits,
By providing three synchronization circuits and determination circuits,
It is possible to determine the error and correct it.

In the present embodiment, the predetermined logic is the logic shown in Table 1, but other logic may be used. In that case, the method of creating the predetermined logic may be as follows. "Data D1 (n-1), D3 (n-
1), D1 (n−3) and D3 (n−3) form a bit pattern, a specific bit is erroneous ”can be created by statistically obtaining the logic.

In the above description, the delay is delayed by the three delay circuits, the synchronization is synchronized by the three synchronizing circuits, and the judgment circuit judges the error position from the binary data D1 to D3. By using the delay circuit and the synchronization circuit of, it is possible to improve the resolution of position detection in the detection window of the signal P. FIG. 9 shows five delay circuits 1.
31 is a block diagram of a data detection device using 31 to 135 and five synchronization circuits 141 to 145. FIG. As described with reference to FIG. 1, the signals D1 to D5 are generated according to the position of the signal P in the detection window. In FIG. 9, the delay times of the delay circuits 131 to 135 are (Td
-2T / 5), (Td-T / 5), Td, (Td + T /
5) and (Td + 2T / 5). Here, the respective periods obtained by dividing the detection window into 5 are set to periods 1 to 5 in order from the earliest on the time axis. Synchronization circuits 141-145
Outputs data D1 to D5 depending on which of the periods 1 to 5 the signal P is located to the determination circuit 16. Judgment circuit 1
6 includes a storage unit 161, an error determination unit 162, and an error correction unit 163. The determination circuit 16 uses the data D1 to D5.
When it is determined that there is an error in the data based on a predetermined logic, the error is corrected and output as the reproduction signal RD. Table 2 is a table showing a predetermined logic used by the error determination unit 162.

[0038]

[Table 2]

In Table 2, when "*" is added, it is arbitrary whether the error is caused by the leading pulse and the trailing pulse. In Table 2, the one with the higher correction rate is selected based on the measured results.

The optimization of N when the number of divisions of the detection window (corresponding to the number of delay circuits described above) is N will be described below. FIG. 10 is a graph showing the relationship between the number N of divisions of the detection window and the correction rate. The graph of FIG. 10 is the result of actual measurement using a circuit similar to the configuration of FIGS. 1 and 9. In the case of N = 3, the circuit of FIG. 1 and the logic of Table 1 are
When N = 5, the circuit of FIG. 9 and the logic of Table 2 are used. The correction rate of an error that does not satisfy the d constraint when d = 2 is 95% or more when N = 3 (three delay circuits). The correction rate when N is 4 or more is not significantly improved over the correction rate when N = 3. Therefore, in consideration of downsizing of hardware and speeding up of processing, the case of N = 3 (circuit of FIG. 1) is more preferable.

Further, when N = 3, the difference in the delay amount is set to about -T / 3 and about T / 3, but other values may be set. Here, the above three delay circuits are (Td-D
It is assumed that the delay amounts are LY), Td, and (Td + DLY). At this time, it is preferable that T / 5 <DLY <T / 2. Furthermore, it is more preferable that DLY = T / 3. This is because if DLY = T / 3, the error can be corrected on average regardless of the type of optical disc medium and the reproduction state.

Further, in the above example, it has been described that the signal P is delayed by N (integer of 3 or more) delay circuits and synchronized with the single signal CLK. However, N signals CLK (1) to CLK (N) are generated by delaying the single signal CLK by N delay circuits, and the signal P is synchronized by the synchronization timing of these N signals. May be turned into. FIG. 11 is a block diagram showing a configuration in which a plurality of synchronization circuits use different clocks.

In the above example, the error is corrected by using only the d constraint of the (d, k) rule, but the error can be corrected by using the k constraint with the same configuration.
It is also possible to use both d and k constraints to correct the error. However, in the case of high density optical discs, errors that do not satisfy the d constraint have a greater impact on the bit error rate than errors that do not satisfy the k constraint. Therefore, it is more efficient to perform error correction based on the d constraint.

(Second Embodiment) FIG. 12 is a block diagram of a second embodiment of the data detecting apparatus according to the present invention. 12
In, the reproduction system 10, the comparison circuit 11, the PLL 12, the delay circuits 131 and 132, and the determination circuit 15 function as in FIG. FIG. 13 is a timing chart in the second embodiment.

The delay circuit 132 receives the signal P and outputs T
A signal DP ((f) in FIG. 13) is generated by delaying the signal P ((d) in FIG. 13) by / 3. Where T
Is the clock cycle of the reproduction signal RS ((c) of FIG. 13). The delay circuit 131 outputs the signal DCLK ((g) in FIG. 13) to the synchronization circuit 341 by delaying the signal CLK by T / 3.

The synchronizing circuit 341 sets the signal D1 to "1" at the timing when the signal DCLK first becomes "1" after the rising edge of the signal P, and after the time T,
By setting to "0", a signal synchronized by the signal DCLK is obtained. The synchronization circuit 341 uses the signal CLK.
In order to match the timing with the signals D2 and D3 which are transited by, the signal synchronized by the signal DCLK is resynchronized by the signal CLK and output as the signal D1 ((h) in FIG. 13).

The synchronizing circuit 342 sets the signal D2 to "1" at the timing when the signal CLK first becomes "1" after the rising edge of the signal P, and after the time T, becomes "0".
To obtain a signal synchronized by the signal CLK. The synchronization circuit 342 resynchronizes the signal synchronized by the signal CLK with the signal D2 in order to match the timing with the signal D1.
((I) in FIG. 13).

The synchronizing circuit 343 sets the signal D3 to "1" at the timing when the signal CLK first becomes "1" after the rising edge of the signal DP, and after the time T,
By setting to "0", a signal synchronized by the signal CLK is obtained. The synchronizing circuit 343 resynchronizes the signal synchronized by the signal CLK with the signal CLK to match the timing with the signal D1, and outputs the signal as a signal D3 ((j) in FIG. 13).

In the second embodiment, the delay time is T / 3, but other values may be used.

In the second embodiment, by using the above structure, the same effect as that of the first embodiment can be obtained with a simpler circuit structure.

(Embodiment 3) FIG. 14 is a block diagram of a third embodiment of the data detecting apparatus according to the present invention. 14
, The reproduction system 10, the PLL 12, the delay circuits 131 to
133 and the synchronizing circuits 141-143 function similarly to FIG.

The difference from the configuration of FIG. 1 is that the comparison circuit 11,
A determination circuit 45 and a threshold control circuit 46. The comparison circuit 11 outputs the signal P and the signal CS representing the NRZI code ((b) of FIG. 2) to the threshold value control circuit 46 based on the signal RS.

The determination circuit 45 has a storage unit 451, an error determination unit 452 and an error correction unit 453. Judgment circuit 4
Numeral 5 generates the signal D2 from the signals D1 to D3, detects that the data represented by the signal D2 does not satisfy the predetermined rule of the recorded digital data (that is, “bit regular”), and performs threshold control. It outputs a bit regular signal BI to the circuit 46. Here, the predetermined rule is a d constraint. This bit regular signal BI has a signal D2 of "01010" or "01".
When it is "10", it takes "1", and otherwise, it takes "0". The storage unit 451, the error determination unit 452, and the error correction unit 453 are the same as the storage unit 15 except that the error determination unit outputs the above-described bit regular signal BI.
1, the same function as the error determination unit 152 and the error correction unit 153.

The threshold control circuit 46 includes counters 461 and 462, an error calculating circuit 463, a threshold adjusting circuit 464.
And AND gates 465 and 466. AN
When the bit regular signal BI is "1" and the signal CS is "1", the D gate 465 outputs
"1" is output, otherwise "0" is output. AND gate 466 has a bit regular signal B
When I is "1" and the signal CS is "0",
"1" is output, otherwise "0" is output.

The counter 461 is ANDed within a predetermined period.
The number of times the output of the gate 465 becomes "1" is counted. This count value is the NRZ generated within a predetermined period.
It corresponds to the number of bit regulars of the code “1” in the I code.

The counter 462 is ANDed within a predetermined period.
The number of times the output of the gate 466 becomes "1" is counted. This count value is the NRZ generated within a predetermined period.
This corresponds to the number of bit regulars of the code “0” in the I code.

The error calculation circuit 463 calculates a value obtained by subtracting the count value of 462 from the count value of the counter 461, and outputs data representing the difference value to the threshold value adjustment circuit 464. This difference value corresponds to the difference between the count values of the bit regulars of "1" and "0" that occur during a predetermined period.

FIG. 15 is a diagram showing the relationship between the threshold value TH and the signal binarized by NRZI. In FIG. 15, the level of (a) is the optimum threshold, the level of (b) is larger than the optimum threshold, and the level of (c) is smaller than the optimum threshold. When the threshold value TH is shifted from the optimum value, as can be seen from FIG. 15, the sign of the bit regular varies depending on the direction of the shift (whether the level of the threshold value TH increases or decreases). That is, when the threshold value TH becomes larger than the optimum level (a), "1" is set in the NRZI code.
When the threshold value TH becomes smaller than the optimum level (a), the bit regular of “0” occurs in the NRZI code.

The threshold adjustment circuit 464 receives from the error calculation circuit 463 the data corresponding to the difference between the count values of the bit regulars of "1" and "0" which occur during the predetermined period, and the threshold value is adjusted according to the difference between the count values. Change the TH level. Specifically, when the difference between the count values is positive, that is, when the count value of the bit regular of "1" is larger than the count value of the bit regular of "0", the level of the threshold value TH is decreased. When the difference between the count values is negative, that is, when the count value of the bit regular of "1" is smaller than the count value of the bit regular of "0", the level of the threshold value TH is increased.

With the above arrangement, the threshold can be automatically adjusted by obtaining the frequency of occurrence of bit regular from the reproduction signal.

In addition, the error calculation circuit 463 operates the counters 461 and 46 according to the type of medium and the characteristics of the device.
By weighting the count value from 2 and then taking the difference, more accurate threshold value adjustment can be performed.

Further, in the third embodiment, it is preferable to increase the step of changing the threshold value TH when the difference between the count values is large, and to decrease the step of changing the threshold value TH when the difference between the count values is small. . This makes it possible to approach the optimum level in a short time when the threshold value is largely shifted from the optimum level, and when the difference between the threshold value and the optimum level becomes small, the optimum level is exceeded. You can get closer without repeating shots.

[0063]

According to the present invention, the position in the detection window of digital data at the timing when the analog signal reproduced from the recording medium or the like crosses a predetermined threshold is detected, and the position of the timing in the detection window is detected. Then, the error of the data is corrected. As a result, at least the following effects can be obtained.

Since the position in the detection window can be detected with high resolution, the error correction rate can be improved.

The delay amount of N delay circuits for delaying the pulse signal obtained from the reproduced analog signal is variable, and a control circuit for controlling each delay amount is further provided.
As a result, it is possible to determine the bit regular where the specific portion of the digital data reproduction signal deviates from the predetermined rule of the digital data recording signal and improve the error correction rate.

Further, the bit regular of the reproduced digital data is counted, and the threshold for binarization can be changed according to the magnitude of the count number of the bit regular of "1" and "0". Thereby, the error correction rate can be further improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a data detection device according to the present invention.

FIG. 2 is a timing chart in the first embodiment.

FIG. 3 is a timing chart of a signal DP1, a signal CLK, and a signal D1.

FIG. 4 is a timing chart when the rising edge of the signal P is located in the period 1 of the detection window.

FIG. 5 is a timing chart when the signal P is located in the period 2 of the detection window.

FIG. 6 is a timing chart when the signal P is located in the period 3 of the detection window.

FIG. 7 shows a preceding pulse and a subsequent pulse.

FIG. 8 is a diagram for explaining how to obtain a predetermined logic when using the delay circuits 131 to 133.

FIG. 9 is a block diagram of a data detection device using five delay circuits and five synchronization circuits.

FIG. 10 is a graph showing the relationship between the number N of divisions of the detection window and the correction rate.

FIG. 11 is a block diagram showing a configuration in which a plurality of synchronization circuits use different clocks.

FIG. 12 is a block diagram of a second embodiment of the data detection device according to the present invention.

FIG. 13 is a timing chart in the second embodiment.

FIG. 14 is a block diagram of a third embodiment of the data detection device according to the present invention.

FIG. 15 is a diagram showing a relationship between a threshold TH and a signal binarized by NRZI.

[Explanation of symbols]

 10 reproduction system 11 comparison circuit 12 PLL 15 determination circuit 131, 132, 133 delay circuit 141, 142, 143 synchronization circuit 151 storage unit 152 error determination unit 153 error correction unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04L 7/00 H04L 7/00 D // H04L 25/49 9199-5K 25/49 A

Claims (8)

[Claims] 1. A data detection device for reproducing digital data modulated from an analog signal according to a (d, k) rule, the timing extraction generating a timing signal representing a timing at which the analog signal crosses a threshold value. Means, clock generating means for generating a clock signal having a cycle corresponding to one bit of the digital data from the timing signal, timing position detecting means for detecting the position of the timing signal in the cycle, and the detected clock signal. An error correction unit that corrects an error of the digital data according to a position, and a data detection device. 2. The timing position detecting means delays the timing signals by different delay amounts to generate N delay timing signals (N is a natural number of 2 or more), respectively, and the N delay circuits. And N synchronization circuits that generate N data signals in accordance with the N delay timing signals by synchronizing the delay timing signals with the clock signals. Means, based on the N data signals,
The data detection device according to claim 1, which corrects an error in the digital data. 3. The timing position detecting means delays the clock signal by a different delay amount to obtain N.
A delay circuit for generating a plurality of (N is a natural number of 2 or more) delayed clock signals, and N pieces of data according to the N delayed clock signals by synchronizing the timing signals with the delayed clock signals. And N synchronizing circuits for respectively generating signals, wherein the error correction means is based on the N data signals,
The data detection device according to claim 1, which corrects an error in the digital data. 4. The timing position detecting means delays the timing signal by a certain delay amount to generate a delayed timing signal, and delays the clock signal by a certain delay amount to generate a delayed clock signal. By synchronizing the delay circuit to be generated, the timing signal and the delayed timing signal with the clock signal and the delayed clock signal, N delayed data signals corresponding to the delayed timing signal and the delayed clock signal are generated. A synchronization circuit, wherein the error correction means is based on the N data signals,
The data detection device according to claim 1, which corrects an error in the digital data. 5. The timing position detection means generates three delay timing signals, and the timing represented by the delay timing signals is shifted by T / 3 when the cycle of the clock signal is T. The data detection device according to claim 2, wherein 6. The timing position detecting means generates three delayed clock signals, and the timing represented by the delayed clock signals is shifted by T / 3 when the cycle of the clock signal is T. The data detection device according to claim 3, wherein 7. The error correction means includes a first counter for counting the number of irregular occurrences of a bit "1" in which the number of consecutive "1" s in the digital data is less than a predetermined number, and a first counter for the digital data. A second counter that counts the number of occurrences of irregular bits "0" in which the number of consecutive "0" s is less than a predetermined number, the number of occurrences of irregular bits "1", and the number of occurrences of irregular bits "0". The data detection device according to claim 1, further comprising a threshold value control unit that changes the threshold value according to the number of regular occurrences. 8. The threshold value control means includes the bit “1”.
8. The data detection device according to claim 7, wherein the step of changing the threshold value is changed in accordance with a difference in the count of the irregularity of 1 and the irregularity of the bit “0”.