JPH08292927A - Information processor - Google Patents

Abstract

PURPOSE: To provide an information processor which can displays the performance of an external extension device such as an application board and an extension unit sufficiently without the restrictions of an external bus interface for connecting the external extension device. CONSTITUTION: When the extension unit 21 is connected to the external bus interface 20, a signal S Di goes down to a LOW level and an MPU 10 recognizes the connection of the extension unit 21 from the level of this signal S Di. After the connection of the extension unit 21 is recogninzed, a serial communication is made between the MPU 10 and extension unit 21 through the external bus interface 20 with signals S CK, S Di, and S Do to send and receive information on the kind, operation frequency, transfer protocol of the extension unit 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus provided with an external bus interface for connecting an external expansion device for executing an expanded function operation.

[0002]

2. Description of the Related Art Generally, an expansion bus used in a personal computer is composed of basic bus lines such as address lines, data lines, control lines, clock lines, etc. An application board connected to this expansion bus is a bus line signal. It is made to suit.

The bus clock is usually fixed at several MHz, and application boards and expansion units are made to operate in accordance with this clock.

A memory board is one of the expansion units. The memory board and the bus line connected to the memory board will be described with reference to FIG. Figure 10
FIG. 4 is a conceptual diagram showing signal connection between a CPU board and a memory board in a conventional personal computer.

CPU board 8 of personal computer
0 and a SIMM memory board (hereinafter referred to as a memory board) 85 are connected by a bus 86, as shown in FIG. The bus 86 is composed of basic lines such as an address line 81, a data line 82, and a control line 83, and a SIMM ID line 84 for recognizing specifications such as a memory capacity of the memory board 85 and an access speed. The SIMM ID line 84 is usually composed of about 4 to 6 signal lines, and Low, Hi, Op of the signal are set.
The above specification is identified by the combination of en, and the recognizable number of the specification is SIMM ID line 8
Limited by the number of signal lines of four.

[0006]

However, since the application board and expansion unit operate in synchronization with the bus clock, the functions of the application board and expansion unit having a transfer rate higher than the bus clock cannot be fully utilized, and the expansion bus is not utilized. Will be subject to the restrictions. Therefore, due to the restriction, it may not be possible to bring out a capacity higher than a predetermined level.

For example, as described above, the memory board 8
In 5, the number of signal lines of the SIMM ID 84 limits the number of recognizable parts for the specifications of the memory board 85. To increase the number of recognizable parts, the SIMM ID
It is necessary to increase the number of signal lines of the line 84.

An object of the present invention is to provide an information processing apparatus capable of fully exhibiting the performance of an external expansion device without being restricted by an external bus interface for connecting the external expansion device such as an application board or expansion unit. To provide.

[0009]

According to the first aspect of the present invention,
A function processing means for executing a predetermined function operation, an external bus interface for connecting an external expansion device for executing the expanded function operation, and a function operation of the function processing means,
In an information processing device comprising a control means for controlling an extended function operation of the external expansion device and an operation of the external bus interface, between the external expansion device and the control means via the external bus interface. It is characterized in that a communication means for communication is provided.

According to a second aspect of the present invention, in the information processing apparatus according to the first aspect, the external expansion device is provided by using a signal line connecting the external expansion device and the control means via the external bus interface. Is connected to the external bus interface, and the communication means performs communication between the external expansion device and the control means by using a signal line of the detection means. Is characterized by.

According to a third aspect of the present invention, in the information processing apparatus according to the first aspect, the control means is configured to control the external expansion device based on information obtained by communication with the external expansion device by the communication means. It is characterized in that the control method of the external bus interface is changed so that the consistency for maximizing the function can be obtained.

According to a fourth aspect of the present invention, in the information processing apparatus according to the first aspect, the function processing means comprises a storage means for storing a program relating to control by the control means.

According to a fifth aspect of the present invention, in the information processing apparatus according to the first aspect, the function processing means includes an image pickup means for converting a subject image into an image signal, and an A / A for converting the image signal into a digital signal. It is characterized by having a D converter, a signal processing means for performing signal processing on the digital signal, and a display means for displaying the image signal.

According to a sixth aspect of the present invention, in the information processing apparatus according to the first aspect, the function processing means includes an input means for inputting a digital video signal, and a digital video signal input to the input means. And a display unit for displaying.

According to a seventh aspect of the present invention, in the information processing apparatus according to the sixth aspect, the input means is set so that an analog video signal can be input by a switching operation.

[0016]

In the information processing apparatus according to the first aspect, the communication means communicates between the external expansion device and the control means via the external bus interface.

According to another aspect of the information processing apparatus of the present invention, the external expansion device is connected to the external bus interface by the detection means using a signal line connecting the external expansion device and the control means via the external bus interface. It is detected that the communication means communicates between the external expansion device and the control means by using the signal line of the detection means.

According to another aspect of the information processing apparatus of the present invention, the control means provides the consistency for maximizing the function of the external expansion device based on the information obtained by the communication with the external expansion device by the communication means. To change the control method of the external bus interface.

In the information processing apparatus according to the fourth aspect, the function processing means comprises a storage means for storing a program related to control by the control means.

According to another aspect of the information processing apparatus of the present invention, the function processing means includes an image pickup means for converting a subject image into an image signal, an A / D converter for converting an image signal into a digital signal, and a signal processing into a digital signal. And a display means for displaying an image signal.

In the information processing apparatus according to the sixth aspect, the function processing means has an input means for inputting the digital video signal and a display means for displaying the digital video signal input to the input means.

In the information processing apparatus according to the seventh aspect, the input means is set so that the analog video signal can be input by the switching operation.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

First, a signal connection between a host computer which is the information processing apparatus of the present invention and an expansion unit connected to the host computer through an external bus interface will be conceptually described with reference to FIG. FIG. 1 is a conceptual diagram showing signal connection between a host computer which is an information processing apparatus of the present invention and an expansion unit.

As shown in FIG. 1, the host computer is a microprocessor (hereinafter referred to as MPU) 10 for executing computation, processing and control, and an external bus interface for connecting the microprocessor 10 and the expansion unit 21. And 20.

The external bus interface 20 is the MPU 1
It has a plurality of signal lines connected to 0a. As signal lines, an address line 11, a data line 12, and a line 13 for supplying a read timing signal (hereinafter referred to as / RD) to the external bus interface 20.
A line 14 for supplying a write control signal (hereinafter referred to as / WR) to the external bus interface 20, and a line 15 for supplying a control signal (hereinafter referred to as / MEM) for requesting reading to the memory. A line 16 for supplying a control signal (hereinafter referred to as I / O) for requesting reading to the I / O device, and a line 17 for supplying a serial clock (hereinafter referred to as SCK) which is a timing clock during serial data communication. A line 18 for outputting serial data (hereinafter referred to as S Do) to the external bus interface 20, a line 19 for inputting serial data (hereinafter referred to as S Di) from the external bus interface 20 to the MPU 20, and a clock speed Supply a bus clock (hereinafter referred to as bus CK) that is variably controlled to the external bus interface 20 That the line 22, the serial data command instructing signal for instructing the instruction by the time of communication (or less, S as SC) external bus interface 2
There is a line 23 for supplying 0.

In this embodiment, the address line 11 is 24
The data line 12 is composed of 24 bit lines A23 to A0 and the data line 12 is 16 bit width D15 to D0. However, the number of address lines and data lines is not limited to the above-mentioned number, and The optimum number is set according to. In addition, each signal SCK, SD
Serial communication is performed between the MPU 10 and the extension unit 21 using i, S Do, and S CS.

As the expansion unit 20, for example, EE
PROM, expansion memory, compression board for image compression,
Hard disk, magneto-optical disk (MOD), modem card having FAX function, network card for constructing LAN, etc., character recognition card for processing such as character recognition, input pen board for pen input, Special image processing board for color management (CMS) of captured images or images on memory,
There is a unit for executing various applications such as a line-of-sight input control card for performing control by line-of-sight input. A type code indicating the type is associated in advance with these expansion units. For example, as shown in FIG. 1, each extension unit has "00h" to "0A".
Corresponding type codes up to "h" are assigned.

Next, a data transmission / reception operation performed between the MPU 10 and the expansion unit 21 via the external bus interface 20 will be described with reference to FIG. FIG. 2 is a diagram showing a bit configuration of data transmitted and received between the host computer and the expansion unit in FIG.

When the expansion unit 21 is not connected to the external bus interface 20, the signal S Di is pulled up to Vcc in the open state. When the expansion unit 21 is connected to the external bus interface 20,
The signal S Di becomes LOW level, and this signal S Di
Depending on the level of, the MPU 10 recognizes the connection of the expansion unit 21.

After recognizing the connection of the expansion unit 21, each signal S
Serial communication is MP by CK, S Di, S Do
This is performed between the U10 and the expansion unit 21 via the external bus interface 20, and by this communication, information such as the type of the expansion unit 21, the operating frequency, and the transfer protocol is transmitted and received. Specifically, as shown in FIG. 2A, the transmission data from the MPU 10 side consists of 8 bits, and each bit has a transfer baud rate, a remaining memory capacity, a memory capacity, a transfer protocol, an operating frequency, and a type. Inquiry information (flag) such as (name) is assigned. Similar to the transmission data, the reception data corresponding to the transmission data is composed of 8 bits, and each 8 bits is assigned with the reply information (flag) corresponding to the inquiry information.

For example, as inquiry information about the type, as shown in FIG. 2B, transmission data having a bit configuration of "00000001" is sent, and as response information to this, 8-bit indicating a type code (name) is sent. Is returned from the expansion unit 21 to the MPU 10. Also,
As inquiry information regarding the operating frequency, as shown in FIG. 2C, transmission data having a bit configuration of “00000010” is sent, and as response information to this, 8-bit data indicating the operating frequency is sent from the expansion unit 21. M
Returned to PU10.

The MPU 10 sets conditions for maximizing the performance of the expansion unit 21 based on the information obtained by communication. For example, the bus clock is changed.

(First Embodiment) Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a first embodiment of the information processing apparatus of the present invention and a compression card connected to it.

As shown in FIG. 3, the information processing apparatus includes an optical block 31 having a lens, a shutter and the like. An optical image captured by the optical block 31 is converted into an electric signal by a CCD (charge coupled device) 32. As the CCD 32, a TV type one having square pixels is used.

An electric signal from the CCD 32 is converted into a digital signal by an A / D converter (hereinafter referred to as A / D) 34, and the digital signal is given to a viewfinder 39 and a digital signal processing circuit 35.

The viewfinder 39 selectively switches between the image represented by the digital signal from the A / D 34 and the image represented by the analog signal from a D / A converter (hereinafter referred to as D / A) 37, which will be described later. indicate.

The digital signal processing circuit 35 includes an A / D 34
After temporarily storing the digital signal from the memory 36 in the memory 36, the digital signal stored in the memory 36 is subjected to image processing such as white balance, AE correction, gamma processing, image compression, and noise reduction. Further, the digital signal stored in the memory 36 is subjected to arithmetic processing for image processing by the MPU 33 described later.

The digital signal from the digital signal processing circuit 35 is given to the D / A 37, the recording section 40 or the external bus interface 41.

The D / A 37 is a digital signal processing circuit 35.
The digital signal from is converted into an analog signal, and the analog signal is given to the viewfinder 39 and the video out 38. The video out 38 is composed of a terminal for outputting an analog signal from the D / A 37 to an external monitor or the like.

The recording section 40 includes a digital signal processing circuit 35.
The digital signal from is recorded on a recording medium. For example, a recording operation of recording a digital signal as a still image on a hard disk or the like is performed. In addition, the recording unit 40 has a VTR.
A terminal for connecting the
By outputting a digital signal by TR, VT
It is set so that recording by R is possible.

The external bus interface 41 includes a compression board 50 and an MPU 3 which are expansion units connected to the external bus interface 41.
3 is an interface for transmitting and receiving data to and from the computer.

The MPU 33 performs arithmetic processing for the above-mentioned image processing and control for each of the above-mentioned blocks, and uses the above-mentioned respective signals S CK, S Di, S Do (shown in FIG. 1) to communicate with the compression card 50. Serial communication is performed between them via the external bus interface 41.

The compression card 50 has an interface section (hereinafter referred to as I / F) 51 connected to the external bus interface 41. A CPU (not shown) is built in the I / F 51, and the CPU controls transmission / reception of data including image data and control signals and controls each unit in the compression board 50.

Transmission / reception of data via the I / F 51 is performed between the external bus interface 41 and the memory 57, and between the external bus interface 51 and the color space conversion unit 52.

The color space conversion unit 52 converts RGB image data into YUV data of a color difference signal, and vice versa for the data from the raster / block conversion unit 53.

The raster / block conversion unit 53 is 8 × 8 for every 8 lines for the YUV data from the color space conversion unit 52.
DCT / ID
This is performed on the data from the CT unit 54.

The DCT / IDCT section 54 performs discrete cosine transform for each 8 × 8 block, and
Quantize inverse discrete cosine transform / inverse quantizer 5
Perform on data from 5.

The quantizing / inverse quantizing unit 55 compresses the data amount by quantizing the discrete cosine transformed data in accordance with the spatial frequency band, and
Decompression by inverse quantization is performed on the data from the Huffman decoder / decoder 56.

The Huffman decoder / decoder 56 is
The quantized data is Huffman-encoded, and Huffman decoding is performed on the image data stored in the memory 57.

The memory 57 stores the Huffman-encoded data from the Huffman decoder / decoder 56 as compressed image data, and this compressed image data is I / O.
It is sent to the external bus interface 41 via F51. The memory 57 also includes an external bus interface 4
1 stores compressed image data fetched through the I / F 51, and the compressed image data is stored in the Huffman decoder / decoder 56, the quantizer / inverse quantizer 55, and the DCT / decoder.
The IDCT unit 54, the raster / block conversion unit 53, and the color space conversion unit 52 are sequentially expanded. The expanded image data is sent to the external bus interface 41 via the I / F 51.

Next, communication performed between the MPU 33 and the compression board 50 via the external bus interface 41 will be described with reference to FIG. FIG. 4 is a timing chart of signals during a communication operation performed between the information processing apparatus of FIG. 3 and a compression card connected to the information processing apparatus.

When the compression board 50 is connected to the external bus interface 41, as shown in FIG. 4, SCK, SDi, SDo are provided between the MPU 33 and the compression board 50.
Serial communication is performed by each signal.

First, data transmission is performed. At the time of data transmission, as shown in FIG. 4A, a start bit of S Do, 8 bits of data, a parity bit by an even parity method, and a stop bit are sequentially transmitted in synchronization with the clock of SCK. Specifically, the start bit starts with "0", the data "01h", the parity bit "1" are sequentially sent, and finally the stop bit "1" is sent. The data “01h” indicates an inquiry about the type of expansion board, as described above with reference to FIG.

The response data from the compression card 50 for this transmission data is returned, and this response data is sent to the MPU 33.
Will be received at. At the time of data reception, as shown in FIG. 4B, a start bit of SDi, 8 bits of data, a parity bit by an even parity method, and a stop bit are sequentially received in synchronization with the clock of SCK. In this embodiment, "02h" is received as data, and the expansion board connected to the external bus interface 41 is recognized as the compression board 50 from this data. Further, other information (flags) such as the transfer baud rate, the remaining memory capacity, the memory capacity, the transfer protocol, and the operating frequency are also recognized by the above-mentioned communication.

In this way, the switching control of the image processing procedure and the cycle of the external bus data transfer clock is performed based on the specification for the compression card 50 recognized by the communication.

Next, the operation of the information processing apparatus of this embodiment will be described.

When the compression card 50 or other expansion unit is not connected to the external bus interface 41,
The optical image captured by the optical block 31 is converted into an electric signal by the CCD 32, and the electric signal is converted into a digital signal by the A / D 34. The digital signal from the A / D 34 is given to the digital signal processing circuit 35, and the digital signal processing circuit 35 performs the above-mentioned image processing.

The digital signal image-processed by the digital signal processing circuit 35 is recorded by the recording section 40.

When image compression is performed in order to increase the recording capacity for the image data, the MPU 33 performs a compression calculation process on the image data taken into the memory 36 from the digital signal processing circuit 35, and the processed image data is After being written in the memory 36, it is encoded and recorded in the recording unit 40.

On the other hand, when the compression card 50 is connected to the external bus interface 41, the connection is recognized by the serial communication described above, and the MPU 33 performs an operation on the data from the digital signal processing circuit 35. Instead, the processing procedure is changed so that the data is transferred to the compression card 50 via the external bus interface 41 by the external bus transfer clock set by the above-mentioned switching control. For example, the cycle of the external bus transfer clock is increased from the usual 8 MHz to 20 MHz.

In the compression card 50, the transferred data is sequentially taken in through the I / F 51, and the color space conversion unit 52
Processing by the raster / block conversion unit 53, processing by the DCT / IDCT unit 54, and processing by the quantization / inverse quantization unit 55 in real time to generate compressed image data. The generated compressed image data is written in the memory 36, and the compressed image data written in the memory 36 is sent to the recording unit 40 via the external bus interface 41. The recording unit 40 records the compressed image data.

As described above, the information processing apparatus recognizes that the compression card 50 is connected, changes the processing procedure from soft compression to hard compression, and speeds up the cycle of the external bus data transfer clock. The compression card 50 is changed to perform image compression processing in real time. Therefore, the compression card 5 is not restricted by the bus clock which is normally fixed at 8 MHz.
The performance of 0 can be fully exhibited.

In this embodiment, the compression card 50 has a C
Since the PU is installed, the signal S C can be used for serial communication.
Do not use S.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. Figure 5
Is a timing chart of signals in a read operation and a write operation between the second embodiment of the information processing apparatus of the present invention and an EEPROM connected thereto, and FIG. 6 shows a second embodiment of the information processing apparatus of the present invention. EEPROM connected
FIG. 7 is a diagram showing the contents of the instruction set, and FIG. 7 is a diagram showing the relationship between addresses and data for discriminating the expansion unit by the communication operation of the second embodiment of the information processing system of the invention.

This embodiment has the same structure as that of the first embodiment. In this embodiment, an example in which an EEPROM is connected as an expansion unit to the external bus interface will be described. In this EEPROM, the compression card 5 of the first embodiment will be described.
Unlike 0, a CPU is not mounted and a decoder circuit is added instead of the CPU.

EEPRO from the information processing apparatus of this embodiment
Since the EEPROM does not include a CPU, the operation command for M is not limited to the above-mentioned signals S SC, S CK,
Given by serial communication using SDo, S Di.

Specifically, after S SC is set to “H”, S D is synchronized with the rising edge of the clock of S CK.
o (serial data) is transferred to the EPPROM. The serial data of S Do in data reading is input in the order of a start bit (1 bit), an operation code (7 bits), an address (8 bits), and data (16 bits). On the EEPROM side, the decoder circuit
The start bit is recognized by capturing the S Do "H" at the rising edge of the S CK clock after the S SC "H", and the completion of the instruction input is recognized when the S SC "L". Therefore, after setting SSC to "H",
As long as S Do maintains “L”, the EEPROM side does not recognize the start bit by the input of S CK, and by setting S SC to “L”, acceptance of the command is prohibited and , The SSC level is held at "L".

For example, as shown in FIG. 6, READ (data read), WRITE (data write), ERAL
Serial data including a start bit, an operation code, an address, and data is given to each instruction of (chip erase).

When reading data from the EEPROM,
As shown in FIG. 5A, after S SC is set to “H”, S D is synchronized with the rising edge of the clock of S CK.
o (serial data) is transferred to the EPPROM. Serial data of S Do in the data read is input in the order of a start bit (1 bit), an operation code (7 bits), and an address (8 bits). Data of S Di is transferred from the EEPROM side.

When writing data to the EEPROM, as shown in FIG. 5A, after SSC is set to "H",
S Do is synchronized with the rising edge of the clock of S CK.
(Serial data) is transferred to the EPPROM. Serial data of S Do in data writing is input in the order of a start bit (1 bit), an operation code (7 bits), an address (8 bits), and data (16 bits).

The same is done for each ERAL (chip erase) instruction.

To determine the expansion unit by such serial communication, as shown in FIG. 7, the relationship between the address and the data is used. For example, the address "00
A type code is assigned to the “H” address, and the type of expansion unit is recognized from this data. Address "01
The operating frequency is assigned to the address "H", and the operating frequency is recognized from this data. Frequency switching control of the bus data transfer clock is performed according to the recognized operating frequency. A transfer protocol is assigned to the address "02H", and the transfer protocol is recognized from this data. This transfer protocol recognition request is issued when a special communication method is requested.

In the case of an expansion unit such as an EEPROM that does not require high speed, it is not necessary to recognize the operating frequency and transfer protocol, and data can be read and written by serial communication using the instruction set shown in FIG.

For other expansion units, if necessary, the operating frequency, transfer protocol, memory capacity, etc. are associated with an address, and each specification is recognized from the data of that address to maximize the performance of that expansion unit. It is possible to control for maximum utilization.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the third embodiment of the information processing apparatus of the present invention. In the figure, the same blocks as those in FIG.

This embodiment is the optical block 3 of the first embodiment.
1, a digital signal I / F 61 that takes in an output from a digital signal output device 60 such as an external digital VTR is provided in place of the CCD 32 and the A / D 34.

Even with such a structure, the same effect as that of the first embodiment can be obtained.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing the configuration of the fourth embodiment of the information processing apparatus of the present invention. In the figure, the same blocks as those in FIG.

This embodiment is the optical block 3 of the first embodiment.
1. Instead of the CCD 32, a signal I / F 71 for taking in an output from an analog signal output device 70 such as an external VTR or a camcorder is provided, and the output from the analog signal output device 70 is converted into a digital signal by the A / D 34. Is configured.

Even with such a structure, the same effect as that of the first embodiment can be obtained.

In each of the above-described embodiments, the information processing apparatus having the image processing function for the input image has been described as an example. However, the information processing apparatus including the MPU, the memory, the recording unit, and the external bus interface. It is not necessary to mention that the principles of the invention can be applied to.

[0083]

As described above, according to the information processing apparatus of the first aspect, the communication means communicates between the external expansion device and the control means via the external bus interface. The performance of the external expansion device can be fully exhibited without being restricted by the external bus interface that connects the external expansion device such as the board and the expansion unit.

According to another aspect of the information processing apparatus of the present invention, the detection means uses the signal line connecting the external expansion device and the control means via the external bus interface, and the external expansion device is connected to the external bus interface. Since the connection is detected and the communication means communicates between the external expansion device and the control means by using the signal line of the detection means, it is possible to suppress an increase in the bus lines of the external bus interface.

According to the information processing apparatus of the third aspect, the consistency for maximizing the function of the external expansion device by the control means based on the information obtained by the communication with the external expansion device by the communication means. Since the control method of the external bus interface is changed so as to obtain, the more optimum control can be executed for the expansion device.

According to the information processing apparatus of the fourth to seventh aspects, the performance of the external expansion device can be sufficiently improved without being restricted by the external bus interface for connecting the external expansion device such as the application board and the expansion unit. Can be demonstrated.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing signal connection between a host computer which is an information processing apparatus of the present invention and an expansion unit.

FIG. 2 is a diagram showing a bit configuration of data transmitted and received between the host computer and the expansion unit in FIG.

FIG. 3 is a block diagram showing a configuration of a first embodiment of the information processing apparatus of the present invention and a compression card connected thereto.

4 is a timing chart of signals during a communication operation performed between the information processing apparatus in FIG. 3 and a compression card connected to the information processing apparatus.

FIG. 5 is a timing chart of signals in a read operation and a write operation between the second embodiment of the information processing apparatus of the present invention and an EEPROM connected thereto.

FIG. 6 is a diagram showing the contents of an instruction set for an EEPROM connected to the second embodiment of the information processing apparatus of the invention.

FIG. 7 is a diagram showing a relationship between an address and data for discriminating an expansion unit by a communication operation of a second embodiment of the information processing system of the invention.

FIG. 8 is a block diagram showing the configuration of a third embodiment of the information processing apparatus of the present invention.

FIG. 9 is a block diagram showing the configuration of a fourth embodiment of the information processing apparatus of the present invention.

FIG. 10: CP in a conventional personal computer
It is a conceptual diagram which shows the signal connection of a U board and a memory board.

[Explanation of symbols]

 10, 33 MPU 11 address line 12 data line 17 line (S CK) 18 line (S Do) 19 line (S Di) 20, 41 external bus interface 21 expansion unit 23 line (S CS) 34 A / D 35 digital Signal processing circuit 36 Memory 40 Recording unit 50 Compression card

Claims (7)

[Claims] 1. A function processing unit for executing a predetermined function operation, an external bus interface connecting an external expansion device for executing an expanded function operation, a function operation of the function processing unit, and the external expansion. In an information processing device including a control means for controlling an expanded function operation of the device and an operation of the external bus interface, the external expansion device and the control means communicate via the external bus interface. An information processing apparatus, characterized in that a communication means for providing the information is provided. 2. A detection means for detecting that the external expansion device is connected to the external bus interface by using a signal line connecting the external expansion device and the control means via the external bus interface. 2. The information processing apparatus according to claim 1, wherein the communication unit performs communication between the external expansion device and the control unit by using a signal line of the detection unit. 3. The control means is configured to obtain consistency for maximizing the function of the external expansion device based on information obtained by communication with the external expansion device by the communication means. The information processing apparatus according to claim 1, wherein the control method of the external bus interface is changed. 4. The information processing apparatus according to claim 1, wherein the function processing unit includes a storage unit that stores a program relating to control by the control unit. 5. The function processing means includes an image pickup means for converting a subject image into an image signal, an A / D converter for converting the image signal into a digital signal, and a signal for performing signal processing on the digital signal. 2. A processing means and a display means for displaying the image signal.
The information processing device described. 6. The function processing means comprises an input means for inputting a digital video signal, and a display means for displaying the digital video signal input to the input means. 1. The information processing device according to 1. 7. The information processing apparatus according to claim 6, wherein the input unit is set so that an analog video signal can be input by a switching operation.