JPH08292912A - Memory device and its access method - Google Patents

Abstract

PURPOSE: To provide a memory device which speeds up the processing of the whole continuous access to a memory by enabling a large-capacity memory to be accessed without forcibly fitting the important memory space of a computer system. CONSTITUTION: A system address bus 15 to which the CPU of the computer system is connected and a local address bus to which the memory 9 is connected are separated, and counters 22 and 23 are provided which generate addresses on the local address bus. The device is equipped with a decoder 21 which sets the initial value of an address generated on the system address bus 15 in the counters 22 and 23 and plural logic gates 17-20, and 24. The counters 22 and 23 updates the addresses on the local address in order according to the access of the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device connected to a computer system and a method of accessing the same, and more particularly to accessing a memory device for storing continuous information such as image data.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a computer system to which a conventional memory device of this type is connected. A memory system (memory device) 7 and an external device 8 are connected to the computer system 1. The computer system 1 is a well-known system represented by a personal computer or the like, and a system bus 6 connects a CPU (central processing unit) 2, a system memory 3, a disk 4, a display 5, and the like. As the external device 8, for example, an image scanner that generates a large amount of data, or an A / D
A converter is assumed. The memory system 7 is a device that samples and stores data generated in the external device 8.

FIG. 4 shows the internal structure of the memory system 7. The data generated in the external device 8 is transferred to the DMA (Direct Memory
It is transmitted to the access unit 11 and further written in the memory 9 through the data flow switching unit 12. The DMA unit 11 generates an address to be written in the memory 9 and a WRITE signal (write signal) to the memory 9 in synchronization with the data received from the interface 10. The data flow switching unit 12 switches the bus to the memory 9 depending on whether the external device 8 writes data to the memory 9 or the CPU 2 accesses the memory 9. At the time of writing data from the external device 8 to the memory 9, the data flow switching unit 12 causes the external device 8 to operate by a control signal from the CPU 2 through a control line (not shown).
The data is switched to the side where the data is written in the memory 9.

When the CPU 2 accesses the data thus stored in the memory 9, the CPU 2 sends a control signal through a control line (not shown) to switch the data flow switching unit 12 to the system bus side. Next, the CPU 2 sends the address to which the memory 9 is mapped,
That is, the decoder 13 accesses an address at which the MEMORY ENB signal (memory use permission signal) in FIG. 4 becomes TRUE.

The decoder 13 is composed of a digital comparator. In this example, when 3 bits of the 21st bit to the 23rd bit in the system address bus match the bit string defined in the decoder 13, the MEMORY ENB. The signal is configured to be TRUE. The other bits in the system address bus, that is, the 1st to 20th bits, are stored in the memory 9 as they are.
A memory element and a bit are selected by a decoder (not shown) included in the memory 9.
Since only word access is assumed in this example, the 0th bit is not used for addressing.

When the MEMORY ENB signal is TRUE, the CPU 2
The WRITE signal or the READ signal (read signal), that is, the system WR signal or the system RD signal in FIG. 4 passes through the AND gate (AND circuit) 15 or 16 and the memory 9 through the data flow switching unit 12. Reach When the CPU 2 reads data from the memory 9, the READ signal reaches the memory 9 through the above-mentioned path, so that the data read from the memory 9 is given to the system data bus through the bus transceiver 14. When the CPU 2 writes data to the memory 9, the data on the system data bus is given to the memory 9 through the bus transceiver 14.

The bus transceiver 14 is a three-state bidirectional buffer, and the switching of the data input / output direction is performed by a system WR signal. Further, the output of the bus transceiver 14 becomes high impedance when the MEMORY ENB signal is FALSE (false), so that the system bus and the local data bus do not affect each other except when accessing the memory 9. It is configured.

[0008]

In the above conventional example, C is used.
The address space of PU2 is 23 bits from bit 1 to bit 23, that is, 8 M words, of which the address space occupied by the memory 9 is bit 1 to bit 20.
Up to 20 bits, or 1M words. However, as shown in FIG. 3, since the system memory 3 or the video memory included in the display 5 is arranged in the address space of the CPU 2, it is not possible to allocate 1/8 of the entire address space to the memory 9. There can be possible computer systems 1.

On the other hand, in the case where the memory system 7 is intended to support various computer systems, it is necessary to allocate the memory 9 to an address space that is not commonly used in all computer systems, but this is extremely difficult. Is.

Further, when a plurality of memory systems 7 are connected to one computer system, the occupancy rate 1/8 with respect to the entire address space increases to 2/8, 3/8, ... The address space that can be used by the system memory 3 is limited.

Conventionally, there is a FIFO memory (first-in first-out memory) as a means for narrowing the occupied address space. However, in the FIFO memory, the stored data can be read from any position. Is not possible, so it is not suitable for access by the CPU.

Another problem is as follows. When the data stored in the memory 9 is continuous information such as bitmap image data, adjacent addresses are often read continuously. When reading continuously, the CPU 2 increases the read address by two. In such a case, a register that stores an address for normal reading is prepared, and one word of data is read by accessing the address stored in this register. When this reading is completed, the next reading is prepared and the register is incremented by 2. In this way, when accessing continuous local addresses, since continuous reading is performed while performing addition processing, the speed of the entire reading processing becomes slow.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and an object thereof is to access a large capacity memory without occupying the valuable memory space of a computer system. (EN) It is possible to provide a memory device and a method of accessing the same, which enables the continuous access of a memory at a high speed by making it unnecessary to update the address by the CPU when accessing the continuous local address.

[0014]

To achieve the above object, the device of the present invention comprises a memory means capable of storing continuous information, and a system bus connected to the memory means for transmitting an address to the memory means. Has separate address transmitting means, local address generating means for giving an address to the address transmitting means, and initialization means for setting an initial value of an address generated through the system bus to the local address generating means. However, the local address generating means updates and generates an address each time the memory means is accessed.

The present invention, as one form thereof, can be characterized in that the local address generating means comprises a counter.

As another form of the present invention, the initialization means may be composed of a decoder and a plurality of logic gates.

Also, the method of the present invention is an access method for a memory device having a memory means and a local address bus connected to the memory means and separated from the system bus. An initializing step of setting a value in the counter; and a local address updating step of updating the address by the counter each time the memory means is accessed and supplying the updated address to the memory means through the local address bus. Is characterized by.

[0018]

In the present invention, for example, the CPU is A002H in the I / O space.
And after presetting the local address to A004H, all data in the memory can be accessed by simply reading or writing A000H. Therefore, the I / O space required for the CPU to access the 1M word memory is only 3 of A000H, A002H and A004H.
Is a word. Therefore, according to the present invention, it is possible to access a large capacity memory without occupying the valuable memory space of the computer system.

Further, according to the present invention, when accessing consecutive local addresses, the CPU has the same I / O address A000.
Only H needs to be accessed, and the CPU does not have to perform address update processing. As a result, according to the present invention, the processing of the entire continuous access to the memory becomes faster.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the configuration of a memory system according to an embodiment of the present invention. The internal configuration of the computer system to which the memory system of this example is connected is the same as that of the conventional example of FIG. 3, and the components of the same functions as those of the conventional example of FIG. 4 are the same in FIG. It is attached with a code.

As shown in FIG. 1, the memory system 7 of this embodiment has the same memory 9, interface 10, DMA section 11 and data flow switching section 12 as in the conventional example.
Besides, AND gates 17 and 18, OR gate (OR circuit) 19, AND gate 20, decoder 21, counters 22 and 23, AND gates 24 and 2 according to the present invention.
5, 26 and a bus transceiver 27. The process until the data generated in the external device 8 is stored in the memory 9 is the same as that in the conventional example described above, and thus the description thereof is omitted.

Prior to continuous reading of data from the memory 9 which is a memory means, the CPU 2 sets the read start address on the memory 9 to the counters 22 and 23 which are local address generating means. This set consists of the system WR signal and the system I / O EN on the system bus.
Set the B signal to TRUE, for example A002 in the I / O (input / output) space.
It is performed by a write operation for H (H represents a hexadecimal number) and A004H (see FIG. 2).

The decoder 21 is a system address BIT-
If 1 (bit 1) to BIT-15 (bit 15) are given and this address is A002H above, the PRESET LOW ENB signal (preset low enable signal) in Fig. 1 becomes TRUE. Such a digital comparator. Similarly, the address given to the decoder 21 is
If it is A004H, the PRESET HIGH ENB signal (preset high enable signal) becomes TRUE. Therefore, C
PU2 has BIT- of preset address in A002H of I / O space.
When BIT-15 is written from 1, the PRESET LOW ENB signal becomes TRUE, and the writing to the I / O space is AN.
The output I / OWR signal from the D gate 17 also becomes TRUE. As a result, the output of the AND gate 20, that is, the counter 2
Since the LOAD input of 2 becomes TRUE, the preset addresses BIT-1 to BIT-15 appearing on the system data bus are simultaneously loaded into the counter 22.

Similarly, the CPU 2 uses the A004H in the I / O space.
Writing to the PRESETHIGH ENB signal causes the
Since it becomes E and the output of the AND gate 24 also becomes TRUE,
Counter 23 preset address BIT-16 to BIT-20
Is loaded. At the time of this loading, the local address bus which is the address transmission means in FIG.
The value that I / O written to A002H and A004H by PU2 appears. Therefore, each register in the counters 22 and 23, the decoder 21, the AND gates 17 and 2
0, 24 and OR gate 19 constitute the initialization means of the present invention.

Next, the CPU 2 sets the system I / O ENB signal and the system RD signal on the system bus to TRUE to read (READ) the memory 9 from, for example, the A000H address of the I / O space. The decoder 21 is also a digital comparator such that the MEMORY DATA ENB signal (memory data enable signal) in FIG. 1 becomes TRUE when the given address is A000H.
For I / O reading, the output of AND gates 18 and 26 is TR
Become a UE. That is, since the read signal to the memory 9, that is, the local RD signal becomes TRUE, the data in the memory 9 designated by the local address output from the counters 22 and 23 appears on the local data bus. This data is supplied to the system data bus via the bus transceiver 27 and reaches the CPU 2.

In the above-mentioned data read operation for the memory 9 by the CPU 2, the output I / O RD signal of the AND gate 18 once becomes TRUE, so that the OR gate 19
Output is TRUE. Since the output of the OR gate 19 is the clock input of the counter 22, the TRUE of the output causes the register in the counter 22 to be incremented by +1. Since the output of the counter 22 is BIT-0 connected to BIT-1 of the local address bus, the local address is incremented by +2 in accordance with +1 of the register in the counter 22. In this way, the local address given to the memory 9 through the local address bus is CP.
After one access by U2, it is incremented +2,
I will prepare for the next access.

Since the counter 22 is a 15-bit counter, a CARRY signal (carry signal) is generated when a count exceeding 15 bits occurs. This CA
Since the RRY signal is connected to the clock input of the counter 23, the counters 22 and 23 together form a 30-bit counter. However, the lower 20 bits of these 30 bits are BI to BI of the local address bus.
It is connected to the T-20.

Writing to the memory 9 by the CPU 2 (WRI
In the case of (TE) operation, the counters 22 and 23 are also the same as above.
Is incremented, the local address is automatically incremented, and the address is prepared for the next write operation.

With the above configuration, the I / O space from the address A000H to A004H as seen from the CPU 2 is shown in FIG.
Looks like. That is, the CPU 2 is the I / O space
After presetting the local addresses in A002H and A004H, all the data in the memory 9 can be accessed simply by continuing to read (read) or write (write) A000H.

The decoder 21 of the above embodiment includes a digital comparator, but it is also possible to set the bit string to be the address comparison target by, for example, a DIP switch. In this case, A0 of the above embodiment
The I / O space from 00H to A004H can also be moved arbitrarily with the DIP switch.

In the above embodiment of the present invention, the CPU 2
The I / O space required to access the memory 9 of 1 M words (2 M bytes) is only 3 words of A000H, A002H and A004H. Further, since the local address presetting mechanism is provided, access can be started from any local address in the 1M word. Therefore, according to the present invention, it becomes possible to access a large capacity memory without occupying the valuable memory space of the computer system.

Further, when accessing continuous local addresses, the CPU 2 only needs to access the same I / O address, that is, A000H in the above embodiment, so that C
It is not necessary to perform address update processing by the PU. Therefore, according to the present invention, the processing of the entire continuous access of the memory becomes faster.

Further, the computer system often includes a well-known DMAC (Direct Memory Access Controller). This DMAC has a mode of continuously accessing one I / O address.
If the present invention is applied, it is possible to access a large capacity memory by DMAC control using that mode.

Generally speaking, it is not considered that there is no unused I / O space of 3 words in a computer system. Therefore, the memory device to which the present invention is applied has the address space in all computer systems. Can be used without squeezing.

[0036]

As described above, according to the present invention, for example, after the CPU presets the local address in A002H and A004H of the I / O space, it only reads or writes A000H to save the memory. Since all data can be accessed, the I / O space required for the CPU to access the 1M word memory is A000HA.
With only 3 words of 002H and A004H, it is possible to access a large amount of memory without occupying the valuable memory space of the computer system.

Further, according to the present invention, when the continuous local addresses are accessed, the CPU only needs to access the same I / O address, so that it is not necessary to perform the address update processing by the CPU. The processing of the entire continuous access to the result memory becomes faster.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory system according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the contents of an I / O space from addresses A000H to A004H viewed from the CPU in one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a general computer system to which the present invention can be applied.

FIG. 4 is a block diagram showing a configuration example of a conventional memory system.

[Explanation of symbols]

 1 Computer System 2 CPU 3 System Memory 6 System Bus 7 Memory System 8 External Equipment 9 Memory 10 Interface 11 DMA Section 12 Data Flow Switching Section 17, 18, 20, 24, 25, 26 AND Gate 19 OR Gate 21 Decoder 22, 23 Counter 27 bus transceiver

Claims (4)

[Claims] 1. A memory means capable of storing continuous information, an address transmitting means connected to the memory means for transmitting an address to the memory means and separated from a system bus, and an address is given to the address transmitting means. The local address generating means, and the initialization means for setting an initial value of an address generated through the system bus to the local address generating means, the local address generating means is an address for each access to the memory means. A memory device characterized by being generated by updating. 2. The memory device according to claim 1, wherein the local address generating means comprises a counter. 3. The memory device according to claim 1, wherein the initialization unit includes a decoder and a plurality of logic gates. 4. A method of accessing a memory device having a memory means and a local address bus connected to the memory means and separated from a system bus, wherein an initial value of an address generated through the system bus is set in a counter. A memory device comprising an initialization step and a local address updating step of updating an address by the counter each time the memory means is accessed and supplying the updated address to the memory means through the local address bus. Access method.