JPH08288625A - Method for connecting circuit board and electronic circuit device using it - Google Patents

Method for connecting circuit board and electronic circuit device using it

Info

Publication number
JPH08288625A
JPH08288625A JP9219295A JP9219295A JPH08288625A JP H08288625 A JPH08288625 A JP H08288625A JP 9219295 A JP9219295 A JP 9219295A JP 9219295 A JP9219295 A JP 9219295A JP H08288625 A JPH08288625 A JP H08288625A
Authority
JP
Japan
Prior art keywords
electroless
circuit board
metallization
plating
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9219295A
Other languages
Japanese (ja)
Inventor
Tomoko Yoda
智子 依田
Takashi Inoue
隆史 井上
Ryohei Sato
了平 佐藤
Kiyoshi Matsui
清 松井
Toshihiko Ota
敏彦 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9219295A priority Critical patent/JPH08288625A/en
Publication of JPH08288625A publication Critical patent/JPH08288625A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE: To prevent the segregation of Pb on the boundary between an electroless-plated Ni-B metallized pad containing Pb and formed on a circuit board and parts by connecting the parts to the metallized pad by forming an Ni-Sn alloy of an Sn-based brazing material. CONSTITUTION: The surface of a conductor substrate is pretreated by soft etching the surface with an alkaline solution, neutralizing the surface with an acid, and activating the surface with a liquid containing a lead compound after degreasing the surface. Then, after an electroless-plated Ni-B film 5 is formed, an electroless-plated Au film 15 is formed and the film 15 is metallized. After the film 15 is metallized, the adhesion between the joined metallic layers 5 and 15 is improved by mutually diffusing the films 5 and 15 to each other. Then I/O pins 17 mounted with Au-20Sn are positioned on the metallic layers formed in the conductor section of the substrate and the pins 17 are heated. Therefore, the segregation of Pb on the boundary between the pins 17 and metallic layer can be prevented, because the Pb can be diffused in the formed intermetallic compound layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は回路基板と部品の接続方
法に係り、特に、回路基板とI/Oピン等の電子部品との
高接合強度確保と信頼性向上に好敵な接続方法、および
これを用いた電子回路装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting a circuit board and components, and more particularly to a method for connecting a circuit board and an electronic component such as an I / O pin, which is suitable for securing high joint strength and improving reliability. And an electronic circuit device using the same.

【0002】[0002]

【従来の技術】大形計算機をはじめとする電子回路装置
は、プリント板やセラミック板(以下これらを回路基板
と呼ぶ)上に、多数の半導体素子等電子回路部品やI/O
ピン等の電子部品を搭載し電子回路を形成している。こ
れら部品を搭載する代表面な方法は以下のとうりであ
る。回路基板上にはんだ接続用のメタライゼーションパ
ッドを形成し、電子回路部品には電解用の金属端子をそ
の他の接合部材には接合用金属層を形成する。その後、
基板と電子部品間にはんだ材を介し接続温度まで加熱す
ることによりメタライゼーションとの間にはんだ合金を
形成させ接続する。このメタライゼーション材料とし
て、従来技術では特開平1−1060号公報に記載のよ
うに、基板のモリブデン導体部上にニッケル/金層を設
ける方法が述べられている。このメタライゼーション形
成方法として、スパッタ法、めっき法が代表的である。
スパッタ法の特徴は、緻密で下地との密着性の高い膜が
得られる点であるが、メタライゼーションのパタ−ン分
離工程が必要なため、コスト高になる欠点がある。めっ
き法の特徴は、低コストで成膜が可能な点であるが、基
板表面と密着力を得る工程が必要となる。めっき法の中
で電気めっき法は、高純度の皮膜が得られるが、それぞ
れの被めっきパタ−ンに電極またはそれに代る配線の取
り付けができない場合、電気的に独立したパタ−ン上に
は膜形成できない欠点がある。一方、無電解めっき法
は、目的の金属以外の不純物が、必須成分である添加剤
等の起源によりめっきと同時に析出してしまう欠点を持
つが、複雑で微細な独立パタ−ン上に均一に膜形成が可
能であり、最も低コストなプロセスである。以上の理由
より、回路基板上の微細な独立パタ−ンに対し無電解め
っき法を用いメタライゼーションを形成した。ここで、
電子部品に用いられる無電解ニッケルめっきについて説
明する。代表的なめっきには無電解ニッケル−ホウ素合
金めっきおよび無電解ニッケル−リン合金めっきがあ
る。この両者の特徴を比較して、融点が高くはんだ付け
性が良好で低温めっきのできる無電解ニッケル−ホウ素
合金めっきを採用した。この方法で得られるめっき膜
は、ホウ素含有量が0.5重量パ−セント以下と少なく
比較的ニッケル純度の高い膜を与える。しかし、無電解
ニッケル−ホウ素合金めっき(以下Ni−Bめっきと記
す)には次の欠点がある。めっき液中に液の安定化や選
択析出性を目的として添加されている鉛(実際は鉛化合
物として)が、膜形成と同時にめっき膜中に取り込まれ
る。同様に、無電解Ni−Bめっき反応を開始させるた
めの活性化処理液中にも、液の安定化の目的で鉛(実際
は鉛化合物)が添加されていため被めっきパタ−ンに吸
着した活性化粒子にもPbが含まれ、この結果、めっき
膜中にPbが含まれる。これらの理由で、めっき膜は活
性化処理液起源および無電解Ni−Bめっき液起源の鉛
を含む。無電解Ni−Bめっき方法で形成したニッケル
層の上に、表面保護の目的で無電解金めっきし、メタラ
イゼーションを形成した。
2. Description of the Related Art Electronic circuit devices such as large-scale computers are equipped with a large number of semiconductor circuit elements such as semiconductor elements and I / O on a printed board or a ceramic board (hereinafter referred to as a circuit board).
An electronic circuit is formed by mounting electronic parts such as pins. The representative method of mounting these parts is as follows. A metallization pad for solder connection is formed on a circuit board, a metal terminal for electrolysis is formed on an electronic circuit component, and a metal layer for joining is formed on other joining members. afterwards,
A solder alloy is formed between the substrate and the electronic component by heating through a solder material to a connection temperature to form a connection with the metallization. As this metallization material, the prior art describes a method of providing a nickel / gold layer on a molybdenum conductor portion of a substrate, as described in JP-A-1-1060. Typical methods for forming this metallization are a sputtering method and a plating method.
A characteristic of the sputtering method is that a dense film having high adhesion to the underlying layer can be obtained, but it has a drawback that the cost is high because a patterning step of metallization is required. The feature of the plating method is that it is possible to form a film at low cost, but it requires a step of obtaining adhesion to the substrate surface. Among the plating methods, electroplating provides a high-purity film, but if electrodes or wiring in place of them cannot be attached to each plated pattern, then an electrically independent pattern cannot be used. There is a drawback that a film cannot be formed. On the other hand, the electroless plating method has a drawback that impurities other than the target metal are deposited at the same time as the plating due to the origin of the additive which is an essential component, but it is uniformly distributed on a complicated and fine independent pattern. Film formation is possible and it is the lowest cost process. For the above reason, the metallization was formed on the fine independent pattern on the circuit board by the electroless plating method. here,
The electroless nickel plating used for electronic parts will be described. Representative platings include electroless nickel-boron alloy plating and electroless nickel-phosphorus alloy plating. By comparing the characteristics of both of them, electroless nickel-boron alloy plating having a high melting point and good solderability and capable of low temperature plating was adopted. The plating film obtained by this method has a boron content of 0.5% by weight or less and a relatively high nickel purity. However, electroless nickel-boron alloy plating (hereinafter referred to as Ni-B plating) has the following drawbacks. Lead (actually as a lead compound) added to the plating solution for the purpose of stabilizing the solution and selectively depositing is taken into the plating film at the same time as the film formation. Similarly, since lead (actually a lead compound) is added to the activation treatment solution for starting the electroless Ni-B plating reaction for the purpose of stabilizing the solution, the activity adsorbed on the plated pattern is The chemical conversion particles also contain Pb, and as a result, the plating film contains Pb. For these reasons, the plating film contains lead derived from the activation treatment solution and electroless Ni-B plating solution. On the nickel layer formed by the electroless Ni-B plating method, electroless gold plating was performed to form a metallization for the purpose of surface protection.

【0003】この方法によりメタライゼーションを形成
した回路基板上に、多数電子部品を搭載し、電子回路装
置を組立てる方法として、特開平1−124304号公
報が開示されている。この記載によると回路基板の組立
ては、基板にI/Oピン半導体素子、封子キャップの順で
接続される。I/Oピンを接続するろう材、半導体素子を
接続するろう材、封子キャップを接続するろう材の順に
融点の高い材料が用いられ、組立て工程で他のろう材を
溶かさずに作業する条件を満たすI/Oピン接続用ろう材
として、Au−Geろう材が示されている。356℃〜
450℃の融点を有するAu−Ge系ろう材を搭載した
I/Oピンをろう材の融点以上に加熱し、その融液がメタ
ライゼーションに濡れ拡がると同時にニッケルと反応
し、Ni−Ge金属間化合物を形成する。この接合方法
によれば、多層セラミック回路基板の低残留応力、高強
度接続、高い信頼性が得られる。
Japanese Unexamined Patent Publication No. 1-124304 discloses a method of assembling an electronic circuit device by mounting a large number of electronic components on a circuit board having metallization formed by this method. According to this description, the circuit board is assembled by connecting the I / O pin semiconductor device and the sealing cap to the board in this order. The brazing material that connects the I / O pins, the brazing material that connects the semiconductor elements, and the brazing material that connects the sealing cap are used in this order.The materials with the highest melting points are used. Au-Ge brazing filler metal is shown as an I / O pin connecting brazing filler metal that satisfies the above conditions. 356 ℃ ~
An Au-Ge brazing material having a melting point of 450 ° C was mounted.
The I / O pin is heated above the melting point of the brazing material, and the melt wets and spreads on the metallization and at the same time reacts with nickel to form a Ni-Ge intermetallic compound. According to this joining method, low residual stress, high strength connection, and high reliability of the multilayer ceramic circuit board can be obtained.

【0004】従来技術を組合せて、I/Oピンろう材にA
u−Geろうをメタライゼーション材料にPbを含む無
電解Ni−Bめっき膜を採用しI/Oピン接合を行った。
接合状態を評価した結果、I/Oピン接合強度はきわめて
低く無電解Ni−Bめっきメタライゼーションと接合の
際に生成した金属間化合物との接合界面で破断する不良
現象が多発した。この多層セラミック基板がその後の組
立て工程や修正・修理等で行われる回路基板との脱着に
耐えられないものであった。
Combining conventional technologies, I / O pin brazing filler metal
I / O pin bonding was performed by using an electroless Ni-B plating film containing Pb as a metallization material of u-Ge solder.
As a result of evaluating the bonding state, the I / O pin bonding strength was extremely low, and a failure phenomenon frequently occurred at the bonding interface between the electroless Ni—B plating metallization and the intermetallic compound generated during bonding. This multilayer ceramic substrate cannot withstand the attachment and detachment with the circuit substrate performed in the subsequent assembling process, correction and repair.

【0005】本発明では、上記従来技術の欠点を解決す
るため、Pbを含む無電解Ni−Bめっきメタライゼー
ションに接合した際、接合界面にPb編析を起さない十
分な接合強度の得られる好適なろう材を選定し問題解決
を図った。
In the present invention, in order to solve the above-mentioned drawbacks of the prior art, when bonded to an electroless Ni-B plating metallization containing Pb, sufficient bonding strength can be obtained without causing Pb segregation at the bonding interface. A suitable brazing material was selected to solve the problem.

【0006】[0006]

【発明が解決しようとする課題】上記従来技術により、
回路基板上にPbを含む無電解Ni−Bめっき膜メタラ
イゼーションを形成し、Au−Geろう材を用いてI/O
ピン付けを行った。接合の後、I/Oピンの引張り試験を
行い接合状態を評価した。その結果、接合強度が低く、
無電解Ni−Bめっきメタライゼーションと接合の際に
生成した金属間化合物との接合界面で破断する不良現象
が多発した。そのため、I/Oピンを備えた電子回路装置
のコネクタへ挿抜に対して十分な強度が得られず、組立
工程や使用中の障害となっていた。この原因究明のため
以下の実験を行った。接合不良を起こしたI/Oピンのピ
ン側および基板側破断面をマイクロオージェ分析し、被
断面に存在する原素の種類を確認した。その結果、I/O
ピン側の破断面最表面よりNi−Ge化合物層とPbの
存在が確認され、基板側からはNiめっき層のみの存在
が確認された。I/Oピン側破断面の最表面を深さ方向に
約150Åをスパッタエッチングして取り除き、同様の
分析を行ったところPbは存在していなかった。この結
果から、I/Oピンの被断はメタライゼーションと金属間
化合物との界面でおこり、偏析したPbは、接合界面に
薄層に存在していることが判明した。また、接合材料の
分析を行った結果、Pbは無電解Ni−Bめっきメタラ
イゼーション以外、すなわち、ろう材中、I/Oピン中、
Auめっき膜中および基板表面中には含まれていなかっ
たため、偏析を起こしたPbの起源は無電解Ni−Bめ
っき膜と断定した。以上の解析により、接合強度劣化
は、無電解Ni−Bめっき膜に含まれる鉛の接合界面偏
析が原因で起こることが判った。
According to the above conventional technique,
Electroless Ni-B plating film metallization containing Pb is formed on the circuit board and I / O is performed using Au-Ge brazing material.
Pinned. After joining, a tensile test of the I / O pin was performed to evaluate the joined state. As a result, the bonding strength is low,
A failure phenomenon frequently occurred at the bonding interface between the electroless Ni-B plating metallization and the intermetallic compound generated during bonding. Therefore, sufficient strength cannot be obtained for insertion / removal into / from the connector of the electronic circuit device having the I / O pin, which is an obstacle during the assembly process and during use. The following experiment was conducted to investigate the cause. Micro Auger analysis was performed on the pin-side and substrate-side fractured surfaces of the I / O pin that caused the bonding failure, and the types of the elements existing on the cross-sectional surface were confirmed. As a result, I / O
The existence of the Ni-Ge compound layer and Pb was confirmed from the outermost surface of the fracture surface on the pin side, and the existence of only the Ni plating layer was confirmed from the substrate side. The outermost surface of the fracture surface on the I / O pin side was removed by sputter etching to remove about 150 Å in the depth direction, and the same analysis was performed. As a result, Pb was not present. From this result, it was found that the disconnection of the I / O pin occurred at the interface between the metallization and the intermetallic compound, and the segregated Pb existed in a thin layer at the bonded interface. Also, as a result of analyzing the bonding material, Pb was found to be other than electroless Ni-B plating metallization, that is, in the brazing material, in the I / O pin,
Since it was not contained in the Au plating film and the substrate surface, the origin of segregated Pb was determined to be an electroless Ni-B plating film. From the above analysis, it has been found that the deterioration of the bonding strength is caused by segregation of the bonding interface of lead contained in the electroless Ni-B plating film.

【0007】本発明の目的は、Pbを含む無電解Ni−
Bめっき膜メタライゼーションに対して、I/Oピン等部
品の接合強度低下の原因である接合界面のPb偏析を起
こさない好適なろう材を選定することにより、十分な接
合強度を有する回路基板と部品との接合方法およびこれ
を用いた電子回路装置を提供することにある。
An object of the present invention is to electroless Ni-containing Pb.
By selecting a suitable brazing material that does not cause Pb segregation at the bonding interface, which is the cause of the reduction in bonding strength of parts such as I / O pins, for B plating film metallization, a circuit board having sufficient bonding strength can be obtained. An object is to provide a method for joining parts and an electronic circuit device using the same.

【0008】[0008]

【課題を解決するための手段】上記課題は回路基板上に
形成されたPbを含む無電解Ni−Bめっきメタライゼ
ーションパッドに、前記回路基板上に接続する部品をS
n系ろう材で主にNi−Sn合金形成により接続するこ
とを特徴とする接合方法により達成される。
SUMMARY OF THE INVENTION The above object is to provide a component for connecting on the circuit board to an electroless Ni-B plating metallization pad containing Pb formed on the circuit board.
This is achieved by a joining method characterized by connecting with an n-based brazing material mainly by forming a Ni—Sn alloy.

【0009】[0009]

【作用】本発明における作用を図を参照しながら説明す
る。
The operation of the present invention will be described with reference to the drawings.

【0010】回路基板上に形成されたPbを含む無電解
Ni−Bめっきメタライゼーションパッドに対して、接
合するろう材がGe系とSn系の違いにより接合強度が
異なる原因を説明する。まず、従来技術により、Au−
Geろう材で接合した場合のI/Oピンの接合断面模式図
を図1に示す。No.1はI/Oピン、No.2は回路基板、No.
3はAu−Geろう材、No.4はAu−Ge金属間化合
物層、No.5は無電解Ni−Bめっきメタライゼーショ
ン、No.6は基板上電極用パッド、No7はスル−ホ−
ルである。図1中の接合界面部分の拡大図を図2に示
す。分析の結果、Ni−Ge金属間化合物層4の中でメ
タライゼーションとの界面にはNi3Ge金属間化合物
8が生成する。同様に、Au−Snろう材を無電解Ni
−Bめっきメタライゼーションに接合した場合の、接合
部の接合界面部分の拡大図を図3に示す。分析の結果よ
り、Ni−Sn金属間化合物層9の中でメタライゼーシ
ョンとの界面には金属間化合物Ni3Snが生成するこ
とを確認した。そこで、接合界面に成生する金属間化合
物Ni3SnおよびNi3Geに着目し、接合温度でのそ
れぞれの化合物に対するPb金属の拡散挙動を以下の実
験により調べた。表面を鏡面研磨した金属間化合物Ni
3Sn、Ni3Geに対し数ミクロン厚さのPb蒸着を行
い、この試験片をそれぞれのろう付温度に1時間保持し
て、Pbを拡散させた。その後、拡散せずに表面に残っ
たPb金属をケミカルエッチングにより除去し、金属間
化合物表面の深さ方向へのPbの存在をSIMS(Seco
ndary Ion Mass Spectroscopy:二次イオン質量分光分
析)により測定した。この結果を表1に示す。
The reason why the bonding strength of the brazing material to be bonded to the electroless Ni-B plating metallization pad containing Pb formed on the circuit board is different depending on the difference between Ge-based and Sn-based will be explained. First, according to the conventional technique, Au-
FIG. 1 shows a schematic cross-sectional view of the I / O pins when they are joined with a Ge brazing material. No. 1 is I / O pin, No. 2 is circuit board, No.
No. 3 is Au-Ge brazing filler metal, No. 4 is Au-Ge intermetallic compound layer, No. 5 is electroless Ni-B plating metallization, No. 6 is electrode pad on substrate, No. 7 is through-hole.
It is. An enlarged view of the bonded interface portion in FIG. 1 is shown in FIG. As a result of the analysis, in the Ni—Ge intermetallic compound layer 4, Ni 3 Ge intermetallic compound 8 is generated at the interface with the metallization. Similarly, the Au-Sn brazing material is replaced with electroless Ni.
FIG. 3 shows an enlarged view of the joining interface portion of the joining portion when joined to the -B plating metallization. From the result of the analysis, it was confirmed that the intermetallic compound Ni 3 Sn was generated at the interface with the metallization in the Ni—Sn intermetallic compound layer 9. Therefore, attention was paid to the intermetallic compounds Ni 3 Sn and Ni 3 Ge generated at the bonding interface, and the diffusion behavior of Pb metal with respect to each compound at the bonding temperature was examined by the following experiment. Intermetallic compound Ni with mirror-polished surface
Pb was vapor-deposited with a thickness of several microns on 3 Sn and Ni 3 Ge, and the test pieces were held at the respective brazing temperatures for 1 hour to diffuse Pb. Then, the Pb metal remaining on the surface without being diffused is removed by chemical etching, and the presence of Pb in the depth direction of the intermetallic compound surface is confirmed by SIMS (Seco
ndary Ion Mass Spectroscopy). Table 1 shows the results.

【0011】[0011]

【表1】 [Table 1]

【0012】Pbの拡散挙動は両金属間化合物に対して
全く異ることが判る。Au−Geろう材を用いてI/Oピ
ン接合した際に、接合界面に生成するNi3Ge金属間
化合物に対してはPbは全く接散しないのに対し、Au
−Snろう材を用いた場合接合界面に生成するNi3
e金属間化合物に対しては、Pbは25nmも拡散す
る。 また、Pb偏析によるI/Oピン接合強度劣化の原
因を接合に関わる金属とPbのそれぞれの相性を合金の
状態図により考察した。図4と図5はそれぞれ、Ni−
Pb2元系状態図およびNi−Ge2元系状態図(Thad
deus B. Massalski,Ed.; BINARY ALLOY PHASE DIAGRAMS
1986)を示している。Ni−Pb状態図から判るよう
に接合温度400℃付近ではPbは極微量Ni中に固溶
するが、室温では全く固溶しない。同様にNi−Ge状
態図から、PbはGeに対しても、室温から接合温度付
近で全く固溶しない。したがって、回路基板組立ての温
度条件でPbはNiおよびGeと安定な金属間化合物も
しくは合金として存在しない。そのため、ろう材中のG
eは接合時にNiとNi−Ge合金(金属間化合物)を
形成し、PbとGe−Pb合金化しない。
It can be seen that the diffusion behavior of Pb is completely different for both intermetallic compounds. When I / O pin bonding is performed using an Au-Ge brazing material, Pb does not diffuse at all to the Ni 3 Ge intermetallic compound generated at the bonding interface, whereas Au does not diffuse.
-Ni 3 G generated at the bonding interface when Sn brazing material is used
ePb diffuses as much as 25 nm for the intermetallic compound. In addition, the cause of deterioration of the I / O pin joint strength due to Pb segregation was examined by the phase diagram of the alloy for the compatibility between the metals involved in the joint and Pb. 4 and 5 show Ni-
Pb binary system phase diagram and Ni-Ge binary system phase diagram (Thad
deus B. Massalski, Ed .; BINARY ALLOY PHASE DIAGRAMS
1986). As can be seen from the Ni-Pb phase diagram, Pb dissolves in a very small amount of Ni near the joining temperature of 400 ° C, but does not dissolve at all at room temperature. Similarly, from the Ni-Ge phase diagram, Pb does not form a solid solution with Ge at room temperature to around the bonding temperature. Therefore, Pb does not exist as a stable intermetallic compound or alloy with Ni and Ge under the temperature condition of circuit board assembly. Therefore, G in the brazing material
e forms a Ni—Ge alloy (intermetallic compound) at the time of joining and does not form a Pb—Ge—Pb alloy.

【0013】以上の考察と実験結果より、I/Oピン接合
の際Ni3Ge金属間化合物の生成が、無電解Ni−B
めっきメタライゼーションに含まれるPbの拡散バリア
−となり、メタライゼーションと金属間化合物の間にP
b偏析を起こすことが明らかとなった。その上、接合界
面にはPb偏析に伴うボイドやクラック等が発生し、接
合状態劣化が原因でI/Oピン接合強度の低下をまねい
た。これに対して、Au−Sn系ろう材接合の場合、接
合界面に生成するNi3Sn金属間化合物中をPbが拡
散できる。そのため、無電解Ni−Bメタライゼーショ
ンがSn系ろう材を用いたPbを含んでいても、I/Oピ
ン接合は、接合界面にPbは偏析せずこれに伴う接合状
態劣化を起こさないため十分なI/Oピン接合強度を有す
る。
From the above consideration and experimental results, the formation of Ni 3 Ge intermetallic compound at the time of I / O pin joining is caused by electroless Ni-B.
It acts as a diffusion barrier for Pb contained in the plating metallization, and P between the metallization and the intermetallic compound.
It became clear that b segregation occurs. In addition, voids, cracks, etc. were generated at the bonding interface due to Pb segregation, and the deterioration of the bonding state caused the I / O pin bonding strength to decrease. In contrast, in the case of Au-Sn based brazing material bonding, the Ni 3 Sn intermetallic compound that generates at the bonded interface Pb can diffuse. Therefore, even if the electroless Ni-B metallization contains Pb using the Sn-based brazing filler metal, the I / O pin bonding is sufficient because the Pb does not segregate at the bonding interface and the bonding state is not deteriorated. Has excellent I / O pin bonding strength.

【0014】このように、無電解Ni−Bめっきメタラ
イゼーション中のPbが、接合時に形成される金属間化
合物層を拡散できるような、メタライゼーションとろう
材の組み合を選択することより、接合界面へのPb偏析
を解消しI/Oピンの接合強度低下を防止することができ
る。
Thus, by selecting the combination of the metallization and the brazing material so that Pb in the electroless Ni-B plating metallization can diffuse the intermetallic compound layer formed at the time of joining, It is possible to eliminate Pb segregation at the interface and prevent a decrease in the bonding strength of the I / O pin.

【0015】[0015]

【実施例】以下、本発明の一実施例について、回路基板
とI/Oピンの接合方法を図面を参照しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the method of joining a circuit board and an I / O pin with reference to the drawings.

【0016】(実施例1)図6はPbを含む無電解Ni
−BめっきメタライゼーションにSn系ろう材を用いて
I/Oピン付けした本発明の実施例を示した接合部の断面
図で、図中、11は多層セラミック基板、12はSn2
0重量%Au80重量%の成分組成のろう材、9は金属
間化合物層、5は無電解Ni−Bめっきメタライゼーシ
ョン、6は回路基板表面の導体部、7はスルーホールで
ある。図8は、Au20Snろう材によってI/Oピンを
接続した本発明の実施例である回路基板を組み立てた電
子回路装置の概略を示した斜視図である。本実施例の電
子回路装置は、上記の方法で接続したI/Oピン1を有す
る多層配線基板11に複数個の半導体素子18を配置
し、この半導体素子上に熱伝導中継部材19を載せ、こ
の中継部材上から、多層配線基板11にこれを覆うキャ
ップ20を載置し、このキャップ20の上面に冷却板2
1を積層してある。この電子回路装置配線基板は、I/O
ピンを介して配線ボード22に接続され、電子回路を構
成している。
Example 1 FIG. 6 shows electroless Ni containing Pb.
-Using Sn-based brazing material for B plating metallization
FIG. 2 is a cross-sectional view of a joint portion showing an embodiment of the present invention with I / O pins attached, in which 11 is a multilayer ceramic substrate and 12 is Sn2.
A brazing material having a composition of 0% by weight Au and 80% by weight, 9 is an intermetallic compound layer, 5 is electroless Ni-B plating metallization, 6 is a conductor portion on the surface of the circuit board, and 7 is a through hole. FIG. 8 is a perspective view showing an outline of an electronic circuit device in which a circuit board as an embodiment of the present invention in which I / O pins are connected by Au20Sn brazing material is assembled. In the electronic circuit device of this embodiment, a plurality of semiconductor elements 18 are arranged on the multilayer wiring board 11 having the I / O pins 1 connected by the above method, and the heat conduction relay member 19 is placed on the semiconductor elements. A cap 20 that covers the multilayer wiring board 11 is placed on the relay member, and the cooling plate 2 is placed on the upper surface of the cap 20.
1 is laminated. This electronic circuit device wiring board is I / O
It is connected to the wiring board 22 via pins and constitutes an electronic circuit.

【0017】次に、本発明に用いた回路基板とI/Oピン
接続電極メタライゼーションの作成方法について。図7
の作成工程概略図を用いて説明する。図7(a)は基板の
導体部およびスルーホール断面の拡大図で、基板として
はセラミック回路基板を用いた。前処理として、導体表
面をアルカリ溶液でソフトエッチし、酸で中和処理し、
脱脂を行なった。次に、安定化剤として鉛化合物を含む
液体を用いて活性化処理した(図7(b))。その後、無電
解Ni−Bめっき膜5を形成し(図7(c))、表面保護の
目的で無電解Auめっき膜15を形成し(図7(d))、メ
タライゼーションとした。成膜後、基板の熱処理により
導体表面/無電解Ni−Bめっき膜/無電解Auめっき
膜間を相互拡散させ、接合金属層間の密着性を上げる
(図7(e))。熱処理の後、あらかじめAu−20Snろ
う材が搭載されているI/Oピンを、基板導体部に形成し
た金属層の上に位置決めした(図7(f))後、320℃ま
で加熱した。Au−Snろう材が接合金属層表面に濡れ
拡がると同時に、無電解Ni−Bめっき層に拡散してN
i−Sn金属化合物を形成しI/Oピンは基板に接続され
る。
Next, the circuit board used in the present invention and the method for producing the I / O pin connection electrode metallization. Figure 7
Will be described with reference to a schematic view of the production process of. FIG. 7A is an enlarged view of a conductor portion and a through hole section of the substrate, and a ceramic circuit substrate is used as the substrate. As a pretreatment, the conductor surface is soft-etched with an alkaline solution and neutralized with an acid.
Degreasing was performed. Next, activation treatment was performed using a liquid containing a lead compound as a stabilizer (FIG. 7 (b)). After that, an electroless Ni-B plating film 5 was formed (FIG. 7C), and an electroless Au plating film 15 was formed for the purpose of surface protection (FIG. 7D) to obtain metallization. After film formation, heat treatment of the substrate causes mutual diffusion between the conductor surface / electroless Ni-B plating film / electroless Au plating film to improve adhesion between the joining metal layers.
(FIG. 7 (e)). After the heat treatment, the I / O pin on which the Au-20Sn brazing material was previously mounted was positioned on the metal layer formed on the substrate conductor portion (FIG. 7 (f)), and then heated to 320 ° C. At the same time that the Au-Sn brazing material wets and spreads on the surface of the joining metal layer, it diffuses into the electroless Ni-B plating layer and N
The i-Sn metal compound is formed and the I / O pins are connected to the substrate.

【0018】この工程で接続したI/Oピンと基板上導体
部との接合状態を評価するために、I/Oピンの引張り強
度を測定した。評価の基準は以下のとうりである。接合
状態が良好な場合、I/Oピン接合部(ろう付け部)が破
断せず、I/Oピンそのものが一定強度以上で破断する。
すなわち、I/Oピン1本あたりのろう付け部分の接合強
度が、I/Oピン軸部分の材料の引張り強度よりも高い条
件である。Au20Snろう材を用いて接合したI/Oピ
ンの接合状態を評価するため、引張り試験を行ったとこ
ろ、すべてについてピン切れとなり、十分な接合強度が
得られた。この接合部の断面形状を観察したところ、ボ
イド、クラック等の発生はなく接合状態は正常であるこ
とが判った。
The tensile strength of the I / O pin was measured in order to evaluate the bonding state between the I / O pin connected in this step and the conductor portion on the substrate. The evaluation criteria are as follows. When the joining condition is good, the I / O pin joint (brazing part) does not break, and the I / O pin itself breaks at a certain strength or higher.
That is, the condition is that the joint strength of the brazed portion per I / O pin is higher than the tensile strength of the material of the I / O pin shaft portion. In order to evaluate the bonding state of the I / O pin bonded using the Au20Sn brazing material, a tensile test was conducted, and all the pins were broken, and sufficient bonding strength was obtained. Observation of the cross-sectional shape of this bonded portion revealed that the bonded state was normal without the occurrence of voids, cracks and the like.

【0019】また比較のために、従来技術を用いて上記
方法で形成した無電解Ni−Bめっきメタライゼーショ
ンに400℃の接合温度でAu13Geを用いてI/Oピ
ン接合したものに対して同様の引張り試験を行った。そ
の結果、90%以上のI/Oピンが金属間化合物とメタラ
イゼーションの間で破断する接合不良を起こした。これ
により、本発明の一実施例であるAu20Snろう材を
用いた接合が、Pbを含む無電解Ni−Bめっきメタラ
イゼーションに対して十分な接合強度を与えるろう材で
あることが検証された。このように、Sn系ろう材を用
いてI/Oピン接合を行うと、形成する金属間化合物層を
Pbが拡散できるため、接合界面のPb偏析を起こすこ
となく高いI/Oピン接合強度が得られた。
For comparison, the same applies to the electroless Ni-B plating metallization formed by the above method using the conventional technique and the I / O pin bonding using Au13Ge at the bonding temperature of 400 ° C. A tensile test was performed. As a result, 90% or more of the I / O pins caused a joint failure that fractured between the intermetallic compound and the metallization. From this, it was verified that the joining using the Au20Sn brazing filler metal, which is one embodiment of the present invention, is a brazing filler metal that gives a sufficient bonding strength to the electroless Ni-B plating metallization containing Pb. In this way, when I / O pin bonding is performed using a Sn-based brazing material, Pb can diffuse in the intermetallic compound layer to be formed, so that high I / O pin bonding strength can be achieved without causing Pb segregation at the bonding interface. Was obtained.

【0020】このように、本発明を用いることにより、
回路基板上に形成したPbを含む無電解Ni−Bめっき
メタライゼーションに対し、接合強度低下の原因となる
接合界面Pb偏析を起こすことなく、接合強度と高い信
頼性を有する良好な回路基板とI/Oピンの接続方法が達
成でき、これを用いた電子回路装置が実現できた。
As described above, by using the present invention,
With respect to electroless Ni-B plating metallization containing Pb formed on a circuit board, a good circuit board having high bonding strength and high reliability without causing segregation of Pb at the bonding interface that causes deterioration of bonding strength The connection method of / O pin was achieved, and the electronic circuit device using this was realized.

【0021】(実施例2)回路基板上の無電解Ni−B
メタライゼーションに、Auめっきされた電極端子部分
を持つ半導体素子をAg3重量%Sn97重量%の組成
からなるはんだ材を用いて接合した実施例について説明
する。図9に示すように、回路基板の電極上に実施例1
と同様の方法で形成したメタライゼーションと、半導体
素子の電極端子部分との間にSn3Ag微小はんだボー
ル23を介在させ、接合温度を240℃でろう接続す
る。この際メタライゼーションとSn3Agろう材の接
合界面にできるNi−Sn金属間化合物に対して、メタ
ライゼーション中に含まれるPbは、化合物層中へ拡散
可能である。したがってPbを含む無電解Ni−Bメタ
ライゼーションに対して、Sn系のSn3Agはんだ材
で接続することにより、接合界面にPb偏析することな
く、十分な強度と高い信頼性を持つ接合が得られる。
(Example 2) Electroless Ni-B on a circuit board
An example in which a semiconductor element having an Au-plated electrode terminal portion is bonded to the metallization by using a solder material having a composition of Ag3 wt% Sn97 wt% will be described. As shown in FIG. 9, Example 1 was formed on the electrodes of the circuit board.
Sn3Ag fine solder balls 23 are interposed between the metallization formed by the same method as described above and the electrode terminal portion of the semiconductor element, and brazing is performed at a bonding temperature of 240 ° C. At this time, Pb contained in the metallization can diffuse into the compound layer with respect to the Ni-Sn intermetallic compound formed at the bonding interface between the metallization and the Sn3Ag brazing material. Therefore, by connecting the Sn-based Sn3Ag solder material to the electroless Ni-B metallization containing Pb, a bond having sufficient strength and high reliability can be obtained without segregating Pb at the bonding interface.

【0022】このように、本発明を用いることにより、
回路基板上にPbを含む無電解Ni−Bめっきメタライ
ゼーションパットに対し、接合強度低下の原因となる接
合界面Pb偏析を起こすことなく、接合強度と高い信頼
性を有する良好な回路基板と半導体素子の端子電極との
接続方法が達成され、これを用いた電子回路装置が得ら
れた。
As described above, by using the present invention,
A good circuit board and a semiconductor device having a bonding strength and high reliability without causing segregation at the bonding interface Pb that causes a decrease in bonding strength with respect to an electroless Ni-B plating metallization pad containing Pb on the circuit board. The method of connecting to the terminal electrode of 1 was achieved, and an electronic circuit device using this was obtained.

【0023】(実施例3)回路基板上の無電解Ni−B
めっきメタライゼーションに、Pb37重量%Sn63
重量%の組成からなるはんだ合金を用いて半導体素子の
周囲を封止するキャップを接合した実施例について説明
する。図10に示すように、回路基板の周辺部に実施例
1と同様の方法で形成したメタライゼーションと、封止
キャップ側周縁部との間にSn37Pbはんだ材24を
介在させ、接合温度を200℃で接続する。この際メタ
ライゼーションとSn37Pbろう材の接合界面にでき
るNi−Sn金属間化合物に対して、無電解Ni−Bめ
っきメタライゼーション中に含まれるPbは、化合物層
中へ拡散可能である。したがってPbを含む無電解Ni
−Bメタライゼーションに対して、Sn系のSn37P
bはんだ材で接続することにより接合界面にPb偏析す
ることなく良好な接合状態を有し、十分な強度と高い信
頼性を持つ接合が得られる。
(Example 3) Electroless Ni-B on a circuit board
For plating metallization, Pb37 wt% Sn63
An example in which a cap that seals the periphery of the semiconductor element is joined using a solder alloy having a composition of wt% will be described. As shown in FIG. 10, the Sn37Pb solder material 24 is interposed between the metallization formed in the peripheral portion of the circuit board by the same method as in Example 1 and the peripheral edge portion on the sealing cap side, and the bonding temperature is 200 ° C. Connect with. In this case, Pb contained in the electroless Ni-B plating metallization can diffuse into the compound layer, with respect to the Ni-Sn intermetallic compound formed at the bonding interface between the metallization and the Sn37Pb brazing material. Therefore, electroless Ni containing Pb
-Sn-based Sn37P for B metallization
By connecting with the b solder material, a good bonding state can be obtained without Pb segregation at the bonding interface, and bonding with sufficient strength and high reliability can be obtained.

【0024】このように、本発明を用いることにより、
回路基板上にPbを含む無電解Ni−Bめっきメタライ
ゼーションパットに対し、接合強度低下の原因となる接
合界面Pb偏析を起こすことなく、接合強度と高い信頼
性を有する良好な回路基板と封止キャップの接続方法が
達成され、これを用いた電子回路装置が得られた。
Thus, by using the present invention,
For an electroless Ni-B plating metallization pad containing Pb on a circuit board, a good circuit board having good bonding strength and high reliability without causing segregation at the bonding interface Pb that causes a decrease in bonding strength is formed. A cap connecting method was achieved, and an electronic circuit device using the same was obtained.

【0025】[0025]

【発明の効果】本発明を用いることにより、回路基板上
に形成したPbを含む無電解Ni−Bめっきメタライゼ
ーションパットに対し、Sn系ろう材を用いてNi−S
n合金形成により部品を接続することにより、接合強度
低下の原因となる接合界面Pb偏析を起こすことなく、
高い接合強度と高い信頼性が得られる良好な回路基板と
部品の接続方法およびこれを用いた電子回路装置が実現
できた。
As described above, according to the present invention, an Sn-based brazing material is used for a Ni-S alloy for an electroless Ni-B plated metallization pad containing Pb formed on a circuit board.
By connecting the parts by forming the n-alloy, the segregation of the joint interface Pb, which causes a decrease in the joint strength, does not occur.
A good method of connecting a circuit board and parts, which can obtain high bonding strength and high reliability, and an electronic circuit device using the same have been realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来技術により回路基板上に形成したメタライ
ゼーションにI/Oピンを接続した接合部の断面図。
FIG. 1 is a cross-sectional view of a joint in which an I / O pin is connected to a metallization formed on a circuit board by a conventional technique.

【図2】図1の接合界面の拡大図。FIG. 2 is an enlarged view of the bonding interface of FIG.

【図3】本発明の接続方法を用いて、回路基板上に形成
したメタライゼーションにI/Oピンを接続した接合界面
の断面図。
FIG. 3 is a cross-sectional view of a bonding interface in which I / O pins are connected to metallization formed on a circuit board by using the connection method of the present invention.

【図4】本発明に係るNi−Pb2元系状態図。FIG. 4 is a state diagram of a Ni—Pb binary system according to the present invention.

【図5】本発明に係るGe−Pb2元系状態図。FIG. 5 is a Ge-Pb binary system state diagram according to the present invention.

【図6】本発明の接続方法を用いて、回路基板とI/Oピ
ンを接続した接合部の断面図。
FIG. 6 is a cross-sectional view of a joint portion in which a circuit board and an I / O pin are connected by using the connection method of the present invention.

【図7】本発明の回路基板と部品の接続方法を用いて、
回路基板とI/Oピンを接続する工程を示す説明図。
FIG. 7 is a diagram showing a method of connecting a circuit board and components of the present invention,
Explanatory drawing which shows the process of connecting a circuit board and an I / O pin.

【図8】本発明の一実施例の電子回路装置の構成を示す
斜視図。
FIG. 8 is a perspective view showing a configuration of an electronic circuit device according to an embodiment of the present invention.

【図9】本発明の接続方法を用いて、回路基板と半導体
素子を接続した接合部の断面図。
FIG. 9 is a cross-sectional view of a joint portion in which a circuit board and a semiconductor element are connected by using the connection method of the present invention.

【図10】本発明の接続方法を用いて、回路基板と封止
キャップを接続した接合部の断面図。
FIG. 10 is a cross-sectional view of a joint portion in which a circuit board and a sealing cap are connected by using the connection method of the present invention.

【符号の説明】[Explanation of symbols]

1…I/Oピン、 7…Ni−Ge金属間化合物層、 20…封止キャップ、 21…冷却板、 22…配線ボード。 1 ... I / O pin, 7 ... Ni-Ge intermetallic compound layer, 20 ... Sealing cap, 21 ... Cooling plate, 22 ... Wiring board.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 松井 清 神奈川県秦野市堀山下1番地株式会社日立 製作所汎用コンピュータ事業部内 (72)発明者 太田 敏彦 神奈川県秦野市堀山下1番地株式会社日立 製作所汎用コンピュータ事業部内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiyoshi Matsui 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi General Computer Division (72) Inventor Toshihiko Ota 1 Horiyamashita, Hadano, Kanagawa Hitachi Ltd. General Computer Division

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】回路基板上にろう材を用いて接合する接続
方法で、前記回路基板上に鉛を含む無電解ニッケル−ホ
ウ素合金めっきを用いてメタライゼーションパットを形
成し、前記回路基板上に錫系ろう材を用いて、主にニッ
ケル−錫合金形成により部品を接続することを特徴とす
る回路基板の接続方法。
A metallization pad is formed on the circuit board by electroless nickel-boron alloy plating containing lead, and the metallization pad is formed on the circuit board by a connection method using a brazing material on the circuit board. A method for connecting circuit boards, characterized in that parts are connected mainly by forming a nickel-tin alloy using a tin-based brazing material.
【請求項2】請求項1に記載の接続方法を用いた電子回
路装置。
2. An electronic circuit device using the connection method according to claim 1.
JP9219295A 1995-04-18 1995-04-18 Method for connecting circuit board and electronic circuit device using it Pending JPH08288625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9219295A JPH08288625A (en) 1995-04-18 1995-04-18 Method for connecting circuit board and electronic circuit device using it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9219295A JPH08288625A (en) 1995-04-18 1995-04-18 Method for connecting circuit board and electronic circuit device using it

Publications (1)

Publication Number Publication Date
JPH08288625A true JPH08288625A (en) 1996-11-01

Family

ID=14047584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9219295A Pending JPH08288625A (en) 1995-04-18 1995-04-18 Method for connecting circuit board and electronic circuit device using it

Country Status (1)

Country Link
JP (1) JPH08288625A (en)

Similar Documents

Publication Publication Date Title
KR101704030B1 (en) Improvement of solder interconnect by addition of copper
TWI230105B (en) Solder
US5367195A (en) Structure and method for a superbarrier to prevent diffusion between a noble and a non-noble metal
EP2312622B1 (en) Power semiconductor device with a power semiconductor element bonded to a substrate by a Sn-Sb-Cu solder and with a terminal bonded to the substrate by a Sn-Ag-based or Sn-Ag-Cu-based solder and manufacturing method therefor
CN108290250B (en) Soldered joint
US6444562B1 (en) Nickel alloy films for reduced intermetallic formation in solder
TWI505899B (en) A bonding method, a bonding structure, and a method for manufacturing the same
WO2003046981A1 (en) Module structure and module comprising it
EP0828410A2 (en) Dual-solder process for enhancing reliability of thick-film hybrid circuits
JP2004114069A (en) SOLDER ALLOY FOR SOLDERING TO ELECTROLESS Ni PLATED PART
JPS641060B2 (en)
JP4699704B2 (en) Wiring board
JP4011214B2 (en) Semiconductor device and joining method using solder
JP3660798B2 (en) Circuit board
JPWO2002005609A1 (en) Connection structure and connection method between conductors
JP2002111188A (en) Wiring board
JPH1093004A (en) Electronic component and manufacture thereof
US6742248B2 (en) Method of forming a soldered electrical connection
JP2002057444A (en) Wiring board
JPH08288625A (en) Method for connecting circuit board and electronic circuit device using it
EP1956114A1 (en) A layer assembly, a method of forming said layer assembly and a circuit carrier comprising said layer assembly
WO2001076335A1 (en) Mounting structure of electronic device and method of mounting electronic device
JP2003223945A (en) LEAD PIN WITH Au-Ge SYSTEM BRAZING MATERIAL
JP3470789B2 (en) Wiring board and method of manufacturing the same
JP2005286323A (en) Wiring substrate, wiring substrate with solder member, and manufacturing method of the same