JPH08287022A - Multiprocessor system and its exclusive control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lock mechanism which can facilitate a counter measure to a plurality of instructions and/or a plurality of words. SOLUTION: A multiprocessor system 100 is provided with a plurality of processors, intermediate caches 104 connected with the plurality of processors, and shared memory 102 connected through a common bus 106 with the intermediate caches 104, and shared by the plurality of processors. Each of the plurality of processors has a local cache, and the resource of the intermediate cache 104 is shared by the plurality of processors. One processor starts a lock operation in order to obtain the exclusive control of storage units. The exclusive control is maintained across a plurality of instructions. Moreover, any instruction related with the locked storage units is fetched prior to the lock operation, and maintained by the local cache 108 of the processor which makes the lock request until the exclusive control is released by the lock releasing operation.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to processing within multiprocessor systems, and more particularly to storage units.
It relates to a mechanism for locking (a unit of storage). This mechanism allows exclusive control to be maintained over multiple instructions being executed on a locked storage unit, and except when a request to access that storage unit is provided by another processor. It does not keep the shared system bus busy.

[0002]

2. Description of the Related Art In computer systems, various lock mechanisms have been used to perform exclusive control on storage units. Exclusive control is necessary for many reasons, but one of the most important is to ensure storage consistency during update operations.

An example of a general-purpose mechanism for locking a storage unit in a multiprocessor system is shown below. In one example, exclusive control is achieved by disabling the shared system bus of a multiprocessor system. In particular, the system bus appears busy when it is being monitored and a request for an exclusively held storage unit is made by another processor. Therefore, access to the exclusively held storage unit as well as access to the shared memory of the system is prevented.

Locking the system bus as described above has several disadvantages. For example, because the system bus is considered busy, access to shared memory is denied, unnecessarily degrading system performance. In addition, because the system bus is busy for all commands other than invalid commands for a particular locked storage unit, the instructions needed to perform an update operation prior to releasing this exclusive control. Cannot be retrieved from main memory. Thus, a potential deadlock situation arises.

The potential deadlock situation described above is avoided when a single hardware instruction is used to automatically update a memory location. ESA (Enterprise System
Architecture) / 390 instruction set includes a number of single hardware instructions for performing internal lock update operations. For examples of these instructions, see COMPARE AND
SWAP, COMPARE DOUBLE AND SWAP, TEST AND SE
, Etc., but for details of each of these, see IB
Company M (International Business Machines Corporation)
See ESA / 390, "Principles of Operation" (Issue No. SA22-7201-02, December 1994). However, these instructions can only be used for simple compare and update. Thus, if the function performed between fetch and store is more complex than a simple comparison, or if the atomically updated store spans multiple doublewords, then these instructions are not appropriate. Absent.

[0006]

From the above point of view, there is a need for a systematic locking mechanism capable of handling multiple instructions and / or multiple words. In addition, a locking mechanism is needed to keep the system bus busy only when requested by another processor that attempts to invalidate the lock state of the storage unit (that is, gain access). It is said that Furthermore, there is also a need for a mechanism to maintain in the local cache the instructions used to reference a locked storage unit until the locked state is released.

[0007]

The present invention overcomes the deficiencies of the prior art while providing additional benefits. The present invention relates to a plurality of processors each provided with a cache, an intermediate cache connected to the plurality of processors and sharing the resources thereof, and a memory connected to the intermediate cache via a shared bus. And a means provided in one of the plurality of processors for obtaining exclusive control over the storage unit. While exclusive control is maintained over multiple instructions being executed using a storage unit, a shared bus is a multiple processor except when a request to access that storage unit is made by another processor. Will be ready for use.

In a further embodiment of the present invention, the multiprocessor system described above maintains multiple instructions in a local cache of a processor that owns exclusive control, which can refer to a locked storage unit. Have means. Multiple instructions remain in their local cache until the lock is released.

In a further embodiment of the invention, a local
Multiple instructions are maintained in the local cache by relaxing the subset rules that exist between the cache and the intermediate cache connected to it. This allows multiple instructions to be present in the local cache even if not in the intermediate cache.

In a further embodiment of the invention, a method of gaining exclusive control over a storage unit in a multiprocessor system is provided. This multiprocessor
The system is connected to, for example, a plurality of processors each having a cache, an intermediate cache connected to the plurality of processors and sharing the resources thereof by the plurality of processors, and the intermediate cache via a shared bus. And a memory. One of the processors initiates and executes a lock operation to gain exclusive control over a specified storage unit. Until the unlock operation is performed, exclusive control is maintained over the instructions being executed using that storage unit.

In a further embodiment of the invention, an instruction referencing a locked storage unit is fetched into the local cache prior to the lock operation and maintained in the local cache until the lock is released. To be done.

The lock mechanism according to the present invention is advantageous in that a storage unit can be locked over a plurality of instructions or a plurality of words. The lock mechanism of the present invention does not require the shared bus to be in a busy state except for locking only the storage unit and prohibiting access to the locked storage unit by another processor. Further, the locking mechanism of the present invention allows internal code to reside in the local cache, and need not reside in the intermediate cache as well. Thus, code that is age out from the intermediate cache can remain in the local cache. In this way, the number of local cache misses is reduced, thus improving system performance.

[0013]

DETAILED DESCRIPTION OF THE INVENTION In the present invention, a mechanism (ie, technology and associated hardware) for locking storage units is provided. Thus, in a multiprocessor system, one of the processors has exclusive control of the storage unit until the processor explicitly releases the lock state of the storage unit.
The storage unit can remain locked across multiple instructions being executed by the processor. With this locking mechanism, the shared system bus does not appear to be busy unless there is an invalid request (i.e., access request) to a particular storage unit that is locked.

In one embodiment of the present invention, the instruction (ie, code) used to refer to the storage unit is a storage unit lock instruction, a storage unit update instruction, and a storage unit unlock instruction. Yes (but not limited to). These instructions are fetched into the local cache before locking the storage unit,
It stays in the local cache until the lock is released. To remain in the local cache, the subset rules normally associated with the local cache are relaxed. This will be described below.

An example of a multiprocessor system incorporating the locking mechanism of the present invention is provided by IBM Corporation.
It is a system based on the ESA / 390 architecture. ESA / 3
For more information about 90, see "Princip" in ESA / 390 by IBM.
les of Operation '' (Issue No.SA22-7201-02, December
1994).

The multiprocessor system of the present invention comprises:
It is capable of executing the complex instruction set and internal code of the ESA / 390 architecture. Internal code can control system hardware more directly than the ESA / 390 instruction set. An example of internal code is millicode, which is executed in the system in much the same way as the ESA / 390 instruction set. In the present invention internal code is used to execute more complex instructions. For example, an instruction that requires the lock mechanism of the present invention. Millicode routines are known to those of skill in the art and may be found in more detail in the IBM Technical Disclosure Bulletin, Vol. 35, N by Buillions et al.
See 4A, September 1992.

FIG. 1 illustrates a multiprocessor system 10.
0 shows one embodiment. Multiprocessor system 1
00 is, for example, one or a plurality of intermediate caches (that is, level 2 (L2) caches) via the shared bus 106.
A shared memory 102 connected to 104 is provided. These intermediate caches 104 are connected to one or more processors 108 via a general link or bus 110. In this embodiment, each processor has one L2
Connected to cache, but each L2 cache has 1
Alternatively, it may be connected to a plurality of processors. In this case, the resources of the L2 cache (for example, cache,
The directories and the mechanisms for accessing main memory, etc.) are shared by these connected processors. In addition, each processor has a local cache (ie, a level 1 (L1) cache). Shared memory, L2 cache, and L1 cache have three layers
A (three-tier) storage system is configured, and each layer thereof will be described below.

The shared memory 12 is the third layer of the three layer storage system. The shared memory 12 is the processor 108.
Directly addressable by the processor 10
8 stores information (for example, data and instructions) used by the user. As is well known, data and instructions used by a processor are fetched by the processor into an L2 cache and / or an L1 cache.

The L2 cache is an intermediate cache,
It is typically larger than the local cache (L1 cache) and allows faster access than retrieving information from shared memory. This is because the processor can access the L2 cache without referring to the shared bus. As an example, if the L2 cache is a store-in cache, the information stored therein is written to main memory 102 only under certain conditions.

The L1 cache is a local cache, usually smaller than the L2 cache and internal to the processor. As an example, if the L1 cache is a store-through cache, all information stored by the processor in the L1 cache is automatically passed to the L2 cache connected to it.
In one embodiment, a strict subset rule is provided between the L1 and L2 caches. This strict subset rule requires that any information that is present in the L1 cache also be present in the L2 cache connected to that L1 cache. This allows each L2 cache to know whether or not the specific storage unit requested by another processor is stored in any of the L1 caches connected to that L2 cache. In the present invention, this strict subset rule is relaxed for instructions that reference locked storage units. This will be described in detail below.

The locking mechanism of the present invention is located within processor 108. FIG. 2 is a diagram showing the lock mechanism in detail. In one embodiment, each processor includes, for example, an instruction unit 200 that fetches instructions and operands and decodes the instructions, an execution unit 202 that executes the decoded instructions, and a buffer control element 204 that caches the data and instructions. To have. Instruction unit,
The execution unit and the buffer control element will be described in detail below.

As an example, the instruction unit 200 includes, for example, an instruction buffer 206, an instruction register 208, an instruction decoding device 210, an address control device 212,
Address adder 214 and local control register (CR)
And a copying machine 216. Next, each of these will be described.

The instruction buffer 206 receives as an input instructions from the buffer control element 204. These instructions are decoded and finally executed by execution unit 202. The instruction to be decoded is fetched from the instruction buffer 206 and stored in the instruction register 208. After that, the instruction register 208 passes the instruction to be decoded to the instruction decoding device 210. Instruction decoding device 210
Passes the decoded instruction to the instruction queue 218 after parsing and decoding the instruction. Here the instruction waits for execution. The instruction decoder 210 also passes to the address controller 212 information about the valid addressing modes and operand formats for its operation.

The address control device 212 controls the address adder 214 that generates an address number by designating a request format for the address adder 214.
Address adder 214 forms the logical address passed to buffer control element 204. As an example, address adder 214 receives the input from general / access register 220 and determines the address of the storage unit to be locked. The address adder 214 then passes the address to the buffer control element. This will be described later.

The local CR copier 216 stores a local copy of the registers required by the instruction unit hardware to control and modify instruction processing. What is stored in the local CR copying device 216 is, for example, a program event record (Program Event Recordi).
ng) is a copy of the ESA / 390 control register used for ng) and a copy of the internal register that specifies the current mode of operation. Updates to these registers are acknowledged by monitoring the register address written via the execution unit output bus 201.

Execution unit 202 receives decoded instructions from instruction queue 218 and executes these instructions in a manner well known to those skilled in the art. As an example, the execution unit 202 comprises an execution unit controller 222 that controls the sequences within the execution unit 202, a fixed point unit 224, and a floating point unit 232. The fixed point unit 224 has an arithmetic logic unit (ALU) 226.
And a register (eg, A register and B register) 228 that provides an input to the fixed point unit 224 and receives the results of the fixed point unit 224 and directs them to the general / access register 220 and / or the buffer control element 204.
And a register (for example, a C register) 230 to be transferred to. The floating point unit 232 is an arithmetic logic unit (AL
U) 234 and registers (eg A and B registers) 236 that provide input to the floating point unit 232.
And floating-point registers 24 that receive the results of the floating-point unit 224 and locate them in the execution unit 202.
2. General / access register 220 and / or register (eg C register) passed to buffer control element 204 2.
38 and 38 as appropriate.

Also located within execution unit 202 is an operand buffer 240, which receives operand data from a local cache within buffer control element 204 and inputs that data into, for example, register 228. . Furthermore, the register 228 is a general-purpose
/ Data from the access register 220 is also input. In addition, the floating point register 242 is
Input to 36 is provided. Fixed point C register 23
0 and floating point C register 238
Is connected to the single bus 201 and the cache 24
8 to transfer the data stored therein to each of the registers, i.e. general / access register 220, floating point register 242 and local CR copiers 216 and 26.
The update data for 6 is transmitted.

In one example, the buffer control element 204 comprises an address translator 240, which receives an address from an address adder 214, which is converted in a manner well known to those skilled in the art, for example from a virtual address to a real address. And convert. For details, refer to the above-mentioned document "Principle of
Operation ”.

In addition, the buffer control element 204 comprises a logical address (LA) register 246, which
The address received from the address adder is stored. The translated address and / or logical address is a double word
It is used to address the interleave cache 248. For the control relating to the cache 248, for example, the write data even register 25
0, write data odd register 252, and individual multiplexers 254, 256, as well as data even output register 258 and data odd output register 260. The multiplexers 254 and 256 are the execution units 2
02 registers 230, 238, and also from an intermediate cache (L2 cache) connected to the processor. Connected to the above output registers are multiple multiplexers 262, which are instruction unit 200, execution unit 20.
2 and the inputs to the storage buffer 264 for the L2 buffer.

Further in the present invention, the buffer control element 204 comprises a local CR copier 266. It receives input from the execution unit 202. The local CR copier 266 may be, for example, a buffer control element 20.
4 contains a copy of the command stored in the command register. This will be described later with reference to FIG. The local CR copier 266 further includes buffer control element 2
ESA / 390 required to control 04 operations
Contains a local copy of the control register.

The locking mechanism according to the present invention is initiated when the processor requests exclusive control of a storage unit (also called a data cache line or storage block (eg 128 bytes)). This processor
An instruction is used to instruct the buffer control element to lock its storage unit. As a result, no other processor in the system can access the storage unit until the processor holding the locked state releases the lock. An example of an instruction issued by the processor to lock or unlock a storage unit is shown in FIG.

As an example, in FIG. 3, the SYSRQ (Perform S) is used to set or reset the storage unit lock.
ystem Request) command is used. In this example SYSRQ instruction 300, operation code 3 indicates that this instruction is a special request to the buffer control element.
02, a base address (B2) field 304, and a displacement address (D2) field 306. The contents of the general purpose register pointed to by the B2 field are added to the contents of the D2 field to form the address of the second operand. The address of the second operand is the address of the storage unit to be locked (for example, virtual address or real address).

As described with reference to FIG. 2, SYSRQ
The instructions are decoded by instruction unit 200 and executed by execution unit 202. The address of the second operand is passed from address adder 214 to logical address register 246. For lock operations, this address represents the storage unit to be locked.

In the present invention, the hardware for locking and unlocking storage units is located in the buffer control element of the processor requesting the locking and unlocking operations. An example of hardware relating to the lock and unlock mechanism of the present invention will be described with reference to FIG.

In FIG. 4, the address of the storage unit to be locked is received from the processor address bus and stored in the logical address register 246. In one example, this address is 32 bits long and represents either a virtual address or a real address depending on the mode of operation, which is well known. When the address is a virtual address, for example, well-known dynamic address translation (D
It is converted to a real address using AT) technology. To extend performance, a portion of the translated address (ie, the translated page address represented by bits 0-19 of the logical address) is translated lookaside.
Stored in buffer 400. Dynamic address translation and translation lookaside buffers are well known to those skilled in the art and are also described in the aforementioned document "Principles of Operation".

Thereafter, it is determined whether the storage unit to be locked exists in the L1 cache. This decision is
This is done by examining the directory 401 in the buffer control element. If the storage unit is not located in that directory, it is fetched from the L2 cache using line fetch control 403.

The contents of the TLB (Translation Lookaside Buffer) are then loaded into absolute address register 402 along with bits 20-24 of the logical address, which represents the line offset of this address. At this point, the address in the absolute address register represents the absolute address (line boundary) of the storage unit to be locked. In other words, in this example, the line (128 bytes, for example)
Since the lock is performed based on the
Only ~ 24 are required. However, if locking is done in larger units, all addresses (eg bits 0-31) will be used.

In addition to the above, the lock command is loaded into the command register 406 prior to issuing the SYSRQ lock instruction. In particular, instructions such as millicode instructions write the value from the general register representing the lock command to the command register. The above SYSRQ command
Rather than using a logical address to access a store, command register 406 is used to tell the buffer control element to lock the storage unit pointed to by that logical address.

The contents of the command register 406 are decoded by the decoding unit 408 in the buffer control element. At this time, the decoding device determines that the command to be executed is a lock operation. The lock / unlock control 410 (which includes, for example, combinatorial logic) then gets the decoded lock command and sets the lock valid bit in register 412. In addition, lock / unlock control 410 places the address in absolute address register 402 into lock register 404. Thus, the lock operation is complete and the processor that performed the lock operation has exclusive control over the storage unit pointed to by the address located in lock register 404. Until the lock is released, any request to invalidate the locked storage unit will be denied.

In one embodiment of the present invention, no operation is allowed while the storage unit is in the locked state, where the processor holding the lock must access the shared bus. All operations should be contained within the L1 cache and processor internal registers.

In addition to the above, in one example, the system components shown in FIG. 4 are also used to determine if access to a locked storage unit by another processor should be denied. In particular, the address of the requested storage unit is passed from the requesting processor to the buffer control element of the processor holding the lock via the L2 address bus and stored in logical address register 246. This address is translated appropriately and the translated page address is stored in TLB 400. Then, the contents of TLB and bit 20 to 20 of the register 246
24 is loaded into absolute address register 402. (In this example, the new address is lock register 4
The address in register 402 is compared with the contents of lock register 404 which contains the address of the locked storage unit (since it has not been placed in 04) (comparator 41
4). If the comparisons are the same and the lock valid bit is set (AND logic 416), control 418 does not allow the invalidation request to be executed. However, if the lock valid bit is off, access to the storage unit is granted.

When the processor no longer needs exclusive control of a storage unit, it explicitly releases the lock in accordance with the present invention. In one example in particular, command register 406 is set up with an unlock command. The SYSRQ instruction tells the buffer control element to perform the function represented by the command in the command register. In this case, the address is not used. The command register is decoded and the lock / unlock control 410 resets the lock valid bit 412. This allows another processor to access the locked storage unit.

In one embodiment of the present invention, a locking mechanism is used to perform storage unit updates without violating storage consistency. As an example, atomic updates are performed by internal code (ie, millicode). Millicode sets up a command register to indicate that a lock should be taken, issues a lock operation, performs a mutual lock update, stores the result, and releases the lock.

In the present invention, prior to the lock instruction being issued (ie, if the millicode is not already in the local cache), the millicode is fetched from main memory and placed in the local cache of the processor performing the lock. Remembered. In the present invention, this millicode is kept in the local cache until the lock is released.

In one example, the subset rules between the L1 and L2 caches are relaxed to ensure that millicode stays in the local cache.
This allows millicode to remain in the L1 cache even if it is not in the L2 cache. This is achieved, for example, by treating all instructions within the specified absolute address range as read-only.
In this example, millicode instructions remain in storage within this address range. This range is given to the buffer control element at system initialization. In particular, the beginning and end of this range are stored in the register of the buffer control element. Copies of these registers are stored in local CR copier 266. Requests from the L2 cache that try to invalidate code lines within this range (ie 128 bytes) are ignored. Thus this line will remain in the L1 cache until it is disposed of, for example, according to the least recently used (LRU) algorithm or any other scheme.

In one embodiment of the invention, all millicode (ie, internal code) instructions for interlock update operations are stored in one cache instruction line (ie, within 128 bytes). This is, for example, S for lock and unlock operations.
It includes the YSRQ instruction and all instructions executed between two SYSRQ instructions.

The lock mechanism for providing exclusive control for a specific storage unit has been described in detail above.
It can be extended to multiple millicode instructions. In addition to storage unit locking, this locking mechanism according to the present invention and the relaxation of the subset rules for instructions within a certain range ensures that the instruction lines are in sequence in the local cache. You can avoid a deadlock situation. The lock mechanism of the present invention does not stop access from other processors to other storage units in the L1 cache and L2 cache. Only mutual invalidations for interlocked storage units will freeze the shared bus. Relaxing the subset rules allows code lines used by one processor to stay in the L1 cache longer, which results in invalidity due to L2 fetch misses from other processors sharing the L2 cache. The system performance is improved because the influence of the request for computerization is reduced. Also,
Fetching operands within the millicode address range by the buffer control element is not exclusive, further improving system performance.

An example of how to use the locking mechanism in a multiprocessor system is shown and described below. Instruction line 1: ··· Set up registers for lock / unlock operations to drain the instruction pipeline, including writing all operand stores to the L2 cache. Instruction line 2: Interlock command Issue an instruction that includes an update to a locked storage unit Issue a SYSRQ with an unlock command

In the above example, on instruction (ie code) line 1, the command register in the buffer control element is set up with a lock or unlock command depending on the operation to be performed.

First, on line 2, a lock command is issued using the SYSRQ instruction. The lock command locks the particular storage unit specified by this instruction. After the storage unit is locked, the instructions in the code line work on the storage unit. For example, the storage unit is inspected and updated. The lock is then released so that the other processor can access the data line.

In the above example, only one data line is locked. This is just one example. In another embodiment, for example, the local cache is at least a three-way set assoc.
iative) ・ In the case of cache, it is possible to lock multiple storage units. It will be apparent to those skilled in the art that other embodiments are possible.

In the preferred embodiment above, all millicode lines are considered read-only. However, in other embodiments this is not necessary. In yet another example embodiment, locking and memory references are not done by millicode, but by any code present in memory that is considered read-only.

The following is an alternative to the above example.
In one embodiment, a directory bit or code point located in the L1 cache directory indicates that a particular line is millicode, and thus the L1 / L2 subset rule should be relaxed. Used to indicate. The instruction unit will give this instruction to the instruction fetch. In another example, a millicode address register is added.
If the instruction fetch is for millicode, the buffer control element will check this line in the L1 cache and will be fetched if it does not already exist. In this case all invalidation requests for this line are ignored and the instruction unit must provide instructions for millicode instruction fetch and interlock.
The buffer control element then relaxes the subset rule for this line and ignores the invalidation request for this line.

Although the preferred examples have been described in detail above, those skilled in the art can make various modifications, additions, and substitutions without departing from the spirit of the present invention. It will be apparent that it is within the scope of the invention as defined in the claims.

As a summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) A plurality of processors each having a local cache, an intermediate cache having resources connected to the plurality of processors and shared by the plurality of processors, and the intermediate cache via a shared bus A memory connected to the memory unit and a plurality of instructions provided in one processor of the plurality of processors to obtain exclusive control of the storage unit, the exclusive control being performed by a plurality of instructions executed using the storage unit. Means for obtaining exclusive control, which is maintained across and enables the plurality of processors to use the shared bus except when there is a request for access to the storage unit from another processor of the plurality of processors; A multiprocessor system having: (2) The multiprocessor system according to (1), further comprising means for maintaining the plurality of instructions in the local cache of the one processor until the exclusive control is released. (3) Means for maintaining the plurality of instructions so that the plurality of instructions can be present in the local cache of the one processor without being present in the intermediate cache. The multiprocessor system according to (2) above, having means for relaxing a subset rule existing between the cache and the cache. (4) The multiprocessor system according to the above (1), having means for releasing the exclusive control of the storage unit. (5) The multiprocessor system according to (4), wherein the exclusive control acquisition means and the exclusive control release means have a buffer control element. (6) A plurality of processors each having a local cache, an intermediate cache having resources shared by the plurality of processors and shared by the plurality of processors, and connected to the intermediate cache via a shared bus A method for gaining exclusive control of a storage unit in a multiprocessor system having a memory, wherein one processor of the plurality of processors locks to obtain exclusive control of a specified storage unit.・
A step of starting an operation, giving exclusive control of the storage unit to the one processor, locking the storage unit over a plurality of instructions executed by the one processor, and Storage unit in a multiprocessor system, the step of performing the locking operation to enable the shared bus to be used by the plurality of processors except when there is a request for access to the storage unit from another processor. How to obtain exclusive control of. (7) The method according to (6) above, wherein the storage unit is specified by an address included in an instruction specifying the lock operation. (8) The method according to (7) above, wherein the instructions include internal code of the multiprocessor system. (9) The method according to (6) above, which includes a step of releasing exclusive control of the storage unit. (10) The method according to (9) above, wherein the release is specified by an instruction including internal code of the multiprocessor system. (11) The lock operation and the release are
The method of (9) above, which is performed within a buffer control element of the one processor. (12) When the instructions are not in the local cache of the one processor, the instructions are accessed to access the storage unit before gaining exclusive control of the storage unit. The method of claim (6), including the steps of: fetching into the local cache and maintaining the plurality of instructions in the local cache until the exclusive control is released. (13) The step of maintaining may be performed in the local cache without the plurality of instructions existing in the intermediate cache.
13. The method of (12) above, including the step of relaxing the subset rules that exist between the local cache and the intermediate cache so that they can be in the cache. (14) placing a lock command in a command register that will be accessed during execution of the lock operation prior to execution of the lock operation;
Or storing the data placed in a plurality of buffers in the intermediate cache. (15) The step of performing the lock operation locks an address of the storage unit to be locked.
7. The method according to (6) above, comprising storing in a register and setting a lock valid bit indicating exclusive control of the storage unit. (16) A plurality of processors each having a local cache, an intermediate cache connected to the plurality of processors and having resources shared by the plurality of processors, and connected to the intermediate cache via a shared bus. A method for gaining exclusive control of a storage unit in a multiprocessor system having a memory, the lock being stored in a local cache of one of the plurality of processors before the lock of the storage unit. Maintaining instructions for the storage unit to be retained and retaining the instructions in the local cache until the lock is released; and giving the one processor exclusive control of the storage unit. Performing a lock operation in the one processor, the lock operation comprising: Exclusive control of acquisition method of a storage unit in a multiprocessor system in which control; and held across the plurality of instructions. (17) The executing step generates a millicode instruction designating an address of the storage unit to be locked; loading the address into a lock register and locking the storage unit; Using a lock control mechanism to set a lock valid bit as indicated. (18) The method according to (17) above, which includes a step of releasing exclusive control of the storage unit, and the releasing step includes a step of resetting a lock valid bit to indicate that the storage unit is not locked. Method. (19) A plurality of processors each having a local cache, an intermediate cache connected to the plurality of processors and having resources shared by the plurality of processors, and connected to the intermediate cache via a shared bus. A method for controlling the local presence of a code line in a multiprocessor system having a memory, the method comprising the step of indicating one or more code lines as read-only; Maintaining said one or more code lines designated as read-only in a local cache of a processor, said maintaining step wherein said one or more code lines are present in said intermediate cache. To be in the local cache without Serial method of controlling the local presence of the code line in a multiprocessor system that includes a step of relaxing the subset rule is between local cache and the intermediate cache. (20) A plurality of processors each having a local cache, an intermediate cache connected to the plurality of processors and having resources shared by the plurality of processors, and connected to the intermediate cache via a shared bus. A memory and a processor in one of the plurality of processors to obtain exclusive control of a storage unit, the exclusive control being maintained over a plurality of instructions executed for the storage unit, and A multiprocessor system having a lock control mechanism that enables the plurality of processors to use the shared bus except when there is a request for access to the storage unit from another processor of the plurality of processors. (21) The multiprocessor system according to (20), wherein the processor has a buffer control element, and the buffer control element has the lock control mechanism.

[Brief description of drawings]

FIG. 1 illustrates a plurality of processors and 3 according to the principles of the present invention.
FIG. 6 is a diagram illustrating an example of a multiprocessor system having a tiered storage hierarchy and a shared system bus.

2 is a diagram illustrating an example of a hardware configuration for the processor of FIG. 1 according to the principles of the present invention.

FIG. 3 is a diagram showing an example of an instruction for executing locking and unlocking according to the present invention.

4 is an enlarged view of the buffer control element of FIG. 2, particularly the components used in the lock / unlock mechanism of the present invention.

[Explanation of symbols]

 100 multiprocessor system 102 shared memory 104 intermediate cache (L2 cache) 106 shared bus 108 local cache (L1 cache) 200 instruction unit 202 execution unit 204 buffer control element

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Stephen Gardner Grassen United States 12589, New York, Wallkill, Sherwood Drive 11 (72) Inventor Park-Kin Mc United States 12603, New York, Powkeepsie, Ridgewood・ Terrace 13 (72) Inventor William Wu Shen United States 12603, New York State, Pawkeepsie, Keller House Drive 18 (72) Inventor Chun-Ran Keben Sham United States 12603, New York State, Powkeepsie, Sutton Park Lord 31 (72) Inventor Charles Franklin Webs Pawkeepsie, 12603 New York, USA , Meinetti drive 4

Claims (21)

[Claims] 1. A plurality of processors each having a local cache, an intermediate cache having resources shared by the plurality of processors and shared by the plurality of processors, and to the intermediate cache via a shared bus. A memory to be connected and a processor of the plurality of processors to obtain exclusive control of a storage unit, the exclusive control is provided to a plurality of instructions executed by using the storage unit. And an exclusive control acquisition means for maintaining the shared bus by the plurality of processors except when there is a request for access to the storage unit from another processor of the plurality of processors. Having a multi-processor
system. 2. The above-mentioned 1 until the exclusive control is released.
2. The multiprocessor system of claim 1 including means for maintaining said plurality of instructions in said local cache of said processor. 3. The local instructions of the one processor without the instructions being present in the intermediate cache.
The multiprocessor system of claim 2, wherein the means for maintaining the plurality of instructions so that they can reside in a cache comprises means for relaxing a subset rule that exists between the local cache and the intermediate cache. . 4. The multiprocessor system according to claim 1, further comprising means for releasing exclusive control of the storage unit. 5. The exclusive control acquiring means and the exclusive control releasing means have a buffer control element.
The multiprocessor system described in. 6. A plurality of processors each having a local cache, an intermediate cache having resources shared by the plurality of processors and shared by the plurality of processors, and to the intermediate cache via a shared bus. A method of gaining exclusive control of a storage unit in a multiprocessor system having a memory connected thereto, wherein one processor obtains exclusive control of a designated storage unit. To initiate a lock operation, and to give the one processor exclusive control of the storage unit to lock the storage unit over a plurality of instructions executed by the one processor. The plurality of processors except when there is a request for access to the storage unit from another processor of the processors. Method of acquiring exclusive control of the storage unit in a multi-processor system and executing the locking operation so as to allow the shared bus utilization by the processor. 7. The method of claim 6, wherein the storage unit is specified by an address contained in an instruction specifying the lock operation. 8. The method of claim 7, wherein the instructions include internal code of the multiprocessor system. 9. The method of claim 6 including the step of releasing exclusive control of the storage unit. 10. The method of claim 9, wherein the release is specified by an instruction containing internal code of the multiprocessor system. 11. The method of claim 9, wherein the lock operation and the release are performed within a buffer control element of the one processor. 12. When the instructions are not in the local cache of the one processor, the instructions are accessed locally to access the storage unit before gaining exclusive control of the storage unit. 7. The method of claim 6 including fetching into cache and maintaining the plurality of instructions in the local cache until the exclusive control is released. 13. The local maintenance step such that the maintaining step allows the plurality of instructions to be present in the local cache without being present in the intermediate cache.
13. The method of claim 12, comprising relaxing the subset rules that exist between the cache and the intermediate cache. 14. Placing a lock command in a command register that will be accessed during the execution of the lock operation prior to executing the lock operation; and connecting to the intermediate cache. Storing the data located in one or more buffers in the intermediate cache. 15. The step of performing the lock operation stores the address of the storage unit to be locked in a lock register, and sets a lock valid bit indicating exclusive control of the storage unit. 7. The method of claim 6, comprising: 16. A plurality of processors each having a local cache, an intermediate cache having resources shared by the plurality of processors and shared by the plurality of processors, and to the intermediate cache via a shared bus. A multiprocessor having a connected memory and
A method for gaining exclusive control of a storage unit in a system, the plurality of instructions relating to a locked storage unit stored prior to locking the storage unit in a local cache of a processor of the plurality of processors. And retaining the plurality of instructions in the local cache until the lock is released; and a lock operation for giving the one processor exclusive control of the storage unit to the one processor. A step of executing exclusive control, wherein the exclusive control is retained over the plurality of instructions, the method for obtaining exclusive control of a storage unit in a multiprocessor system. 17. The step of executing comprises generating a millicode instruction that specifies an address of the storage unit to be locked; loading the address into a lock register and locking the storage unit. Using a lock control mechanism to set a lock valid bit indicating that. 18. The method of claim 17 including releasing exclusive control of the storage unit, the releasing step including resetting a lock valid bit to indicate that the storage unit is not locked. the method of. 19. A plurality of processors each having a local cache, an intermediate cache having resources shared by the plurality of processors and shared by the plurality of processors, and to the intermediate cache via a shared bus. A multiprocessor having a connected memory and
A method of controlling the local presence of code lines in a system, the method comprising the steps of: directing one or more code lines to be read-only; Maintaining the one or more code lines designated as read-only in the local cache without the one or more code lines being present in the intermediate cache. Can exist in the local
A method of controlling the local presence of a code line in a multiprocessor system comprising the step of relaxing a subset rule between a cache and said intermediate cache. 20. A plurality of processors each having a local cache, an intermediate cache having resources shared by the plurality of processors and shared by the plurality of processors, and to the intermediate cache via a shared bus. A memory to be attached and a processor of the plurality of processors to obtain exclusive control of a storage unit, the exclusive control being maintained over a plurality of instructions executed for the storage unit. And a lock control mechanism which enables the plurality of processors to use the shared bus except when there is a request for access to the storage unit from another processor of the plurality of processors. 21. The multiprocessor system of claim 20, wherein the processor has a buffer control element, and the buffer control element has the lock control mechanism.