JPH0828118B2 - Data bus clamp circuit for semiconductor memory device - Google Patents

Description

The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM), a static random access memory (hereinafter referred to as SRAM), a read only memory. The present invention relates to a data bus clamp circuit in a semiconductor memory device such as a memory (hereinafter referred to as ROM).

(Prior Art) Conventionally, as a semiconductor memory device of this type, for example, a second
There were the ones shown in FIGS. The configuration will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of a conventional DRAM.

This DRAM has a plurality of divided memory blocks 10-1,
10-2 and their respective memory blocks 10-1, 10-2
Are memory cell arrays 11-1 and 11-2 for storing data, row address decoders 12-1 and 12-2, and sense amplifiers 13-1 and 13
-2 and column address decoders 14-1 and 14-2. Here, the row address decoders 12-1 and 12-2 are
This circuit decodes the address signal fetched by the row address strobe signal () and selects the memory cells in the row direction of the memory cell arrays 11-1 and 11-2 via the word line WL. The memory cell arrays 11-1 and 11-2 have sense amps 13-1 and 13-2 via complementary bit lines BL and ▲ ▼.
And column address decoders 14-1 and 14-2 are connected to each other, and the column address decoders 14-1 and 14-2 are connected to complementary sub data buses SDB, ▲ ▼. The sense amplifiers 13-1 and 13-2 are circuits for detecting and amplifying read data on the bit line BL, {circle around (▼)}. Column address decoder
14-1, 14-2 are selected column decoder enable signals
A circuit that decodes an address signal based on Yde1 and Yde2 and selects the column direction of the memory cell arrays 11-1 and 11-2.

Sub data bus SDB, ▲ ▼ is a switch circuit 20-
It is connected to complementary data buses DB, ▲ ▼ via 1, 20-2. The switch circuits 20-1 and 20-2 have a function of opening and closing between the sub data bus SDB, ▲ ▼ and the data bus DB, ▲ ▼ based on the selected column decoder enable signals Yde1 and Yde2. ing. The column decoder enable signals Yde1 and Yde2 are output from the block selection circuit 21 based on the column decoder enable signal Yde and the block signal CB.

A data bus pull-up circuit 22, a data bus clamp circuit 23, and a differential amplification type read circuit 24 are connected to the data bus DB, ▲ ▼. The data bus pull-up circuit 22 receives the data bus DB, based on the row address latch signal RAS.
The circuit for raising ▲ ▼ to near the power supply potential Vcc, and the data bus clamp circuit 23 is a circuit for clamping the data bus DB, ▲ ▼ to a predetermined potential based on the row address latch signal RAS. Further, the differential amplification type read circuit 24 amplifies the potential difference between the complementary data buses DB and ▲ ▼ to read data D.
This is a circuit that outputs out.

FIG. 3 is a circuit diagram of the switch circuits 20-1 and 20-2 in FIG.

The switch circuits 20-1 and 20-2 are turned on and off by the column decoder enable signals Yde1 and Yde2 to open / close the sub data bus SDB and the data bus DB 30.
And a switch means 31 for opening / closing the sub-data bus ▲ ▼ and the data bus ▲ ▼ by turning on / off by the signals Yde1 and Yde2. Further, the sources of N-channel MOS transistors (hereinafter referred to as NMOSs) 32 and 33 are connected to the sub-data buses {circle around (S)}, SDB, and their gates and drains are connected to the power supply potential Vcc.

FIG. 4 is a circuit diagram of the data bus pull-up circuit 22 shown in FIG.

The data bus pull-up circuit 22 has an inverter 40 that inverts the row address latch signal RAS.
The output side of 0 is connected to the gates of the two NMOSs 41 and 42. The drains of the NMOSs 41 and 42 are connected to the power supply potential Vcc, and the sources are connected to the data bus DB, ▲ ▼, respectively.

FIG. 5 is a circuit diagram of the data bus clamp circuit 23 in FIG.

The data bus clamp circuit 23 includes NMOS 50 and 51 connected in series between the data bus DB and the ground potential and the data bus ▲ ▼.
And NMOSs 52 and 53 connected in series between the ground potential and the ground potential, and the NMOSs 50 and 52 are turned on and off by the row address latch signal RAS.

The operation of the DRAM configured as described above will be described with reference to FIG. Note that FIG. 6 shows the NMOS 50-
FIG. 13 is an operation waveform diagram when the mutual conductance of 53 is small.

For example, a read operation for the memory cell array 11-1 of FIG. 2 will be described.

In FIG. 6, the row address strobe signal ▲
During the standby (standby) period when ▼ is at high level (hereinafter referred to as “H”), the row address latch signal RAS is at low level (hereinafter referred to as “L”) and the column decoder enable signal.
Yde, Yde1 and Yde2 are “L”. Row address latch signal RAS
Is "L", the NMOSs 50 and 52 in the data bus clamp circuit 23 of FIG. 5 are in the off state. On the other hand, in the data bus pull-up circuit 22 of FIG. 4, the NMOS4 having the threshold voltage Vth
Since 1, 42 are in the ON state, the potential of the data bus DB, ▲ ▼ becomes (Vcc-Vth).

When the row address strobe signal ▲ ▼ falls to "L" and enters the active period, the row address latch signal RA
S rises to "H", then column decoder enable signal Y
de rises to "H". Then, the block selection circuit 21 of FIG. 2 selects, for example, the signal Yde1 of the column decoder enable signals Yde1 and Yde2, and it becomes "H".

When the row address latch signal RAS becomes "H", the row address decoders 12-1, 12-2 cause the memory cell array 11-1,
The row direction of 11-2 is selected, and the data of the selected memory cell is transferred to the bit line BL, ▲ ▼ and the sense amplifier 13−.
It is supplied to the column address decoders 14-1 and 14-2 via 1, 13-2. On the other hand, when the row address latch signal RAS becomes "H", the data bus pull-up circuit 22 shown in FIG. 4 is turned off and NM in the data bus clamp circuit 23 shown in FIG.
The OS50 to 53 are turned on, and the charges on the data bus DB, ▲ ▼ are gradually discharged to the ground potential.

When the column decoder enable signal Yde1 becomes “H”, the column address decoder 14-1 causes the pair of bit lines BL, ▲
The data above ▼ is transferred to the sub data bus SDB, ▲ ▼, and the data is further transferred to the data bus DB, ▲ ▼ through the switch circuit 20-1. Therefore, a potential difference corresponding to the bit line data is generated in the data bus DB, ▲ ▼, and the potential difference is amplified by the differential amplification type read circuit 24 and then output as the read data Dout.

Row address strobe signal ▲ ▼ changes from "L" to "H"
In the standby period, the switch circuit 20-1 is turned off by the fall of the column decoder enable signal Yde1 to "L", and the data is turned on by the fall of the row address latch signal RAS to "L". When the bus clamp circuit 23 turns off, the data bus pull-up circuit 22
Turns on, the data bus DB, ▲ ▼ becomes the same potential, and the read operation ends.

Now, consider a case where the power supply potential Vcc, for example, drops from 6V to 4V in the active period.

When the power supply potential Vcc drops from 6V to 4V, the row address latch signal RAS of "H" drops from 6V to 4V, and the "H" potential of the column decoder enable signals Yde and Yde1 also becomes 4V.
In the data bus clamp circuit 23 of FIG.
When the transconductance of 53 is small, the rise of the row address latch signal RAS causes the charges of the data bus DB, ▲ ▼ to be discharged little by little, and the column decoder enable signal.
When Yde1 becomes “H”, the data on the bit line BL, ▲ ▼ is transferred to the data bus DB, ▲ ▼, and the potential difference ΔV1 occurs after the time t1.

On the other hand, when the mutual conductance of the NMOSs 50 to 53 is large, as shown in the operation waveform diagram of FIG. 7, when the row address latch signal RAS rises to "H", the data bus D
When the charge of B, ▲ ▼ is rapidly discharged and the column decoder enable signal Yde1 becomes “H”, the bit line data is transferred to the data bus DB, ▲ ▼, and the potential difference Δ after the time t2.
2.

As described above, in the conventional DRAM, the data bus clamp circuit 23 is provided, and during the active period, the data bus DB, ▲
By discharging the electric charge of ▼ to the ground potential, the power supply potential
When Vcc decreases, the potential of the data bus DB, ▲ ▼ is set to a set value, and the differential amplification type read circuit 24 operated by the potential difference ΔV1, ΔV2 of the data bus DB, ▲ ▼
The delay of the reading speed was prevented.

(Problems to be Solved by the Invention) However, the data bus clamp circuit 23 having the above configuration
Then, there were the following problems.

The row address strobe signal ▲ ▼ becomes “L”,
If the power supply potential Vcc drops within the time when the column address decoders 14-1 and 14-2 are enabled by the column decoder enable signals Yde1 and Yde2, the data bus DB, ▲ in FIG.
Since the potential difference ΔV1 between ▼ is large, the operation speed of the read circuit 24 becomes slow. In addition, in FIG. 7, the data bus
Potential difference ΔV formed by increasing from low potential of DB, ▲ ▼
Since 2 is read by the read circuit 24, the operation speed of the read circuit 24 becomes slow and it is difficult to solve them.

SUMMARY OF THE INVENTION The present invention provides a data bus clamp circuit for a semiconductor memory device, which solves the problem that the above-mentioned conventional technique has that the operation speed of the read circuit becomes slow due to a decrease in the power supply potential during the active period.

(Means for Solving the Problem) In order to solve the above problems, a first invention is to decode a plurality of divided memory cell arrays for storing data and an address signal taken in by a first control signal. A plurality of row address decoders that respectively select the row direction of each of the memory cell arrays, and an address signal is decoded based on a second control signal delayed from the first control signal to change the column direction of the memory cell array. A plurality of column address decoders to be selected, a pair of data buses for transmitting data read from the memory cell array, the first
A semiconductor memory device comprising a data bus clamp circuit that clamps the pair of data buses to a predetermined potential during an active period of the control signal, and a differential amplification type read circuit that reads data on the pair of data buses, The data bus clamp circuit is configured as follows.

That is, the data bus clamp circuit of the present invention is the first bus
A first discharge circuit that discharges the charges of the pair of data buses during an active period of the control signal, and a second discharge circuit that discharges the charges of the pair of data buses for a certain period of time based on the second control signal. have.

In a second aspect based on the first aspect, the data bus clamp circuit is connected between the pair of data buses and a power supply potential source, and a third control signal generated from the first control signal. And a first discharge circuit formed of a switch circuit for electrically connecting the pair of data buses and a power supply potential source in response to the first discharge circuit, and the first discharge circuit connected in parallel with the first discharge circuit and generated from the second control signal. And a second discharge circuit formed of a switch circuit for electrically connecting the pair of data buses and the power supply potential source in response to the generated fourth signal.

In a third aspect based on the first or second aspect, the mutual conductance of the second discharge circuit is larger than the mutual conductance of the first discharge circuit.

In a fourth aspect based on the first, second or third aspect, the first control signal is a row address strobe signal,
The second control signal is a column decoder enable signal, the third control signal is a row address latch signal, and the fourth
Is a one-shot pulse.

(Operation) According to the first, second, third, and fourth inventions, since the data bus clamp circuit is configured as described above, the first discharge circuit is configured by, for example, an element having a small mutual conductance. By doing so, in the active period in which the first control signal (row address strobe signal) is "L", the electric charges of the pair of data buses are gradually discharged.
In addition, the second discharge circuit, for example, by configuring it with an element having a large transconductance, works to rapidly discharge the charges of the pair of data buses for a certain period when the power supply potential decreases. Therefore, for example, when the first control signal (row address strobe signal) becomes “L” and the power supply potential drops within the time when the column address decoder is enabled, the potential of the pair of data buses is changed to the power supply potential. As a result, the differential amplification type read circuit can always be operated at the same operating speed. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a data bus clamp circuit showing an embodiment of the present invention.

This data bus clamp circuit is provided in place of the conventional data bus clamp circuit 23 in the DRAM of FIG. 2, and includes a first discharge circuit composed of NMOSs 60, 61, 62 and 63,
It is composed of a one-shot pulse generator 70 and a second discharge circuit composed of NMOSs 80, 81, 82 and 83.

In the first discharge circuit, one of the data buses in FIG.
The drain of NMOS60 is connected to DB, and the gate of NMOS60 is the row address latch signal RAS of FIG. 2 and the source is NMO.
They are connected to the drain and gate of S61, respectively. N
The source of MOS61 is connected to the ground potential. The drain of the NMOS 62 is connected to the other data bus ▲ ▼ in FIG. 2, and the gate of the NMOS 62 is connected to the row address latch signal RA.
The source of S63 is connected to the drain and gate of the NMOS 63, respectively. The source of the NMOS 63 is connected to the ground potential. These NMOSs 60 to 63 have a small mutual conductance.

In the second discharge circuit, the one-shot pulse generator
70 has a function of inputting the column decoder enable signal Yde of FIG. 2 and outputting a pulse OSP of "H" for a fixed time in synchronization with the rise of the signal Yde from "L" to "H". ing. The one-shot pulse generator 70 has, for example, three stages of inverters 71 to 73 that delay the column decoder enable signal Yde, and the outputs of the inverters 71 to 73 and the column decoder enable signal Yde are two-input NAND gates (hereinafter referred to as “nand gates”). , NAND) 74 and its NAND gate
The output of 74 is connected to the node N via the inverter 75. The gate of the NMOS 80 is connected to the node N, and its NM
OS80 drain is one data bus DB, source is NMOS
It is connected to the drain and gate of 81. The source of the NMOS 81 is connected to the ground potential. Furthermore, at node N
The gate of the NMOS 82 is connected, the drain of the NMOS 82 is connected to the other data bus (2), and the source is connected to the drain and gate of the NMOS 83. The source of the NMOS 83 is connected to the ground potential. These NMOSs 80 to 83 have a large mutual conductance.

Next, with reference to FIG. 2 and FIG. 8, the operation of the data bus clamp circuit of this embodiment at the time of reading data will be described. Note that FIG. 8 is an operation waveform diagram of FIG.

In FIG. 8, the row address strobe signal ▲
During the standby period when ▼ is H, the row address latch signal RAS and the column decoder enable signals Yde, Yde1 and Yde2, which are in opposite phase to the signal ▲, are "L". When the column decoder enable signals Yde1 and Yde2 are "L", the switch means 30 and 31 in the switch circuits 20-1 and 20-2 shown in FIG. 3 are off, so that the NMOS 32 and 33 having the threshold voltage Vth The potential of the sub data bus SDB, ▲ ▼ becomes (power supply potential Vcc-threshold voltage Vth). Further, when the column decoder enable signal Yde and the row address latch signal RAS are "L", the node N in the data bus clamp circuit becomes "L", and the NMOSs 60, 62,
80, 82 is off. On the other hand, in the data bus pull-up circuit 22 of FIG. 4, since the NMOSs 41 and 42 having the threshold voltage Vth are in the ON state, the potential of the data bus DB, ▲ ▼ becomes (Vcc-Vth).

When the row address strobe signal ▲ ▼ falls to "L" and enters the active period, the row address latch signal RAS rises to "H" in synchronization with the signal ▲ ▼, and after a fixed time from the rise of the signal RAS. The column decoder enable signal Yde rises to "H". When the column decoder enable signal Yde rises to "H", the block selection circuit 21 of FIG. 2 selects, for example, the signal Yde1 of the column decoder enable signals Yde1 and Yde2 by the block selection signal CB and sets it to "H". "I will. The other signal Yde2 remains "L". In addition, the column decoder enable signal Yde "H"
As a result, the one-shot pulse generator 70 in the data bus clamp circuit of FIG. 1 outputs a pulse OSP having a constant time width to the node N. That is, in the one-shot pulse generator 70, when the column decoder enable signal Yde becomes “H”, the NAN
The node N rises to "H" through the D gate 74 and the inverter 75, and the node N is pulled down to "L" after the elapse of a certain delay time generated by the inverters 71 to 73.

When the row address latch signal RAS becomes "H", the row address decoders 12-1 and 12-2 in FIG. 2 decode the address signal and pass through the word line WL to the memory cell arrays 11-1 and 11-2.
Select the memory cell in the middle row direction. The data of the selected memory cell is detected and amplified by the sense amplifiers 13-1 and 13-2 through the bit line BL, and is supplied to the column address decoders 14-1 and 14-2. On the other hand, when the row address latch signal RAS becomes “H”, the NMOSs 41 and 42 in the data bus pull-up circuit 22 in FIG.
The NMOSs 60 to 63 in the data bus clamp circuit of FIG. 1 turn on, and the data buses DB, ▲
▼ The above charge is discharged to the ground potential. At this time, NMOS60 ~
Since the mutual conductance of 63 is set small, the charges on the data bus DB, ▲ ▼ are gradually discharged.

When the column decoder enable signal Yde1 becomes "H", the second
The column address decoder 14-1 in the figure decodes the address signal and selects a pair of bit lines BL, ▲ ▼, and the bit line B
Data on L, ▲ ▼ sub data bus SDB, ▲ ▼
Transfer to The data on the sub data bus SDB, ▲ ▼ is the switch means 3 in the ON state in the switch circuit 20-1.
Since the data is transferred to the data bus DB, ▲ ▼ through 0 and 31, a potential difference corresponding to the bit line data is generated in the data bus DB, ▲ ▼. This potential difference is amplified by the differential amplification type read circuit 24 and then output as read data Dout. Further, in synchronization with the rise of the column decoder enable signal Yde to “H”, the one-shot pulse generator 70 in the data bus clamp circuit of FIG.
When P is output, NMO in the data bus clamp circuit
S80 to 83 are turned on for the pulse width time, data bus DB, ▲
▼ Discharge the above charge to the ground potential. At this time, NMOS80 ~
Since 83 has a large mutual conductance,
The charges on the data bus DB, ▲ ▼ are rapidly discharged.

Row address strobe signal ▲ ▼ changes from "L" to "H"
When it rises to the standby period, the signal ▲
The row address latch signal RAS falls to "L" in synchronization with ▼, and the column decoder enable signals Yde and Yde1 also fall to "L" due to the signal RAS. When the column recorder enable signal Yde1 becomes "L", the switch means 30 and 31 in the switch circuit 20-1 are turned off. Further, depending on the “L” state of the signal OSP and the “L” state of the row address latch signal RAS, the NMOS 60, 62, 80, 8 of the data bus clamp circuit of FIG.
2 is turned off, and NM in the data bus pull-up circuit 22 of FIG.
The OS41 and 42 are turned on, the data bus DB and ▲ ▼ become the same potential, and the read operation is completed.

Here, in FIG. 8, the row address strobe signal ▲
Column decoder enable signal after ▼ becomes “L”
The power supply potential Vcc changes from 6V in the time until Yde becomes “H”.
Consider the case when it drops to 4V.

When the row address latch signal RAS rises to "H" in synchronization with the fall of the row address strobe signal ▲ ▼ to "L", the data bus DB, ▲ ▼ becomes the transconductance in the data bus clamp circuit of FIG. Small NMOS
By 60-63, the electric charge is discharged little by little. After that, the column decoder enable signals Yde, Yde1 are "L" (= 0V)
When rising from "H" (= 4V) from the sub data bus SDB, ▲
The above bit line data is transferred to the data bus DB, ▲ ▼ via the switch circuit 20-1, and at the same time, the first
Data bus DB, ▲ ▼ by NMOS 80 to 83 with large transconductance in the data bus clamp circuit in the figure.
Is quickly discharged, and during the time t3, the data bus D
The potential difference between B and ▲ ▼ is ΔV3. In this way, when the power supply potential Vcc drops from 6V to 4V, the potential of the data bus DB, ▲ ▼ is also lowered so as to follow it, so that the potential of the data bus DB, ▲ ▼ is the optimum value (for example, 1 V) and the potential difference ΔV3 is also the optimum value, so that the operation speed of the differential amplification type readout circuit 24 can be improved.

When the power supply potential Vcc rises from 4V to 6V and returns to the normal state, the data bus DB, ▲ ▼ is quickly charged by the NMOS 32, 33 in the switch circuit 20-1 of FIG.
This ensures high-speed operation of the differential amplification type readout circuit 24.

To write data in the DRAM of FIG. 2,
A write circuit is connected to the data bus DB, ▲ ▼, and input data is transferred via the write circuit to the data bus DB, ▲ ▼.
Put it on top. Then, the data on the data bus DB, ▲ ▼ is switched to the switch circuits 20-1, 20-2, the sub data bus SDB, ▲.
, And the column address decoders 14-1 and 14-2 may be used to write in the memory cell arrays 11-1 and 11-2.

The present invention is not limited to the illustrated embodiment, and various modifications can be made. The following are examples of such modifications.

(A) The entire structure of the semiconductor memory device can be modified to a structure other than that shown in FIG. 2, and it may be another semiconductor memory device such as SRAM or ROM other than DRAM.

(B) In the data bus clamp circuit of FIG. 1, NM
The OSs 60 to 63, 80 to 83 may be composed of other semiconductor elements such as P channel MOS transistors. The one-shot pulse generator 70 may change the delay time by changing the number of the inverters 71 to 73, or may have a circuit configuration other than that shown in FIG.

(Effect of the Invention) As described in detail above, according to the first, second, third, and fourth inventions, the data bus clamp circuit is composed of the first and second discharge circuits. Even if the power supply voltage drops by the time until the first control signal (row address strobe signal) is "L" and the column address decoder is enabled, the first and second discharge circuits promptly change the data bus voltage. The charge can be discharged. Therefore, the differential amplification type readout circuit can always be operated at a high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a data bus clamp circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional DRAM, and FIG.
FIG. 4 is a circuit diagram of the switch circuit in FIG. 2, FIG. 4 is a circuit diagram of the data bus pull-up circuit in FIG. 2, and FIG.
6 is a circuit diagram of the data bus clamp circuit in the figure, FIG. 6 and FIG. 7 are operation waveform diagrams of FIG. 2, and FIG. 8 is an operation waveform diagram of FIG. 11-1, 11-2 ... Memory cell array, 12-1,12-2 ...
Row address decoder, 14-1, 14-2 ... Column address decoder, 20-1, 20-2 ... Switch circuit, 21 ... Block selection circuit, 22 ... Data bus pull-up circuit, 23 ... Data bus Clamp circuit, 24 ... Differential amplification type readout circuit,
60 to 63, 80 to 83 …… NMOS, 70 …… One-shot pulse generator.

Claims (4)

[Claims] 1. A plurality of divided memory cell arrays for storing data and a plurality of row addresses for decoding the address signal fetched by a first control signal to select the row direction of each memory cell array. A decoder, a plurality of column address decoders for decoding an address signal based on a second control signal delayed from the first control signal to select a column direction of the memory cell array, and data read from the memory cell array , A data bus clamp circuit that clamps the pair of data buses to a predetermined potential during the active period of the first control signal, and a differential amplifier that reads data on the pair of data buses. A semiconductor memory device including a type read circuit, wherein the data bus clamp circuit includes the first control signal A first discharge circuit that discharges the charges of the pair of data buses in an active period; and a second discharge circuit that discharges the charges of the pair of data buses for a certain period of time based on the second control signal. And a data bus clamp circuit for a semiconductor memory device. 2. The data bus clamp circuit is connected between the pair of data buses and a power supply potential source,
A first discharge circuit including a switch circuit for electrically connecting between the pair of data buses and a power supply potential source in response to a third control signal generated from the first control signal; and the first discharge. A second discharge circuit including a switch circuit connected in parallel with the circuit and electrically connecting between the pair of data buses and the power supply potential source in response to a fourth control signal generated from the second control signal. The data bus clamp circuit of the semiconductor memory device according to claim 1, further comprising: 3. A data bus clamp circuit for a semiconductor memory device according to claim 1, wherein a transconductance of said second discharging circuit is larger than a transconductance of said first discharging circuit. 4. The first control signal is a row address strobe signal, the second control signal is a column decoder enable signal, the third control signal is a row address latch signal, and the fourth control signal is one. 4. The data bus clamp circuit for a semiconductor memory device according to claim 1, wherein the data bus clamp circuit is a shot pulse.