JPH08279517A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: To enable the manufacturing step to be simplified as well as a semiconductor device to be miniaturized by a method wherein the side of an ohmic electrode is decomposed in an etching resistant denatured layer as well as provided with a semiconductor mesa part self-aligning with the ohmic electrode containing the denatured layer. CONSTITUTION: A subcollector layer 2, a collector layer 3, a base layer 4 are continuously epitaxial grown by organic metallic vapor growth process on a semiinsulating semiconductor substrate 1 further to deposit an emitter layer 5 and a contact layer 6. Next, an ohmic electrode 7 is formed on the upper part of the deposited emitter layer 5 and coated layer 6 for ion-implanting the side of the ohmic layer 7 so that the side may be decomposed in an etching resistant denatured layer 8 as well as to form a self-aligning semiconductor mesa part 12 by masa-etching the semiconductor layers 5, 6 using the ohmic electrode 7 containing the denatured layer 8. Through these procedures, the manufacturing steps can be simplified thereby enabling the semiconductor device to be miniaturized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, such as a HBT (heterojunction bipolar transistor) used as a self-alignment mask by enhancing the etching resistance of an ohmic electrode made of a high melting point material. The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable increase in the performance of semiconductor integrated circuit devices, and this applies not only to silicon semiconductor integrated circuit devices but also to compound semiconductor integrated circuit devices using GaAs or the like.

Although such high performance has been achieved by improving the performance of the element itself such as the element structure,
Other than that, it is desired to reduce the parasitic resistance and the parasitic capacitance due to the electrodes or the wiring.

Conventionally, in a GaAs-based compound semiconductor integrated circuit device, an InGaAs layer having a band gap smaller than that of the GaAs layer is grown on the GaAs layer in order to reduce the parasitic series resistance associated with the ohmic electrode. An ohmic electrode was provided on the InGaAs layer.

In recent years, I as an ohmic contact layer
The composition of the nGaAs layer is In_0.7Ga _0.3Assume about As
In addition, as such an ohmic electrode material, WSi and
By using a high melting point material such as TiW, ohmic
The low resistance and the improved reliability of the electrode are obtained.

[0006]

[Problems to be Solved by the Invention] However, such a WS
Since high-melting-point materials such as i and TiW do not have good etching resistance, the semiconductor layer cannot be etched using the ohmic electrode as a mask to form a mesa structure such as an emitter mesa in a self-aligned manner, which simplifies the manufacturing process. And the miniaturization of semiconductor devices.

That is, when the emitter mesa is formed by the self-alignment process using the emitter electrode made of a high melting point conductive material as a mask, the emitter electrode undergoes side etching at an etching rate of several tens of liters / minute, which is favorable. It was difficult to obtain a mesa structure such as an emitter mesa with etching accuracy.

When the self-alignment process is not used,
Since it is necessary to align the emitter electrode with the mask at the time of mesa etching and a margin for the alignment is required, it is difficult to miniaturize the mesa structure such as the emitter mesa as the manufacturing process is increased.

Therefore, it is possible to adopt a self-alignment process by improving the etching resistance of the ohmic electrode made of a high melting point material, thereby simplifying the manufacturing process and miniaturizing the semiconductor device. And

[0010]

FIG. 1 is an explanatory view of the principle configuration of the present invention, and means for solving the problems in the present invention will be described with reference to FIG. Referring to FIG. 1, the present invention relates to a semiconductor device having an ohmic electrode 7 made of at least one high melting point conductive material, in which the side surface of the ohmic electrode 7 is transformed into an etching resistant transformation layer 8 and the transformation layer 8 is formed. The semiconductor mesa portion 12 is self-aligned with the included ohmic electrode 7.

Further, the present invention is characterized in that, in the semiconductor device, the high melting point conductive material is either WSi or TiW.

The present invention is also characterized in that the semiconductor device is a heterojunction bipolar transistor. Further, the present invention is characterized in that the ohmic electrode 7 is an emitter electrode of a heterojunction bipolar transistor.

Further, according to the present invention, in the method of manufacturing a semiconductor device having the ohmic electrode 7 made of at least one refractory conductive material, the ohmic electrode 7 is subjected to plasma treatment so that the side surface thereof is an etching resistant metamorphic layer. And the mesa etching of the semiconductor layers 5 and 6 using the ohmic electrode 7 including the metamorphic layer 8 as a mask.

Further, according to the present invention, in the method of manufacturing a semiconductor device having the ohmic electrode 7 made of at least one refractory conductive material, the side surface of the ohmic electrode 7 is ion-implanted and the side surface is transformed with etching resistance. The method is characterized by including a step of modifying the layer 8 and mesa-etching the semiconductor layers 5 and 6 using the ohmic electrode 7 including the metamorphic layer 8 as a mask.

In FIG. 1, 1 is a semi-insulating semiconductor substrate, 2 is a sub-collector layer, 3 is a collector layer, 4 is a base layer, 5 is an emitter layer, 6 is a contact layer, 9 is a base electrode, and 10 is a base electrode. The collector electrodes and 11 are insulation isolation regions.

[0016]

In the semiconductor device having the ohmic electrode 7 made of at least one refractory conductive material, the side surface of the ohmic electrode 7 is formed as the etching resistant metamorphic layer 8 so that the ohmic electrode 7 including the metamorphic layer 8 and the semiconductor. The mesa portion 12 can be provided in a self-aligned manner.

Further, according to the present invention, by using WSi or TiW as the high melting point conductive material, an ohmic electrode having low resistance and high reliability can be formed.

Further, according to the present invention, by applying the technical idea to a heterojunction bipolar transistor, a high-speed bipolar transistor having a small parasitic resistance can be realized, and an emitter mesa can be formed in a self-aligned manner. It is possible to further miniaturize and speed up the junction bipolar transistor.

Further, in the method of manufacturing a semiconductor device having the ohmic electrode 7 made of at least one refractory conductive material, the side surface of the ohmic electrode 7 is easily treated by the plasma treatment to form the etching-resistant metamorphic layer 8. Moreover, the semiconductor layers 5 and 6 are mesa-etched by a self-alignment process using the ohmic electrode 7 including the metamorphic layer 8 as a mask, which simplifies the manufacturing process and further miniaturizes the semiconductor device. can do.

Further, according to the present invention, in the method of manufacturing a semiconductor device having the ohmic electrode 7 made of at least one refractory conductive material, the side surface of the ohmic electrode 7 is ion-implanted and the side surface is easily etched. Can be transformed into the metamorphic layer 8 and the semiconductor layers 5 and 6 are mesa-etched by a self-alignment process using the ohmic electrode 7 including the metamorphic layer 8 as a mask. The device can be further miniaturized.

[0021]

EXAMPLE A heterojunction bipolar transistor according to an example of the present invention
The manufacturing process of the transistor will be described with reference to FIGS.
It See FIG. 2 (a). First, on the semi-insulating GaAs substrate 13, a metal organic chemical vapor deposition is performed.
N by the long method (MOVPE method)⁺Type GaAs sub-core
Layer 14, n-type GaAs collector layer 15, p ⁺Type Ga
As base layer 16, n-type AlGaAs emitter layer 17,
n⁺Type GaAs contact layer 18, n⁺Type InGaAs
Graded layer 19 and In_0.7Ga_0.3As Con
The tact layer 20 is continuously epitaxially grown.

The n-type AlGaAs emitter layer 17 is composed of n-type Al _0.3 Ga _0.7 As, and n ⁺ -type I
The nGaAs graded layer 19 is a layer that gradually changes from GaAs (In ratio 0) to In _0.7 Ga _0.3 As (In ratio 0.7).

Referring to FIG. 2B, a WSi emitter electrode 21 having a thickness of 300 nm to be an ohmic electrode is deposited by a sputtering method using WSi as a target.
SiON film 2 serving as a mask when patterning 1
2 is deposited by low pressure chemical vapor deposition (LPCVD). The thickness of the WSi emitter electrode 21 is 200
It may be in the range of up to 400 nm.

Next, referring to FIG. 3 (c), using the photoresist mask 23 as a mask, C
By dry etching using HF ₃ as a reaction gas, S
The iON film 22 is mesa-etched to a size corresponding to the emitter mesa.

Next, as shown in FIG. 3D, after removing the photoresist mask, SiO 2 is removed.
Using the N film 22 as a mask, the WSi emitter electrode 21 is patterned by the RIE (reactive ion etching) method, and then the nitrogen plasma 24 generated at an applied power of 500 W to 1.5 kW and a pressure of 5 to 10 Pa. By performing the treatment in the inside, N (nitrogen) atoms are introduced into the side surface, which is the exposed surface of the WSi emitter electrode 21, to change it into the metamorphic layer 25 having excellent etching resistance.

Next, as shown in FIG. 4E, the In _0.7 Ga _0.3 As contact layer 20 to the n-type AlGaAs emitter 17 are wet-coated with the WSi emitter electrode 21 having the metamorphic layer 25 formed on the side surface as a mask.
P ⁺ type GaAs base layer 1 by etching
6 is exposed and the emitter mesa 26 is formed in a self-aligned manner.

Next, after removing the SiON film, a base electrode 27 is formed by depositing and patterning Au.Zn serving as a base electrode, and then using a second photoresist mask 28. Then, the p ⁺ type GaAs base layer 16 is etched into a predetermined shape to form a base mesa 29.

Next, after removing the second photoresist mask 28, oxygen ions 31 are removed using the third photoresist mask 30 newly provided so as to cover the emitter mesa 26 and the base mesa 29 as a mask. By ion implantation,
The peripheral portion is insulated to form the insulating isolation region 32.

Next, after removing the third photoresist mask 30, the n-type GaAs collector layer 15 is etched using the newly provided fourth photoresist mask 33 as a mask to remove the n ⁺ -type. The GaAs sub-collector layer 14 is exposed to form a collector mesa 34, Au.Ge.Ni to be a collector electrode 35 is deposited, and the fourth photoresist mask 33 is removed to lift the collector electrode 35 by a lift-off method. Formed to complete the heterojunction bipolar transistor.

As described above, in the present invention, since the side surface of the WSi emitter electrode is nitrided to form the metamorphic layer having excellent etching resistance, the self-alignment process can be adopted, and therefore the low resistance emitter electrode is provided. In addition, the manufacturing process of the heterojunction bipolar transistor can be simplified and can be miniaturized with good reproducibility.

Next, another embodiment of the present invention will be described in which an ion implantation method is adopted as a means for improving the etching resistance of the emitter electrode. In this example, only the step of FIG. 3D is different and the other steps are substantially the same, so only the step of improving the etching resistance of the emitter electrode will be described.

In this case, after patterning the WSi emitter electrode using the SiON film as a mask, the main surface of the semiconductor wafer composed of the semi-insulating GaAs substrate to the In _0.7 Ga _0.3 As contact layer is irradiated in the irradiation direction of implanted ions. Accelerating energy of nitrogen ions (N ⁺ ) of 10 keV while rotating with a slight tilt from the vertical direction, and
By implanting ions at a dose of 1 × 10 ¹⁶ cm ^-2 , N atoms are introduced into the side surface of the WSi emitter electrode,
The modified layer 25 is excellent in etching resistance.

When the ion implantation method is used to form the metamorphic layer 25, the dose amount is 1 × 10 ¹⁶ cm ^-2.
It is not limited to 1 × 10 ^{15 to} 6 × 10 ¹⁶ cm
^It should be in the range of ^-2 .

In the nitrogen plasma treatment step or the nitrogen ion implantation step in each of the above embodiments, I
N atoms are also introduced to the surface of the n _0.7 Ga _0.3 As contact layer and are nitrided to some extent, but this does not cause any particular problem in the subsequent wet etching step in forming the emitter mesa, and there is a problem depending on the material system. When it occurs, the nitride layer on the surface may be removed in advance by the Ar ion milling method or the like.

Although WSi is used as the emitter electrode in each of the above embodiments, the composition ratio Si / W is used.
The (atomic ratio) may be in the range of 0.2 to 0.6, and TiW having a composition ratio Ti / W (atomic ratio) in the range of 0.2 to 0.6 may be used instead of WSi. It is good, and in this case, it may be deposited by a sputtering method using a TiW target.

In each of the above embodiments, the SiON film is used as a mask when patterning the emitter electrode, but the O / N ratio is arbitrary, and the S / N ratio is S.
It becomes a mask in the RIE process instead of the iON film,
For example, a SiO ₂ film or a Si ₃ N ₄ film may be used.

In the above embodiment, Al _0.3 Ga _0.7 As is used as the emitter layer and GaAs layers are used as the base layer and the collector layer, but the composition ratio is not limited to this. But AlGaAs with an Al ratio of 0.24 to 0.35 as the emitter layer
May be used, and A may also be used as the base layer.
AlGaAs having an l ratio of 0.1 to 0.00 may be used.

Further, although the contact layer in the above embodiment is In _0.7 Ga _0.3 As, the contact ratio is not limited to such a composition ratio, and the In ratio of In is 0.5 to 1.0.
GaAs may also be used.

In each of the above embodiments, the MOVPE method is used for growing the semiconductor layer, but the MBE method (molecular beam epitaxial growth method) or the ordinary VPE method (vapor phase growth method) may be used. Further, although oxygen ions are implanted at the time of forming the insulating separation region 32, hydrogen ions (protons) may be implanted.

In each of the above embodiments, the emitter top type npnHBT (heterojunction bipolar transistor) is used.
However, the present invention is also applicable to pnpHBTs, and is also applicable to collector-top type HBTs. In that case, the configuration of the collector section is n ⁺ -type. GaAs subcollector layer (contact layer)
On top, an n ⁺ -type InGaAs graded layer and In _0.7
The structure has a Ga _0.3 As contact layer.

In each of the above embodiments, AlGaAs / G
Although the description has been made by taking an aAs-based HBT as an example, the present invention is not limited to InP.
Other material systems such as InP / InGaAs system are also targeted, and in the case of InP / InGaAs system HBT, the contact layer structure of the emitter section is n ⁺ type In _0.53 Ga lattice-matched to InP which is the emitter. _0.47 As contact layer, n ⁺ type InGaAs graded layer, and In
The structure is a _0.7 Ga _0.3 As contact layer.

In each of the above embodiments, a single heterojunction type HBT in which only the emitter / base junction is a heterojunction is described, but the present invention is a double junction in which the base / collector junction is also a heterojunction. Heterozygous HBTs are also targeted.

Further, the object of the present invention is not limited to HBT, but various semiconductor devices, such as HET (hot electron transistor) or RHET, which form a mesa structure by using an ohmic electrode made of a high melting point conductive material as a mask. (Resonant tunnel hot electron transistor) and the like are also targeted.

[0044]

According to the present invention, a mesa structure can be formed in a self-aligned manner with the ohmic electrode by increasing the etching resistance of the side surface of the ohmic electrode made of a high melting point conductive material. A high-performance compound semiconductor device such as a transistor can be miniaturized with good reproducibility, and the manufacturing process thereof can be simplified.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory view of a manufacturing process up to the middle of the embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process up to the middle of FIG. 2 and subsequent steps of the embodiment of the present invention.

FIG. 4 is an explanatory view of a manufacturing process up to the middle of FIG. 3 and subsequent steps of the embodiment of the present invention.

FIG. 5 is an explanatory view of the manufacturing process after FIG. 4 of the embodiment of the present invention.

[Explanation of symbols]

1 semi-insulating semiconductor substrate 2 sub-collector layer 3 collector layer 4 base layer 5 emitter layer 6 contact layer 7 ohmic electrode 8 metamorphic layer 9 base electrode 10 collector electrode 11 insulating isolation region 12 semiconductor mesa portion 13 semi-insulating GaAs substrate 14 n ⁺ Type GaAs subcollector layer 15 n type GaAs collector layer 16 p ⁺ type GaAs base layer 17 n type AlGaAs emitter layer 18 n ⁺ type GaAs contact layer 19 n ⁺ type InGaAs graded layer 20 In _0.7 Ga _0.3 As contact layer 21 WSi Emitter electrode 22 SiON film 23 Photoresist mask 24 Nitrogen plasma 25 Metamorphic layer 26 Emitter mesa 27 Base electrode 28 Second photoresist mask 29 Base mesa 30 Third photoresist mask 31 Oxygen ion 32 Insulation isolation region 33 Fourth Photoresist Mask 34 Collector Mesa 35 Collector Electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 29/43 H01L 29/46 R

Claims (6)

[Claims] 1. A semiconductor device having an ohmic electrode made of at least one refractory conductive material, wherein a side surface of the ohmic electrode is transformed into an etching resistant metamorphic layer, and an ohmic electrode including the metamorphic layer is provided. A semiconductor device having a self-aligned semiconductor mesa portion. 2. The semiconductor device according to claim 1, wherein the high melting point conductive material is either WSi or TiW. 3. The semiconductor device according to claim 1, wherein the semiconductor device having the ohmic electrode made of at least one refractory conductive material is a heterojunction bipolar transistor. 4. The semiconductor device according to claim 3, wherein the ohmic electrode is an emitter electrode. 5. A method for manufacturing a semiconductor device having an ohmic electrode made of at least one refractory conductive material, wherein a side surface of the ohmic electrode is transformed into an etching resistant metamorphic layer by plasma-treating the ohmic electrode. And a step of mesa-etching the semiconductor layer using the ohmic electrode as a mask. 6. A method of manufacturing a semiconductor device having an ohmic electrode made of at least one high melting point conductive material, wherein ion implantation is performed on a side surface of the ohmic electrode.
A method of manufacturing a semiconductor device, comprising the step of modifying the side surface of the ohmic electrode into a modified layer having etching resistance and mesa-etching the semiconductor layer using the ohmic electrode as a mask.