JPH08279248A - Digital signal decoding device - Google Patents

Abstract

PURPOSE: To make it possible to integrate processing circuits, to reduce the size of the above device and to improve its reliability by digitalizing the processing at the time of pattern detection. CONSTITUTION: An A/D converter 20A samples a reproduced signal S13 asynchronously with a recording data present point at the time of out of step and samples the signal S13 at the position of the recording data present point and outputs the reproduced data S18 at the time of in step. At this time, a frequency of three times the recording data rate is used as a sampling frequency. The execution of the detection processing of synchronous patterns is made possible by the signal processing of the data S18 sampling the signal S13 and, therefore, the integration of a synchronous pattern detecting circuit and several processing circuits including this circuit is possible and the reduction of the size is embodied. The recording data is detectable even before the synchronous state is established by using the data S18 obtd. by sampling the signal S13 with the frequency of 3 times the data rate.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problem to be Solved by the Invention Means for Solving the Problem Action Example (1) Overall configuration (2) Configuration of sync pattern detection circuit (2-1) Overall configuration (2-2) ) Configuration of ternary data detector (2-3) Configuration of ternary correlation determiner (2-4) Configuration of optimum time detection circuit (2-5) Configuration of protection interpolation circuit (3) Synchronous detection operation (4 ) Other Examples Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal decoding device and can be applied to, for example, a magnetic disk device.

[0003]

2. Description of the Related Art Currently used magnetic disk devices can be classified into self-synchronous magnetic disk devices and external synchronous magnetic disk devices according to their synchronization systems. Among them, the self-synchronous magnetic disk device is a general term for a device that reproduces a clock signal by extracting a clock component from a reproduction signal of a time reference signal (preamble) and a data signal recorded when writing data. Is a general term for a device for obtaining a clock signal from a physical pattern or a magnetic pattern previously formed on a magnetic disk.

Here, the structure and problems of the conventional circuit will be described by taking an external synchronous magnetic disk device as an example. Before that, FIG. 12 shows the configuration of a magnetic disk used in this external synchronous magnetic disk device. The recording surface of the magnetic disk 1 used in this type of device is divided into a data area 1A for recording data and a servo area 1B for recording servo control signals. Of these, the servo area 1B is several hundreds per track. ~ It is arranged at equal intervals so that it appears at a frequency of about several thousand.

Any one of the three patterns is recorded in the recording pattern recorded in the servo area 1B depending on the purpose. The three patterns referred to here are the three types of recording patterns for synchronization establishment, recording patterns for phase synchronization, and other recording patterns. Among them, the recording pattern for synchronization establishment is arranged so as to appear at a frequency of about several tens to several hundreds per track, and in addition to the pattern 2A for synchronization establishment (hereinafter referred to as a unique pattern), the clock pattern 3, The access pattern 4 and the fine pattern 5 are used.

The recording patterns for phase synchronization are arranged so that one track appears at one track.
The rotation angle origin display pattern 2B (hereinafter referred to as an index pattern), a clock pattern 3, an access pattern 4, and a fine pattern 5 are used. The other recording patterns are composed of the clock pattern 3, the access pattern 4 and the fine pattern 5.

Incidentally, the unique pattern 2A is a pattern radially formed on the magnetic disk 1 and is used to roughly synchronize (initial synchronization establishment assistance) at the time of startup or at the time of synchronization loss. The index pattern 2B is a pattern radially formed on the magnetic disk 1 as an index indicating the origin of disk rotation, and is mainly used for eccentricity control of the head positioning servo system.

Further, the clock pattern 3 is a pattern radially formed on the magnetic disk 1 and is used for generating a servo clock and a data clock. The access pattern 4 is a pattern for holding a track number provided in the disk radial direction, and is used for accessing a predetermined track by a seek operation of the magnetic head. The fine pattern 5 is a tracking control pattern and is used to indicate the off-track amount of the head.

There are several possible methods for forming the servo area 1B including these plural recording patterns on the disk substrate. For example, the magnetic area may be formed by partially removing the magnetic layer by a method such as etching. You can
The residual pattern of these magnetic films becomes each recording pattern.
Incidentally, each recording pattern is assumed to be DC magnetized in the track direction by the magnetic head so that it can be reproduced by the magnetic head. The above is the configuration of the magnetic disk 1 used in the external synchronous magnetic disk device.

[0010]

In the case of the conventional external synchronous magnetic disk device, a method of detecting the unique pattern 2A and the index pattern 2B on the magnetic disk 1 by the synchronous pattern detecting circuit 6 shown in FIG. Is commonly used. Here, the synchronization pattern detection circuit 6 is composed of three circuits: a peak detector 6A, a shift register 6B, and a matching circuit 6C. The peak detector 6A is used to detect the peak of the input data S1 reproduced through the magnetic head and the reproduction amplifier in order and convert it to the binary data string S2.

Incidentally, this binary data string S2 is sequentially stored in the shift register 6B. The shift register 6B collectively reads the stored binary data sequence S2 and supplies it to the matching circuit 6C as a data vector S3. The matching circuit 6C determines whether or not the data vector S3 and the reference vector S4 corresponding to the unique pattern 2A or the index pattern 2B coincide with each other in bit units, and when the unique pattern 2A or the index pattern 2B is detected, the synchronization establishment auxiliary signal is detected. S5 or rotation angle origin instruction signal S6
Is output. The external synchronous magnetic disk device generates a clock signal based on the synchronization establishment auxiliary signal S5 and the rotation angle origin instruction signal S6.

However, the synchronous pattern detection circuit 6 having this configuration has the following problems. First, since the peak detection method is used to detect the recorded data symbol, it is difficult to make the circuit digital, and it is difficult to make the circuit compact by integration (LSI). Further, since the recording data symbol is regarded as a binary symbol and the pattern coincidence is determined, the polarity alternating property of the reproduced waveform pulse which is peculiar to the digital magnetic recording is not used, and there is a problem that erroneous detection easily occurs.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a digital signal decoding apparatus having a pattern detecting means having a higher detection accuracy than the conventional one.

[0014]

According to the present invention, in order to solve such a problem, an input signal is sampled by a clock having a frequency substantially equal to its data rate or an integral multiple, and the sampled value of each sample point is sampled. The sampling means for outputting and the sample value and the reference level are sequentially compared, the symbol detecting means for detecting the information data symbol, the series of the information data symbol and the series of the reference data symbol are collated, and the collation result is obtained. When a certain difference is equal to or less than a certain value, pattern detecting means for recognizing that a pattern matching the reference data symbol series exists in the information data symbol series and outputting a pattern detection signal is provided.

[0015]

The input signal input to the sampling means is sampled by a clock having a frequency approximately equal to the data rate or an integral multiple. The symbol detecting means successively compares the sample value at each sample point with the reference level, detects an information data symbol, and outputs it to the pattern detecting means. The pattern detection means collates this information data symbol sequence with the reference data symbol sequence, and if the difference as the collation result is less than or equal to a certain value, it matches the reference data symbol sequence in the information data symbol sequence. A pattern detection signal is output by recognizing that there is a pattern.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall Configuration FIG. 1 shows the overall configuration of an external synchronous magnetic disk device 11 as an example of a digital signal decoding device. Incidentally, in the case of this example, the magnetic head 1 of the external synchronous magnetic disk device 11 is
2 is used both in the recording mode and the reproducing mode. A switch 13 is used to switch the mode of the magnetic head 12.

Further, in this example, it is assumed that the recording pattern shown in FIG. 12 is formed on the disk surface of the magnetic disk 14 reproduced by the external synchronous magnetic disk device 11. That is, two types of patterns, that is, a unique pattern 2A and an index pattern 2B, are formed as synchronization patterns on the disk surface of the magnetic disk 14. These synchronization patterns are read even in the recording mode and used for the clock generation circuit 15 to generate the clock signal CK.

The recording data generating circuit 16 operates in synchronization with the clock signal CK supplied from the clock generating circuit 15, converts the input data S11 into recording data S12 and outputs it. The recording amplifier 17 receives the input recording data S12
Is amplified and given to the contact R of the switch 13, and this is output to the magnetic head 12. On the other hand, the reproduction amplifier 18 reproduces the reproduction signal S1 reproduced from the magnetic head 12.
3 is input through the contact point P of the switch 13 and is supplied to the data demodulation circuit 19. The data demodulation circuit 19 demodulates the reproduction signal S13 based on the clock signal CK given from the clock generation circuit 21, and outputs this as the demodulation data S14.

The reproduction signal S13 amplified by the reproduction amplifier 18 is supplied to the synchronization pattern detection circuit 20, the clock generation circuit 21 and the position control circuit 22. The sync pattern detection circuit 20 uses the reproduction signal S1.
3 is used to detect the synchronization pattern, and the detection protection signal S obtained by the detection of the index pattern 2B.
16 is provided to the position control circuit 22.
Further, the synchronization pattern detection circuit 20 detects the synchronization pattern from the reproduction signal S13 and supplies the rotation angle origin instruction signal S5 and the synchronization establishment auxiliary signal S6 to the timing generation circuit 23 as the detection protection signal S16.

The clock generation circuit 21 generates a data existence point clock signal CK based on the reproduced waveform of the clock pattern input from the reproduction amplifier 18 and the timing signal S17 supplied from the timing generation circuit 23, and this clock signal CK. Is output to the recording data generation circuit 16, the data demodulation circuit 19 and the timing generation circuit 23.

The timing generating circuit 23 outputs the clock signal C
The detection protection signal S1 from the K and sync pattern detection circuit 20.
Based on 6, the various timing signals S17 are generated and output to the switch 13 and the clock generation circuit 21. Incidentally, the position control circuit 22 generates a tracking error signal S18 based on the reproduction signal S3 and the detection protection signal S16 input from the reproduction amplifier 18, and the voice coil motor (VCM) 24 based on the tracking error signal S18.
Is controlled to position the magnetic head 12 at a predetermined position. Incidentally, the detection protection signal S16 input here is the rotation angle origin instruction signal S5.

(2) Structure of Sync Pattern Detection Circuit (2-1) Overall Structure FIG. 2 shows the internal structure of the sync pattern detection circuit 20. The synchronization pattern detection circuit 20 calculates the degree of coincidence between the multivalued data series obtained for the sampled data of the reproduction signal S13 and the interpolation data thereof and the reference data series as the distance in the multivalued vector space, and based on the distance perspective. To detect the synchronization pattern. As described above, the synchronization pattern detection circuit 20 enhances the detection accuracy by using the sampling data and the interpolation data thereof for the detection of the synchronization pattern, that is, by using the data obtained by oversampling.

First, the A / D converter 20A provided in the first stage of the sync pattern detection circuit 20 will be described. This A
The / D converter 20A is provided for sampling the reproduction signal S13. Here, the A / D converter 20A operates so as to sample the reproduction signal S13 asynchronously with the recording data existing point when the synchronization is not established (hereinafter referred to as the out-of-synchronization state).

Further, the A / D converter 20A samples the reproduction signal S13 at the recording data existing point position when the synchronization is established (hereinafter referred to as the synchronization state). Incidentally, in this embodiment, it is assumed that the sampling frequency is three times the recording data rate. Thus, the recorded data can be detected even before the synchronization state is established.

The reproduced data S18 sampled by the A / D converter 20A is branched into two signal processing sequences and given to the sampling processing block and the linear interpolation processing block. Here, the sampling processing block is a block that processes an input data string (hereinafter referred to as a 0 ° phase data string), and is configured by a 0 ° phase ternary data detector 20B1 and a ternary correlation determiner 20C1. . The linear interpolation processing block is a data string reproduced by averaging the 0 ° phase data string (hereinafter referred to as 180 ° phase data string).
Which is a block for processing a 180 ° phase ternary data detector 20B2 and a ternary correlation determiner 20C2.

The ternary data detectors 20B1 and 20B2 convert the reproduced data S18 into correlation determination vectors V ₀ and V ₁₈₀ and output them. In addition, the three-value correlation determiners 20C1 and 20C
C2 obtains the correlation between these correlation determination vectors V ₀ and V ₁₈₀ and the reference vector Vunique or Vindex (that is, the unique pattern vector Vunique or the index pattern vector Vindex) and calculates the Hamming distance for the two vectors.

The three-value correlation determiners 20C1 and 20C2 use this calculation result as the correlation degree signal 0 ° phase three-value Hamming distance S1.
Output as 9 and 180 ° phase ternary Hamming distance S20. The optimum time detection circuit 20D has a correlation degree signal of 0 ° phase ternary Hamming distance S19 and 180 ° phase ternary Hamming distance S
20 is compared to obtain the smaller one, and the synchronization pattern detection signal S21 is output at the position where the correlation degree is the smallest for the smaller correlation degree signal 0 ° phase three-valued Hamming distance S19 or 180 ° phase three-valued Hamming distance S20. It is done like this. This position is the position where the synchronization pattern exists.

The protection interpolating circuit 20E is provided to improve the detection accuracy of the synchronization pattern. The protection interpolation circuit 20E switches the operation mode according to the detection state of the sync pattern detection signal S21. That is, the protection interpolation circuit 20E prohibits the output of the detection protection signal S16 in the asynchronous mode state until the cycle is stable, and in the synchronous mode state, the output of the detection protection signal S16 is interrupted due to the loss of the synchronization pattern. It is designed not to occur. Here, the detection protection signal S16 is the rotation angle origin instruction signal S5 and the synchronization establishment auxiliary signal S6. Hereinafter, the configuration of each unit that constitutes the synchronization pattern detection circuit 20 will be described in order.

(2-2) Configuration of ternary data detector FIG. 3 shows the internal configuration of the ternary data detectors 20B1 and 20B2, and FIG. 4 shows its operating principle. First, the 0 ° phase ternary data detector 20B1 will be described. This 0 °
The phase ternary data detector 20B1 is a circuit that converts the sampled reproduction data S18 into three values (“−1”, “0”, “+1”), and is configured by the level comparator 31. ing.

This level comparator 31 reproduces the reproduction data S18.
Is divided into three levels by two thresholds + V
It is designed to compare _TH with -V _TH . 2 here
The two thresholds + V _TH and −V _TH are calculated by

[Equation 1] The reference level is divided into three spaces A, B, and C as shown in FIG.

The level comparator 31 has three spaces A, B and C.
Is associated with three values (“−1”, “0”, “+1”). Incidentally, the level comparator 31 outputs the ternary value as a 2-bit binary number "(10), (00), (01)".

Next, the internal structure of the level comparator 31 will be described. The level comparator 31 is composed of a pair of comparators 31A and 31B. Here, the comparator 31A is used for comparing the reproduced data S18 with the threshold value + V _TH, and the comparator 31B is used for comparing the reproduced data S18 with the threshold value −V _TH . Two bits of data are output from each of the comparators 31A and 31B. These comparators 31A and 31
A combination of the outputs of B becomes 2-bit binary data. The sampled data sequence of the reproduction data S18 is indicated by a black circle in FIG.

On the other hand, 180 ° phase ternary data detector 20
B2 is composed of a linear interpolator 32 and a level comparator 33. Of these, the linear interpolator 32 includes a 1-sample delay circuit 32A, an adder 32B, and a divider 32C.
The linear interpolator 32 receives the input data d at the current sampling time t.
An average value of _t and the input data d _t-1 one sampling time before is obtained by these circuits and is output to the level comparator 33 as interpolation data.

The level comparator 33 has the same structure as the level comparator 31 and is composed of a pair of comparators 33A and 33B. The comparator 33A is used to compare the interpolation data with the threshold value + V _TH, and the comparator 33B is used to compare the interpolation data with the threshold value −V _TH . Each comparator 33
Two bits of data are also output from A and 33B. The output of each of the comparators 31A and 31B is combined to form 2-bit binary data. The sampled data sequence of the reproduction data S18 is indicated by a triangle mark in FIG.

(2-3) Structure of the three-valued correlation determiner Next, the internal structure of the three-valued correlation determiners 20C1 and 20C2 will be described. The three-value correlation determiners 20C1 and 20C2
Is used to determine the correlation between the outputs of the ternary data detectors 20B1 and 20B2, that is, the ternary data strings V ₀ and V ₁₈₀ converted into 2-bit binary numbers, and the unique pattern Vunique or the index pattern Vindex. To be

In the case of this example, the unique pattern Vun
ique is a 15-bit M series (1,0,0, -1,1,0, -1,0,1, -1,
1, -1,0,0,0) and the index pattern Vindex is 1
5 bit M series (1,0, -1,0,1, -1,0,0,1,0,0,0, -1,1,-
1) Now, three-value correlation determiners 20C1 and 20C2
Is the Hamming distance, which is the ternary Hamming distance between the 15-bit reference vector V _r (unique pattern Vunique or index pattern Vindex) and the input data string V (V ₀ or V ₁₈₀ ) of the ternary correlation determiner 24. The smaller the value of, the higher the correlation.

Here, the ternary Hamming distance is obtained by taking the exclusive OR when each bit is a ternary space, that is, a binary binary vector. However, the input data string V is divided into 1-bit unit series V ₁ and V ₂ , and the ternary Hamming distance is obtained for each. Incidentally, the development into the series V ₁ and V ₂ of one bit unit is as shown in FIG.

The three-value correlation determiners 20C1 and 20C2 are
The three-valued Hamming distance (weight) for each series V ₁ and V ₂ is obtained by the integrators 36A and 36B, and the integrator 3
A ternary Hamming distance for the input data string V is obtained by adding the calculation results of 6A and 36B in the adder 37. At this time, when the value output from the adder 37 is zero, that is, when the ternary Hamming distance is zero, the ternary correlation determiners 20C1 and 20C2 have detected a sequence that completely matches the reference vector V _r. .

Incidentally, in this embodiment, since the input data is sampled at the triple frequency of the data existence point clock, the ternary correlation determiners 20C1 and 20C2 are input to the 45-stage shift registers 34A and 34B. Column V is being written. And three-value correlation determiners 20C1 and 20C2
15 bits extracted from the shift registers 34A and 34B every 3 bits are the object of the correlation determination.

(2-4) Configuration of Optimal Time Detection Circuit The optimum time detection circuit 20D has 0 ° phase 3 in the comparator 20D1.
The value Hamming distance S19 and the 180 ° phase ternary Hamming distance S20 are input, and the smaller of the two is selected. The minimum value search circuit 20D2 outputs the synchronization pattern detection signal S21 with the pattern detection position when the ternary Hamming distance is t (t is an arbitrary integer) or less and is minimum within a certain time.

Further, when the detection points are continuous, the central point is set as the detection position. Therefore, the minimum value consecutive number counter 2
The number of consecutive minimum points is detected by 0D3, and the half of the detected number is used to obtain the correct detection time S22. This correct detection time S22 is input to the deviation calculator 20D6. The deviation calculator 20D6 calculates the deviation from the predetermined detection time S23 based on the detection time S22, and corrects the time (count value) of the time generator 20D7 configured by the counter.

Incidentally, the correction time S24 output from the deviation calculator 20D6 at this time is given to the frame counter of the protection interpolation circuit 20E described in the next section, and is used for setting to a correct count value. This frame counter specifies the position of the sync pattern to be detected next.

(2-5) Structure of Protection Interpolation Circuit Finally, the structure of the protection interpolation circuit 20E will be described with reference to FIG. Further, its operating state is shown in FIG. The protection interpolation circuit 20E has two protection modes so that the detection state of the synchronization pattern can be continued for a long time. One is the backward protection mode in the out-of-sync state, and the other is the forward protection mode in the in-sync state. Before describing the operation in each mode, the internal circuit configuration will be described.

First, the frame counter 20E1 counts up the clock signal CK, and at the position where the next synchronization pattern is to be detected, the pulsed frame signal S25.
It is designed to output. Frame counter 20
As described in the previous section, E1 corrects the count value according to the correction time S24 and outputs the frame signal S25 to the counter 20E2 and the interpolation circuit 20E3 when the count value reaches a predetermined count value.

The counter 20E2 detects whether or not the sync pattern is actually detected at the timing designated by the frame signal S25. When the synchronization pattern is detected at the expected timing, the number is counted up and the protection end condition determination condition circuit 20E4 is detected.
Has been made to give to.

The protection end condition judging circuit 20E4 is a circuit for switching the above-mentioned two protection modes. Here, the backward protection mode is a mode that is executed when the synchronization state is established from the state where the synchronization is lost, and the forward protection mode is executed when the synchronization state is likely to be lost from the state where the synchronization state is established. Mode.

First, in the backward protection mode, the protection end condition determination circuit 20E4 determines whether or not the synchronization pattern detection signal S21 is first detected at the timing given by the frame signal S25 and continuously detected a predetermined number of times. The protection mode is switched from the rear protection mode to the front protection mode when the predetermined number of times has been reached and the synchronization state is entered. Incidentally, the switching of the protection mode is performed by lowering the signal level of the out-of-synchronization signal S26, so that the counter 20E2 and the interpolation circuit 20E3.
Given to. In the case of the embodiment, the protection mode is switched when the synchronization pattern detection signal S21 is detected three times in succession. Therefore, if the number of times is less than three times, it means that the synchronization is lost again, so that the protection mode is not switched.

On the other hand, in the forward protection mode, the protection end condition determination circuit 20E4 determines whether or not the synchronization pattern detection signal S21 is continuously detected a predetermined number of times in a state where it is constantly detected at the timing given by the frame signal S25. It is determined based on the count value that the protection mode is switched from the front protection mode to the front protection mode when a predetermined number of times is reached and the synchronization is lost. Incidentally, this switching of the protection mode is given to the counter 20E2 and the interpolation circuit 20E3 by raising the signal level of the out-of-synchronization signal S26. In the case of the embodiment, the protection mode is switched when the sync pattern detection signal S21 is not detected three times in succession. Therefore, if it is less than 3 times, it means that the synchronization has been made again, and therefore the protection mode is not switched.

The interpolating circuit 20E3 outputs the out-of-sync signal S2.
Detection protection signal S16 according to the protection mode given by 6
Is designed to control the output of. For example, in the case of the backward protection mode shown in FIG. 9 (that is, when the synchronization is not ensured), even if the synchronization pattern detection signal S21 (FIG. 9A) is input, the interpolation circuit 20E3 detects the detection protection signal S16. (FIG. 9 (E)) is not output. This prevents timing control and generation of the clock signal CK in an unstable state.

On the other hand, in the case of the forward protection mode shown in FIG. 10 (that is, when synchronization is achieved), the interpolation circuit 2
0E3 is a synchronization pattern detection signal S21 (FIG. 10 (A))
Is lost once or twice in succession, the frame signal S25
The interpolation signal S16A is generated based on (FIG. 10 (B)) and is output as the protection detection signal S16 (FIG. 10 (E)). As a result, as long as the synchronization state is maintained, the protection detection signal S16 can be continuously generated without omission.

(3) Sync Detection Operation The sync detection operation of the sync pattern detection circuit 20 in the above configuration will be described with reference to FIG. Incidentally, in the case of this embodiment, A which operates as a sampler before synchronization is established
It is assumed that the clock having a fixed frequency is given to the / D converter 20A and the clock generated by the clock generation circuit 21 is given after the synchronization is established.

FIG. 11 shows the operation of the synchronization pattern detection circuit 20 when initial synchronization is established. Immediately after turning on the power, the operation state of the synchronization pattern detection circuit 20 is out of synchronization. At this time, the signal level of the out-of-sync signal S26 output from the protection end condition determination circuit 20E4 is set to a high signal level.

Now, from this out-of-sync state, the magnetic disk 1
The rotation of No. 4 is started, and the reproduction signal S13 reproduced by the magnetic head 12 is input to the reproduction amplifier 18. The reproduction signal S13 amplified by the reproduction amplifier 18 is supplied to the data demodulation circuit 19 and the like. Here, the reproduction signal S13 supplied to the synchronization pattern detection circuit 20 is an A / D converter as shown in FIG. 20A and sampled and quantized. At this time, the reproduction signal S13 shown in FIG. 11B is sampled at a frequency three times the data rate.

The reproduced data S18 sampled by the A / D converter 20A is ternary data detectors 20B1 and 20B.
Is supplied to B2. The ternary data detectors 20B1 and 20B2 convert the ternary symbol into binary 2-bit data as shown in FIG. The ternary correlation determiners 20C1 and 20C2 take the correlation between the binary 2-bit data input from the preceding stage and the synchronization pattern, and the Hamming distance signal S1 for each of the sampling signal and the interpolation signal.
9 and S20 are calculated. Hamming distance signals S19 and S
20 is supplied to the optimum time detection circuit 25 and is used for detecting the synchronization pattern. The optimum time detection circuit 25 outputs a sync pattern detection signal S21 every time a sync pattern is detected. These operations are always performed.

Immediately after the power is turned on, the synchronization is not yet achieved. In such an out-of-synchronization state, when the first synchronization pattern is detected, the protection interpolation circuit 20E enters the synchronization establishing operation state, and the next synchronization pattern detection signal S21 is input at a certain fixed interval (that is, the synchronization pattern interval). Whether it is done or not is determined. Incidentally, it is the optimum time detection circuit 20D that determines the start reference time of this interval. Protection interpolation circuit 2
The 0E frame counter 20E1 subsequently outputs a frame signal S25 to check whether or not a sync pattern is detected at each sync pattern interval according to this reference time.

The protection interpolating circuit 20E receives the frame signal S
When the synchronization pattern detection signal S21 is detected several times in succession at the detection position indicated by 25, the synchronization establishment operation state transits to the synchronization state, and thereafter, the protection detection signal S16.
Is continuously output. In this state, the frame signal S2
The synchronization pattern detection signal S2 at the timing specified by 5
Even if 1 is not detected several times, the protection detection signal S16 is transmitted without interruption as long as it is not determined to be out of synchronization, and is used for timing control of the external synchronous magnetic disk device 11.

According to the above configuration, since the sync pattern detection process can be executed by the signal processing of the reproduction data S18 obtained by sampling the reproduction signal S13, the synchronization pattern detection circuit 20 and several processing circuits including the same are integrated. Circuitization can be realized. As a result, the synchronization pattern detection circuit 2
0 size reduction can be realized. Further, it is possible to reduce the size of the entire external synchronous magnetic disk device 11 including the synchronous pattern detection circuit 20.

According to the above configuration, the reproduction signal S13
Is sampled at a sampling frequency three times the data rate, and the recorded data is detected even before the synchronization state is established by using the reproduction data S18 sampled at the high sampling frequency. can do

Further, according to the above configuration, the reproduction signal S1
Since the synchronization pattern is detected using not only the sampled data string 3 but also the interpolated data string corresponding to the intermediate data of the sampled data string, a highly accurate pattern can be obtained even in a circuit with a slow operation speed. The synchronization pattern detection circuit 20 that can realize the detection can be realized.

According to the above configuration, the reproduction data S1
8 is compared with two threshold values −V _TH and + V _TH to generate multi-valued data, and a correlation determination vector V and a reference vector V _r (multi-valued reference data symbol series) composed of this multi-valued data group are generated. By executing the correlation degree of the above by calculating the distance in the ternary vector space, the probability of erroneous detection can be further reduced, and the synchronization pattern detection circuit 20 with high synchronization pattern detection accuracy can be realized. .

Further, according to the above configuration, the protection interpolation circuit 20E of the sync pattern detection circuit 20 is provided with two protection modes, and the sync pattern is detected in the backward protection mode which is executed during the period out of synchronization. Also prohibits the output of the synchronization signal (protection detection signal S16) to the peripheral circuits, and in the forward protection mode executed during the period of synchronization, even if the loss of the synchronization pattern occurs, the synchronization signal ( By interpolating the interpolated signal S16A), it is possible to realize the synchronization pattern detection circuit 20 which has higher detection reliability of the synchronization pattern than the conventional one.

(4) Other Embodiments In the above-mentioned embodiments, the case of using in the sync pattern detecting circuit in the external synchronous magnetic disk device has been described, but the present invention is not limited to this, and the self synchronous magnetic disk is used. It can also be used in the sector synchronization circuit of the device.

Further, in the above-mentioned embodiment, the case where the invention is applied to the magnetic disk device is described, but the present invention is not limited to this, and can be applied to the magneto-optical disk device and the optical disk device. Further, it can be applied to a digital signal transmitting / receiving apparatus that transmits / receives information via a transmission path regardless of a wired path or a wireless path.

Further, in the above-mentioned embodiment, the clock pattern 3 and the unique pattern 2 are formed on the magnetic disk 14.
Although the case where A or the index pattern 2B is continuously formed in the radial direction has been described, the present invention is not limited to this.
These patterns may be formed intermittently along the radius.

Further, in the above-described embodiment, the case where each pattern of the servo area 1B of the magnetic disk 14 is formed as a physical pattern by using, for example, an etching method has been described, but the present invention is not limited to this, and the data is not limited thereto. It can also be applied to magnetic recording on a flat magnetic layer as in the case of recording data in the area 1A.

Further, in the above-mentioned embodiment, the magnetic disk 14 in which the two kinds of synchronization patterns of the unique pattern 2A and the index pattern 2B are formed on the same surface has been described, but the present invention is not limited to this. The present invention can also be applied to a magnetic disk on which only one of these two types of synchronization patterns is formed.

Further, in the above embodiment, the case where the unique pattern 2A and the index pattern 2B are respectively used as the pattern for establishing the synchronization and the pattern for instructing the rotation angle origin is described, but the present invention is not limited to this. , For example, search mark pattern detection,
It can also be used for pattern detection for other purposes.

Further, in the above-mentioned embodiments, the case where the recording medium is a magnetic disk has been described, but the present invention is not limited to this, and a magnetic tape may be used. The recording medium may be an optical disk or a magneto-optical disk, and can be applied to the case of a card-shaped optical recording medium.

In the above embodiment, the reproduction signal S
The case where 13 is sampled at a sampling frequency three times the data rate has been described, but the present invention is not limited to this.
The sampling frequency may be approximately equal to the data rate. Further, the sampling frequency does not have to be three times or equal to the data rate as long as it is an integral multiple of the data rate.

Further, in the above-mentioned embodiment, the case where the reproduction signal S13 is quantized into the ternary data is described, but the present invention is not limited to this, and is widely applied to the case where it is quantized into the multivalued data of four or more values. Applicable.

Further, in the above-mentioned embodiment, the case has been described in which not only the sampling data but also the interpolation data corresponding to the intermediate value thereof is used to detect the synchronization pattern, but the present invention is not limited to this, and sampling is performed. The synchronization pattern may be detected using only the data.

[0073]

As described above, according to the present invention, the input signal is sampled by the sampling means, and the sampled value of each sampling point is successively compared with the reference level to form a sequence of detected information data symbols. Based on the digitalization of a series of processing at the time of pattern detection, such as detecting a pattern that matches the sequence of reference data symbols based on the above, a processing circuit can be integrated, and a compact and highly reliable digital signal decoding device is realized. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data reproducing system and a servo system of a digital signal decoding device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of a synchronization pattern detection circuit.

FIG. 3 is a block diagram showing an internal configuration of a ternary data detector.

FIG. 4 is a schematic diagram for explaining the principle of a conversion operation by a ternary data detector.

FIG. 5 is a block diagram showing the internal configuration of a ternary correlation determiner.

FIG. 6 is a diagram showing an example of pattern matching determination on a ternary vector space.

FIG. 7 is a block diagram showing an internal configuration of an optimum time detection circuit.

FIG. 8 is a block diagram showing an internal configuration of a protection interpolation circuit.

FIG. 9 is a timing chart showing an operation example in a rear protection mode.

FIG. 10 is a timing chart showing an operation example in a front protection mode.

FIG. 11 is a timing chart showing an operation example of the entire synchronization pattern detection circuit.

FIG. 12 is a schematic diagram showing the vicinity of a servo area formed on a magnetic disk.

FIG. 13 is a block diagram showing the configuration of a conventionally used synchronization pattern detection circuit.

[Explanation of symbols]

1, 14 ... Magnetic disk, 2A ... Synchronization establishment pattern, 2B ... Phase synchronization pattern, 3 ... Clock pattern, 4 ... Access pattern, 5 ... Fine pattern, 11 ... External synchronization type Magnetic disk device, 12 ... Magnetic head, 13 ... Switching switch, 16 ... Recording data generating circuit, 17 ... Recording amplifier, 18 ... Reproducing amplifier,
19 ... Data demodulation circuit, 20 ... Sync pattern detection circuit, 20A ... A / D converter, 20B1, 20B2 ...
3-value data detector, 20C1, 20C2 ... 3-value correlation determiner, 20D ... Optimal time detection circuit, 20E ... Protection interpolation circuit, 21 ... Clock generation circuit, 22 ... Position control circuit, 23 ... Timing generation circuit, 24 ... VCM.

Claims (12)

[Claims] 1. Sampling means for sampling the input signal by a clock having a frequency substantially equal to or a multiple of the data rate of the input signal, and outputting sampling values at each sampling point; When the difference as the comparison result is less than or equal to a certain value by comparing the information data symbol sequence and the reference data symbol sequence by sequentially comparing the reference level with each other and detecting the information data symbol, A digital signal decoding device comprising: a pattern detecting means for recognizing that a pattern matching the sequence of reference data symbols exists in the sequence of information data symbols and outputting a pattern detection signal. 2. Sampling means for sampling the input signal based on a clock having a frequency substantially equal to or an integer multiple of the data rate of the input signal, and outputting sampling values at each sampling point; Interpolation means for obtaining an interpolated value corresponding to the signal value between each sample point based on the sampled value, and the interpolated value obtained by the interpolated means and the reference level are sequentially compared to detect an information data symbol. Means and the sequence of the information data symbol and the sequence of the reference data symbol are collated, and if the difference as the collation result is less than a certain value, the sequence of the information data symbol matches the sequence of the reference data symbol. A digital signal decoding device, comprising: a pattern detection unit that recognizes that a pattern exists and outputs a pattern detection signal. 3. The digital signal decoding apparatus according to claim 1, wherein the symbol detecting means detects the multilevel information data symbol by comparing the sampled value with a plurality of reference levels. 4. The digital signal decoding apparatus according to claim 2, wherein the symbol detecting means detects the multilevel information data symbol by comparing the sampled value with a plurality of reference levels. 5. The pattern detecting means collates a series of multivalued information data symbols with a series of multivalued reference data symbols by distance calculation in a multivalued vector space. Digital signal decoding device. 6. The pattern detection means according to claim 4, wherein the series of multi-valued information data symbols and the series of multi-valued reference data symbols are collated by distance calculation in a multi-valued vector space. Digital signal decoding device. 7. The digital signal decoding device according to claim 1, wherein the sequence of reference data symbols is a synchronization pattern. 8. The digital signal decoding device according to claim 2, wherein the sequence of the reference data symbols is a synchronization pattern. 9. The pattern detection signal is input when the number of times the pattern detection signal is not input is a predetermined number or less in a synchronization mode in which the pattern detection signal is to be continuously detected at predetermined intervals in principle. 8. The digital signal decoding device according to claim 7, further comprising timing signal output means for outputting a synchronization timing signal at a timing to be performed. 10. The timing signal output means, in the asynchronous mode in which the pattern detection signal is not detected at predetermined intervals, when the pattern detection signal is input, also at the timing when the pattern detection signal is input. 10. The digital signal decoding device according to claim 9, wherein the output of the synchronization timing signal is prohibited. 11. A pattern detection signal is input when the number of times the pattern detection signal is not input is less than a predetermined number in a synchronization mode in which the pattern detection signal is to be continuously detected at predetermined intervals in principle. 9. The digital signal decoding device according to claim 8, further comprising timing signal output means for outputting a synchronization timing signal at a timing to be performed. 12. The timing signal output means, when the pattern detection signal is input in an asynchronous mode in which the pattern detection signal is not detected at predetermined intervals, also at the timing when the pattern detection signal is input. 12. The digital signal decoding device according to claim 11, wherein the output of the synchronization timing signal is prohibited.