JPH08275161A - Image converter - Google Patents

Abstract

PURPOSE: To quickly and surely detect a fault of an image conversion section having no correlation between input and output signals in the image converter having an image conversion section converting an image signal into a coded compressed signal or converting a coded compressed signal into an image signal. CONSTITUTION: A fault monitor control means 2 selects an input signal changeover means 5 to receive a test signal in place of a substantial signal at first in the test mode and selects an output signal changeover means 6 to extract separately a processing signal from a coding processing path when the test signal is received. Then a fault monitor control means receives a test signal 7a from the input signal changeover means and collates a processing signal from the output signal changeover means with a collation signal 7b to discriminate the occurrence of a fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image conversion apparatus for converting an image signal into a coded compressed signal or a coded compressed signal into an image signal. The present invention can be applied to an image encoding device and an image decoding device according to International Standard 1) or MPEG2.

[0002]

2. Description of the Related Art In the era of multimedia in which voices / data / images are handled in an integrated manner, research, development and provision of image coding devices and image decoding devices have been actively carried out.

As shown in FIG. 2, the image encoding device is an image input device 1 such as a video camera or an image recording medium reproducing device.
Under the control of the control unit 2, the A / D conversion unit 3 performs A / D conversion on the analog image signal from, and the encoding / compression unit 4 encodes and compresses the digital image signal and sends it to the line. , And outputs to a multiplexing unit or the like with encoded voice data or encoded information data.

Here, the data sequence of the digital image signal input to the encoding compressor 4 and the data sequence of the encoded compression data from the encoding compressor 4 are uncorrelated, and
The data amount for one picture is also different.

[0005]

As described above, the image coding apparatus, especially the coding compressor 4 thereof has been actively developed and provided recently, and therefore, the coding compressor incorporated in the apparatus. No. 4 is not matured, and there are many cases where the initial failure frequently occurs in the reliability curve (so-called bathtub curve). The failure of the encoding compressor 4 appears as a disorder of the reproduced image in the image decoding device. However, the disorder of the reproduced image also occurs due to a failure of other components in the image coding apparatus or a failure of the image decoding apparatus.

When the image coding device fails, it is necessary to identify (separate) the failed part. A /
Whether or not the D conversion unit 3 has failed has a correlation between the input analog image signal and the output digital image signal, so that the input and output are taken out and aligned to the same analog image signal or digital image signal. After that, it can be determined by comparing.

However, since the input and output of the encoding compressor 4 are uncorrelated and the data amount is different, the failure determination method by extracting and comparing the input and output cannot be applied, and the normality of other components is considered. In addition to estimating the failure of the encoding compressor 4, there has been no determination method in the past. for that reason,
It took a long time to find a failure of the encoding compressor 4, and it took a long time to restore the entire apparatus to a normal state by replacement.

Further, even in a normal operation state, it may be required to perform diagnosis (fault monitoring) of the encoding compressor 4. For example, application of an image coding device to the sending side of a cable broadcasting system is being considered, but in this case, early failure detection and failure location switching are performed in order to minimize the broadcast stop time due to a failure. A division is required. Therefore, diagnosis (fault monitoring) of the encoding compressor 4 is required not only during maintenance but also during operation. However, as described above, since there is no correlation between the input and output of the encoding / compressing unit 4 and the amount of data is different, and since all pixels may have black or white images, the encoding / compressing unit 4 outputs all 0s. Even if data such as 1 or all 1 is output, it cannot be determined that a failure has occurred, and an effective method for early failure detection and fault location isolation in an operating state has not been proposed so far.

Such a problem similarly occurs in the detection of a failure of the decoding / expanding device in the image decoding apparatus.

[0010]

In order to solve such a problem, the present invention converts an image signal into an encoded compressed signal,
Alternatively, an image conversion device having an image conversion unit for converting the encoded compressed signal into an image signal is characterized by including the following means.

That is, at the connection point between the test signal storage means for storing the test signal and the collation signal and the input stage of the image conversion section or the two processing sections inside thereof, the test signal is replaced with the original signal. The input signal switching means capable of inputting the test signal and the connection point between the output stage of the image conversion unit or the two processing units inside the image conversion unit separate the processing signal when the test signal is input from the encoding processing path. And the output signal switching means to be taken out in the test mode, while inputting the test signal from the input signal switching means, the processed signal from the output signal switching means at that time is collated with the collation signal, and the test signal is input from the input point. It is characterized by having a failure monitoring control means for judging a failure occurrence in one or a plurality of processing sections in the image conversion section located between the extraction points of the processed signals.

[0012]

In the image conversion apparatus of the present invention, when the failure monitoring control means enters the test mode, first, the input signal switching means is switched so that the test signal can be input instead of the original signal, and the output signal is output. Switching means,
Switching is performed so that the processed signal when the test signal is input can be separated and taken out from the encoding processing path. Thereafter, the fault monitoring control means inputs the test signal from the input signal switching means, collates the processing signal from the output signal switching means at that time with the collation signal, and extracts the processing signal from the input point of the test signal. A failure occurrence determination is performed in one or more processing units in the image conversion unit located between the points.

Thus, by properly setting the test mode, it is possible to detect the failure of the image conversion unit having no correlation between the input and output signals in an early and reliable manner.

[0014]

【Example】

(A) First Embodiment of Image Coding Device Hereinafter, a first embodiment of the image coding device according to the present invention will be described in detail with reference to the drawings. The image coding apparatus of the first embodiment most conceptually shows the features of the present invention, and the configuration thereof is as shown in FIG. In FIG. 1, the same parts as those in FIG. 2 are designated by the same reference numerals.

In FIG. 1, the image coding apparatus of the first embodiment has two switches 5 and 6 in addition to an image input apparatus 1, a control unit 2, an A / D conversion unit 3 and a coding compressor 4. And a test data storage unit 7.

In the test data storage unit 7, in the test mode, input test data (digital image signal) 7a given to the encoding compressor 4 and its input test data 7 are provided.
Reference output test data (encoded compressed data) 7b obtained when the normal encoding compressor 4 processes a is stored. The input test data 7a may be arbitrary, but a so-called color bar image digital image signal can be applied, for example.

Under the control of the control unit 2, the switch 5 inputs the above-mentioned input test data 7a to the encoding compressor 4 in the test mode, in place of the digital image signal from the A / D conversion unit 3. Is. On the other hand, the switch 6 does not output the encoded compressed data from the encoding compressor 4 to the control unit 2 in the test mode under the control of the control unit 2 instead of outputting it to the processing unit of the next stage. is there.

In the test mode, the control unit 2 of the first embodiment switches the switches 5 and 6 from the connection state of the normal mode so that the input / output terminals of the encoding compressor 4 are both connected to the control unit bus 2a. Then, in this state, the input test data 7a is input to the encoding compressor 4, and the encoding compressor 4 processes the input test data 7a and takes in the encoded compression data output. Then, the control unit 2 collates the captured encoded compressed data with the reference output test data 7b to determine whether the encoding compressor 4 is normal or abnormal, and outputs a test result signal to a test (not shown) such as a monitor. Output to a result output device or a test result using device that uses the test result.

The test mode may be set to be changed when a maintenance worker instructs it, or may be set to be automatically changed by the control unit 2 in a predetermined cycle.

As described above, according to the first embodiment, by appropriately setting the test mode, the failure of the coding compressor 4 having no correlation between the input and output data can be confirmed by the failure location. It is possible to detect early and detect it at an early stage.

(B) Second Embodiment of Image Coding Apparatus Next, a second embodiment of the image coding apparatus according to the present invention will be described in detail with reference to the drawings. The image coding apparatus according to the second embodiment is one in which the technical idea of the present invention is introduced into an image coding apparatus according to MPEG2 in which a picture is a frame. Here, FIG. 3 is a block diagram showing a main configuration of the second embodiment.

In FIG. 3, the image coding apparatus according to the second embodiment naturally includes basic constituent elements according to MPEG2. That is, the control unit 10, the A / D conversion unit 11, the subtractor 12, the DCT conversion unit (discrete cosine conversion unit) 13, the quantization unit 14, the dequantization unit 15, the inverse DCT conversion unit 16, the adder 17, and the prediction. Memory selection switch 18,
First and second prediction memories 19 and 20, averaging circuit 2
1, a prediction data selection switch 22, and an encoding control unit 23.

Therefore, the operation in the normal operation mode is the same as the conventional one except for the processing speed described later. In the normal operation mode, the switches 31 to 35, which will be described later, are switched to the same state as when they do not exist.

That is, the digital image signal of a certain frame (picture) output from the A / D converter 11 is the digital image signal (may be all 0) predicted for the frame by the subtractor 12. The difference signal (prediction error signal) that has been subtracted
After being subjected to DCT transformation by, it is quantized by the quantizing unit 14 to be converted into a quantized transform coefficient, which is output to a processing unit (for example, a variable apex encoding unit) at the next stage. Here, regarding the quantization characteristic designation information such as the quantization step required by the quantization unit 14 and the dequantization unit 15, the encoding control unit 23 under the control of the control unit 10 determines that the picture is an I picture and the picture is a P picture. It is determined and output according to whether it is a picture or a B picture.

The quantized transform coefficient output from the quantization unit 14 is also given to the dequantization unit 15, and the dequantization unit 1
After being inversely quantized by 5, the inverse DCT transform unit 16 further performs an inverse DCT transform, whereby a differential signal for local reproduction corresponding to the differential signal from the subtractor 12 is obtained. In the adder 17, the digital image signal predicted for the frame is added to the difference signal, whereby a digital image signal for local reproduction is obtained. This reproduced digital image signal depends on whether the picture is an I picture (intra-frame encoded image), a P picture (inter-frame forward predictive encoded image) or a B picture (bidirectional predictive encoded image). , Is supplied to and stored in the first or second prediction memory 19 or 20 via the switch 18 that is switched by the encoding control unit 23.

An averaging circuit for the digital image signal stored in the first prediction memory 19, the digital image signal stored in the second prediction memory 20, and the digital image signals from the first and second prediction memories 19 and 20. Either the digital image signal averaged by 21 or the digital image signal of all 0 is transmitted via the switch 22 that is switched by the encoding control unit 23 according to the type of the picture to be encoded and compressed. It is given to the subtractor 12 and the adder 17 as a predicted digital image signal.

MPE performing the above basic operations
In addition to the basic configuration according to G2, this second embodiment has a fault detection configuration.

The fault detection configuration is the test data storage unit 3.
The 0 and 5 switches 31 to 35 and the output test data memory 36 correspond, and also the control unit 10 and the switches 18 and 22 in the basic configuration.

The test data storage section 30 stores five types of test data 30a to 30e. The test data (digital image signal) 30a is input to the DCT conversion unit 13 via the switch 31 in the test mode, and may be arbitrary. For example, a so-called color bar image digital image signal. Can be applied. Each of the other four types of test data 30b to 30e is obtained by converting the test data 30a into the DCT conversion unit 1 when each unit is normal.
3 is input, the DCT transform unit 13, the quantizer 1
4, reference output test data obtained at the output side of the inverse quantization unit 15 and the inverse DCT conversion unit 16.

Under the control of the control section 10, each of the switches 31 to 35 supplies the input signal from the preceding processing section of the basic coding compression processing system to the processing section of the next stage as it is in the normal operation mode. is there.

Further, each of the switches 31 to 34, under the control of the control unit 10, in the test mode in which the switch 31 to 34 is its own, processes the test data 30a, ..., 30d provided from the control unit 10 to the next stage. It is something to give to the club. Under the control of the control unit 10, each of the switches 32 to 34 outputs the output signal (digital signal) from the processing unit at the previous stage in the test mode in which the switch 32 to 34 is self-exited, though the signal line is not shown. The output test data memory 36 is provided and stored.

The switch 35 is opened in the test mode and prohibits the output of the quantized transform coefficient in the test mode.

The predictive memory selection switch 18 described above is
In the test mode in which self is the exit, the adder 1
The output signal (digital image signal) from 7 is given to the output test data memory 36 and stored therein. The above-described prediction data selection switch 22 is connected to the all 0 terminal (ground) in the test mode so that it does not affect the normal encoding process.

The above-mentioned A / D converter 11 temporarily stores in the output buffer 11a a digital image signal obtained by A / D converting an analog image signal from an image input device (not shown), and then, under the control of the controller 10, The output buffer 11a outputs a digital image signal according to the mixing rule of I pictures, B pictures, and P pictures.

Here, in the case of the second embodiment, the number of group of pictures (hereinafter referred to as GOP) is 15, and 2 GO
It is assumed that the failure detection operation (test) is periodically performed every P, in other words, every 30 pictures (30 frames). Since GOP is a unit with processing independence,
It is preferable to execute the failure detection test at GOP breaks (not necessarily every 2 GOPs) because the test does not adversely affect the normal operation. As can be inferred from the operation description described later, even if the test is executed at a timing other than the GOP break, it does not have a bad influence, but the test at the GOP break has the least risk of the bad influence. It is possible and preferable.

As described above, since the test is executed once for every 30 pictures (30 frames), as shown in FIG. 4 (A), the A / D conversion unit 11 receives an analog image signal of 30 pictures per second. Even if input, the reading of the digital image signal from the output buffer 11a of the A / D converter 11 is performed as shown in FIG.
As shown in (B), 30 pictures are read in the first 30 periods obtained by dividing 1 second into 31 equal parts, and the reading is stopped in the 31st period to set a test period. It should be noted that the period for reading one picture is not the entire period obtained by dividing one second into 31 equal parts, but is selected shorter than that in consideration of the above-described switching period of each unit switch.

The serial numbers in FIGS. 4A and 4B represent the number of picture periods in one second, and do not represent the picture number (frame number) (FIG. 4 (A)). In), it may be understood as a picture number). That is, there is a case where the pictures to be read are determined according to the mixture of the I picture, the B picture, and the P picture and the creation order rule, and the pictures may not be read in the ascending order of the picture numbers. In any case, 1 second is divided into 31 equal parts. The 30 pictures are read in the first 30 periods, and the reading is stopped in the 31st period to set the test period.

Therefore, the subtracter 12, the DCT transform unit (discrete cosine transform unit) 13, the quantization unit 14, the inverse quantization unit 15, the inverse DCT transform unit 16, the adder 17, the prediction memory selection switch 18, and the 1st and 2nd prediction memory 19
And 20, averaging circuit 21, prediction data selection switch 2
2 and the components for the basic operation such as the encoding control unit 23, in the case of the second embodiment, processing of one picture in a period shorter than the period in which one second is divided into 31 equal to the switch switching. Is designed to do.

In the test mode, the quantizing unit 14 and the inverse quantizing unit 15 are supplied with the quantization characteristic designation information which is predetermined for the test.

FIG. 5 is a flow chart showing the control operation of the control section 10 in the test mode, and FIG.
It is explanatory drawing which shows the relationship between a test flag TF and a test content. The operation in the test mode will be described below with reference to these drawings.

The control unit 10 sets the test flag TF to the initial value 1 when the processing is started, and thereafter waits for the test timing (steps 100, 1).
01). Note that the control unit 10 executes control in the normal operation mode except at the test timing (step 102).

Here, the test flag TF is, as shown in FIG. 6, an entrance switch for inserting the test data, an exit switch for taking out data on which some processing is performed on the test data, and an encoding. It defines the type of test data to be inserted into the compression processing system and the reference test data to be collated with the data extracted from the encoding compression processing system. For example, when the test flag TF is 1, it means that the test data 30a is inserted from the switch 31,
This means that the processed data is taken out from the switch 18 and the data is collated with the test data 30e.

At the test timing, the control section 10 recognizes the value of the test flag TF at that time,
The switch state of each unit is switched according to the recognized value of the test flag TF, and then the test data determined according to the recognized value of the test flag TF is input to the encoding processing system (steps 103 to 105). As a result, the output test data memory 36 stores the data obtained by performing the predetermined processing on the input test data. The control unit 10 then outputs the output test data memory 3
The data stored in 6 is collated with the collation test data determined according to the value of the recognized test flag TF, and it is determined whether or not a failure has occurred (steps 106 and 107).

Here, when a normal determination result is obtained, the control unit 10 causes the test flag TF at the present time.
Is 1 or not. If it is 1, the process immediately returns to step 101. If it is not 1, the test flag is incremented by 1 and the process returns to step 101 (steps 108, 1
09). When the test flag TF is 5, the test flag TF is reset to 1 instead of being incremented by 1.

As shown in FIG. 6, the test flag TF is 1
In the case of, the test is performed from the DCT conversion unit 13 to the adder 17
Is a fault test in the entire processing system up to, and a test with a value other than 1 for the test flag TF is a fault test for each narrower processing portion. Therefore, the current test flag T
If F is 1 and the judgment result is normal,
This means that the entire processing system is normal, and the test flag TF is maintained at 1 for the next test timing. On the other hand, when the test flag TF at the present time is other than 1 and a determination result of normal is obtained, that part is normal, so at the next test timing, the test flag TF is set to 1 to test the other part. Increment.

When a failure judgment result is obtained in the above-described failure occurrence judgment step 107, the control unit 10
Judges whether or not the test flag TF at the present time is 1, and if it is 1, the process proceeds to step 109 to execute the test for each processing portion, and if it is not 1, the faulty part is known. The fact that a failure has occurred in the processing unit (see FIG. 6) defined by the value is output (steps 108, 10).
9).

Now, it is assumed that the inverse quantizer 15 has a failure. In this case, in the test for the entire coding processing system in which the test flag TF is 1 and the test data is input from the switch 31 and the processing data is extracted from the switch 18, it is determined to be abnormal, and the test flag TF is updated to 2. It In the test for the DCT conversion unit 13 in which the test flag TF is 2 and the test data is input from the switch 31 and the processed data is extracted from the switch 32, it is determined to be normal, and the test flag TF is updated to 3. Quantizer 1 in which test flag TF is 3 and test data is input from switch 32 and processing data is extracted from switch 33
Also in the test for 4, the test flag TF is updated to 4 as determined to be normal. On the other hand, the test flag T
Inverse quantizer 15 in which F is 4 and test data is input from switch 33 and processing data is extracted from switch 34
Is determined to be abnormal, and the inverse quantization unit 15
Since it was found that a failure occurred in, output to that effect.

Therefore, according to the second embodiment, the MPE
It is possible to quickly and accurately detect a failure point in the image encoding device according to G2. Moreover, at that time, the processing speed of each unit is made faster than before, and the test data is inserted at the break of the GOP to perform the test. Therefore, the first and second predictive memories 19 and 20 are connected to the test system. Since it is separated from the above, the failure detection test can be executed without affecting the basic encoding / compression processing.

The output of the quantized transform coefficient and the like is in the output stop period in the test period, but it is a problem because the time axis fluctuation is absorbed by the input buffer and the like in the transmission line encoder in the subsequent stage. There is no such thing.

As a modified example of the second embodiment, the following may be mentioned.

In the second embodiment, the failure judgment for the part of the encoding / compression processing system is also performed in the cycle of 1 second.
When it is determined that the entire encoding / compression processing system is abnormal, it may be possible to immediately shift to the failure determination for the portion of the encoding processing system.

In the flowchart of FIG. 5, it is described that the normal operation cannot be resumed until the process returns to step 101. However, if it takes time to perform the verification, the verification and the normal operation control are processed in parallel. It may be done.

Further, if it is a device that only needs to know whether the encoding / compression processing system as a whole is normal or abnormal, the switches 32 to 3 are used.
4 may be omitted. In this case, since the switch 18 is used as an exit switch, the number of newly added configurations for detecting a fault becomes very small.

Furthermore, the output from the A / D converter 11 may be stopped and the existing switch 22 may be used as an entrance switch for inputting test data for detecting a failure.

Further, the test may not be always executed in a predetermined cycle during operation, but the test may be executed in a predetermined cycle during operation only when instructed by a maintenance person. In this case, it is necessary to switch the processing speed in each unit.

Further, in the above description, the test data is 1
Although shown for pictures, the data amount of a processing unit (block, macroblock, GOB) smaller than one picture according to the hierarchy of image data in MPEG2
The amount of test data may be selected. in this case,
The time required for the failure detection test can be made shorter than the above.

(C) Third Embodiment of Image Coding Apparatus Next, a third embodiment of the image coding apparatus according to the present invention will be described in detail with reference to the drawings. The picture coding apparatus according to the third embodiment complies with MPEG2 in which a picture is a frame, and the technical idea of the present invention is introduced into a picture coding apparatus which employs a double redundant system as a coding structure. It is a thing.

A system for broadcasting encoded compressed data in accordance with MPEG2 has been developed and studied. In such a system, the stop of broadcasting is the biggest problem, and extremely high reliability is required. The image coding apparatus of the third embodiment is suitable for application to such a system that requires extremely high reliability.

Here, FIG. 7 is a block diagram showing the structure of the image coding apparatus according to the third embodiment.

In FIG. 7, the analog image signal from the image input device 41 is given to the encoding / compression unit 43-1 or 43-2 of the active system at that time through the system switching unit 42. Each of the encoding / compression units 43-1 and 43-2 has a configuration other than the control unit 10 and the test data storage unit 30 in the second embodiment. At that time, the encoding compression unit 43-1 or 43-2 of the operating system performs the processing of the normal operation mode similar to that of the second embodiment under the control of the control unit 10-1 or 10-2 of the own system. To do. Various information output from the encoding / compression unit 43-1 or 43-2 of the operating system at that time (macroblock type information of I, P, B pictures, quantization characteristic designation information, quantization conversion coefficient)
Is output to the processing unit at the next stage (for example, the transmission path coding unit) via the system switching unit 44.

Here, the operation control unit 10-1
Or 10-2 is a test data storage unit 30 common to both systems.
Using the test data stored in, the fault detection test is performed by the same method as described in the second embodiment. Here, when a failure has occurred and the failure location is specified, the information is output to the upper control unit 40.

At this time, the upper control unit 40 has the system switching unit 4
A system switching command is given to 2 and 44 to switch the active system, and at the same time, the control unit 10-2 or 10-1 of the system which has been the standby system until now is instructed to operate as the active system. In addition, the information specifying the failure location is notified from the display device, the audio speaker, or the like.

As a result, the maintenance personnel take measures such as replacing the parts at the failed part of the failed system, and as a result, the redundant system (2 system) can quickly return to a state in which it effectively functions.

Therefore, according to the third embodiment, basically, the same failure detection as in the second embodiment is performed.
The same effect as the second embodiment can be obtained. In addition to this, since the redundant system is adopted, the time during which the encoded compressed data (quantized transform coefficient etc.) cannot be output due to a failure can be suppressed to a short time of several seconds. In addition, when a failure occurs, the information specifying the failure location is notified, so that the maintenance staff can take prompt action.

(D) Example of Image Decoding Device Since the image coding device and the image decoding device are symmetrical,
The technical idea of the present invention can be applied to an image decoding device.

In the first embodiment of the image decoding apparatus, although not shown, the signal path of the image encoding apparatus shown in FIG. 1 is in the opposite direction, and the encoding compressor 4 and the A / D conversion unit are provided. 3, the image input device 1, the decoding expansion unit, the D / A conversion unit,
Since it is replaced with an image output device, its detailed description is omitted. Similarly, in the third embodiment of the image decoding apparatus, although not shown, the signal path of the image encoding apparatus shown in FIG.
Since the -1, 43-2 and the image input device 41 are replaced with a decoding / decompressing unit and an image output device, detailed description thereof will be omitted.

Therefore, in the following, the second part of the image coding apparatus will be described.
A second embodiment of the image decoding apparatus corresponding to the embodiment will be described in detail with reference to FIG.

In FIG. 8, the image decoding apparatus according to the second embodiment naturally includes basic constituent elements according to MPEG2. That is, the control unit 50 and the inverse quantization unit 5
1, inverse DCT conversion section 52, adder 53, output data selection switch 54, D / A conversion section 55, prediction memory selection switch 56, first and second prediction memories 57 and 58, averaging circuit 59, and prediction A data selection switch 60 is provided.

Therefore, the operation in the normal operation mode is the same as the conventional one except for the processing speed described later. In the normal operation mode, the switches 71 to 74, which will be described later, are switched to the same state as they do not exist.

The quantized transform coefficient and the quantized characteristic designation information from the processing unit (transmission path decoding unit) in the preceding stage are dequantized by the inverse quantization unit 51
And the inverse quantization unit 51 inversely quantizes the quantized transform coefficient, and then the inverse DCT transform unit 52 performs an inverse DCT transform.
A reproduction differential signal corresponding to the differential signal from (see FIG. 2) is obtained. In the adder 53, the digital image signal predicted for the picture is added to the reproduced difference signal, whereby the reproduced digital image signal is obtained. If the reproduced digital image signal is a B picture, I from the preceding processing unit (transmission path decoding unit),
It is immediately given to the D / A converter 55 via the switch 54 which is controlled to be switched according to the macroblock type information of P and B pictures. On the other hand, if the reproduced digital image signal from the adder 53 is an I or P picture, switching control is performed according to the macroblock type information of the I, P, and B pictures from the preceding processing unit (transmission path decoding unit). Via the switch 56, the first or second prediction memory 57 or 58
Given to and stored.

The I or P picture digital image signal stored in the first prediction memory 57 or the I or P picture digital image signal stored in the second prediction memory 58 is read at an appropriate timing. And switch 54
Is immediately given to the D / A conversion unit 55 via.

The I or P picture digital image signal stored in the first prediction memory 57, the I or P picture digital image signal stored in the second prediction memory 58, and the first and second predictions Either the digital image signal obtained by averaging the digital image signals from the memories 57 and 58 by the averaging circuit 59 or the all-zero digital image signal is
It is given to the adder 53 as a predictive digital image signal via the switch 60 which is switch-controlled according to the macroblock type information of the I, P, and B pictures from the processing unit (transmission path decoding unit) in the previous stage.

The D / A converter 55 converts the input reproduced digital image signal into an analog image signal and outputs it to an image output device such as a monitor or an image recording device.

MPE for performing the above basic operations
In addition to the basic configuration as the image decoding device according to G2, the second embodiment has a fault detection configuration.

The fault detection configuration is the test data storage unit 7
The 0, 3 switches 71 to 73 and the output test data memory 74 correspond, and also the control unit 50 and the switches 54, 56 and 60 in the basic configuration.

The test data storage unit 70 stores three types of test data 70a to 70e. The test data (encoded compressed data) 70a is input to the inverse quantization unit 51 via the switch 71 in the test mode, and may be arbitrary, for example, so-called color bar image code. Compressed data can be applied. Each of the other test data 70b and 70c is a reference value obtained at the output side of the dequantization unit 51 and the adder 53 when the test data 70a is input to the dequantization unit 51 when each unit is normal. Output test data.

Under the control of the control section 50, the switches 71 to 73 respectively apply the input signal from the basic decoding processing system to the processing section of the next stage as they are in the normal operation mode.

The switches 71 and 72 are respectively
Under the control of the control unit 10, in the test mode in which self is the entrance, the test data 70a and 70b given from the control unit 10 are given to the processing unit of the next stage. The switch 72, under the control of the control unit 50, supplies the output signal (digital signal) from the inverse quantization unit 51 to the output test data memory 74 and stores it in the test mode in which the switch 72 is self. . The switch 73 is opened in the test mode, and the first and second prediction memories 5 in the test mode are opened.
Incorrect writing to 7 and 58 is prohibited.

The output data selection switch 54 described above is
In the test mode where self exits, the adder 5
The output signal (digital image signal) from 3 is given to the output test data memory 74 and stored therein. The predictive data selection switch 60 described above is connected to the all 0 terminal (ground) in the test mode so that it does not affect the normal decoding process.

Here, also in the image decoding apparatus of the second embodiment, the number of GOPs is set to 15, and every 2 GOPs, in other words, 30 pictures (30 frames) which are GOP breaks.
The failure detection operation (test) shall be carried out periodically every time. Since the test is executed once for every 30 pictures (30 frames), the processing unit (transmission path decoding unit) in the stage preceding the portion shown in FIG. The output is performed in the first 30 periods divided into 31 equal parts, and the output of the quantized transform coefficient is stopped in the 31st period to be the test period. Under the control of the control unit 50, in the 31st period, the test quantization characteristic designation information is given to the inverse quantization unit 51, and the switch 5
4 and 60 are appropriately switched according to the test part I,
The macroblock type information of P and B pictures is output.

The above-mentioned inverse quantizer 51, inverse DCT converter 52, adder 53, output data selection switch 54, D /
The components for the basic decoding operation, such as the A conversion unit 55, the prediction memory selection switch 56, the first and second prediction memories 57 and 58, the averaging circuit 59, and the prediction data selection switch 60, are also included in the second embodiment. In the case of the example, in a period that is shorter than the period obtained by dividing 1 second into 31 equal to the switch switching period, 1
It is designed to process pictures.

Further, the D / A converter 55 outputs the analog image signal corresponding to the digital image signal arriving in 30 periods out of 31 periods obtained by dividing 1 second into 31 equal parts in the entire period of 1 second. The time axis fluctuation processing is also executed.

In the image decoding apparatus of the second embodiment having the above-mentioned configuration, although not shown, the fault detection test is executed as follows.

The control unit 50 uses the test data 70
a is input from the switch 71, and the switch 54
The data stored in the output test data memory 74 is taken out via the, and collated with the test data 70c to determine the failure occurrence. If it is normal, the same test operation is performed one second after that, and thereafter, when a normal determination result is obtained, such a monitoring operation is repeated.

When a result of abnormality is obtained in such fault monitoring, the control section 50 inputs the test data 70a from the switch 71 one second later.
At that time, the data stored in the output test data memory 74 is taken out via the switch 72 to obtain the test data 70.
The occurrence of a fault is determined by collating with b. Here, when the result of abnormality is obtained, the fact that the inverse quantization unit 51 has failed is notified.

On the other hand, if a normal result is obtained at this time, the control section 50 causes the test data 70b to be input from the switch 72 one second later, and at that time, the output test data memory 74 is output via the switch 54. The data stored in is retrieved and collated with the test data 70c,
Determine the failure occurrence. Here, when the result of abnormality is obtained, the fact that the inverse DCT conversion unit 52 or the adder 53 has failed is notified. At this time, if a normal result is obtained, the normal monitoring state is restored.

Therefore, according to the second embodiment, the MPE
It is possible to quickly and accurately detect a faulty part in the image decoding apparatus according to G2. Moreover, at that time, the processing speed of each unit is made faster than before, and the test data is inserted at the break of the GOP to perform the test. Therefore, the first and second prediction memories 57 and 58 are connected to the test system. Since it is separated from the above, the failure detection test can be executed without affecting the basic decoding / decompression processing.

As a modified example of the second embodiment of the image decoding apparatus, there can be mentioned one corresponding to the modified embodiment of the second embodiment of the image coding apparatus described above.
The description is omitted.

[0089]

As described above, according to the present invention, in an image conversion device having an image conversion unit for converting an image signal into a coded compressed signal or converting a coded compressed signal into an image signal, there is a problem. When the monitoring control means enters the test mode, first, the input signal switching means is switched so that the test signal can be input instead of the original signal, and the output signal switching means is operated when the test signal is input. The processing signal is switched so that it can be taken out separately from the encoding processing path, and then the fault monitoring control means
Since the test signal is inputted from the input signal switching means and the processed signal from the output signal switching means at that time is collated with the collation signal to judge the occurrence of a failure, there is no correlation between the input and output signals. It becomes possible to surely detect a failure of a part at an early stage.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an image encoding device.

FIG. 2 is a block diagram showing a conventional image encoding device.

FIG. 3 is a block diagram showing a second embodiment of the image encoding device.

FIG. 4 is an explanatory diagram of creation of a test period during execution of encoding in the second embodiment of the image encoding device.

FIG. 5 is a flowchart showing a test operation of the second embodiment of the image encoding device.

FIG. 6 is a functional explanatory diagram of a test flag in the second embodiment of the image encoding device.

FIG. 7 is a block diagram showing a third embodiment of the image encoding device.

FIG. 8 is a block diagram showing an embodiment of an image decoding device.

[Explanation of symbols]

1 ... Image input device, 2 ... Control part, 3 ... A / D conversion part, 4 ... Encoding compressor, 5, 6 ... Switch, 7 ... Test data storage part.

Claims (5)

[Claims] 1. An image signal is converted into an encoded compressed signal,
Alternatively, in an image conversion device having an image conversion unit for converting a coded compressed signal into an image signal, a test signal storage means for storing a test signal and a collation signal, and an input stage of the image conversion unit or the inside thereof. An input signal switching means capable of inputting the test signal in place of the original signal to the connection point of the two processing sections, and a connection point of the output stage of the image conversion section or two processing sections inside thereof. Output signal switching means for separating the processed signal when the test signal is input from the encoding processing path and extracting the processed signal from the encoding processing path, and inputting the test signal from the input signal switching means in the test mode, and The processed signal from the output signal switching means is collated with the collation signal, and one or a plurality of portions in the image conversion unit located between the input point of the test signal and the extraction point of the processed signal. An image conversion apparatus comprising: a failure monitoring control unit that determines a failure occurrence in a processing unit. 2. A plurality of pairs of test signals and verification signals stored in the test signal storage means are provided, and
A plurality of the input signal switching means and the output signal switching means are provided, and the fault monitoring control means performs the fault occurrence determination by changing the input signal switching means for inputting the test signal and the output signal switching means for taking out the processed signal. The image conversion apparatus according to claim 1, wherein the specification of the processing unit in which the failure has occurred is limited to a narrow range. 3. An image conversion apparatus comprising a plurality of redundant systems as the image conversion unit, wherein the judgment result of the fault monitoring control means is used for switching the redundant system. 2. The image conversion device described in 2. 4. A test period forming means for compressing a time axis of an input signal to the image converting unit to cyclically form a test period, is provided at a preceding stage of the image converting unit, and performs an encoding compression operation or a decoding operation. The image conversion apparatus according to claim 1, wherein the failure detection test is periodically executed during execution of the decompression operation. 5. An image converter according to MPEG, comprising:
The image conversion apparatus according to claim 4, wherein the test period is selected as a timing of a break of a group of pictures.