JPH08274824A - Fsk demodulation circuit - Google Patents

Abstract

PURPOSE: To receive data signals at much higher speed without depending on the accuracy of a BPF by passing two kinds of data signals, which are passed through the BPF, through a phase filter circuit and a differentiation circuit and turning on/off an analog switch corresponding to the differentiated signals. CONSTITUTION: A BPF 1 passes two kinds of data signals fL and fH at low and high frequencies. A phase filter circuit 2 is connected to the output side of the BPF 1 and respectively delays the phases of two kinds of data signals at 90 deg. before and behind the intermediate frequency of two kinds of data signals. An analog switch 4 is turned on/off corresponding to a signal fD differentiated by a differentiation circuit 3 connected to the output side of the phase filter circuit 2. Only when the analog switch 4 is turned on, a capacitor C2 is charged/ discharged by a fixed time constant. A comparator circuit 5 compares voltages at both the terminals of the capacitor C2 with a threshold voltage V1 decided in advance and outputs '1' or '0' logic data FR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK demodulation circuit,
In particular, it relates to an FSK demodulation circuit capable of setting an arbitrary band as an FSK demodulation band and capable of highly reliable data communication when transmitting and receiving voice and data through a wide band dedicated line such as an intercom device.

[0002]

2. Description of the Related Art Conventionally, an FSK demodulation circuit shown in FIG. 4 has been proposed. FSK demodulator is a low-frequency side BPF61 shown in FIG. 4, the high frequency side BPF 62, the diode D _71, resistor R ₇₁ and capacitor C ₇₁ lower frequency envelope detection circuit 71 is provided with a diode D _72, resistor R ₇₂ and capacitor C
Consists of a high-frequency side envelope detection circuit 72 and a comparator 73 provided with a _72, the low frequency signal f ₆₁ and the high-frequency signal f
_The input terminal T ₃ to which ₆₂ is input is connected to the input sides of the low frequency side BPF 61 and the high frequency side BPF ₆₂ , respectively.

The output side of the low frequency side BPF ₆₁ is a pin P _61.
Is connected to the anode of a diode D ₇₁ provided in the low-frequency side envelope detection circuit 71, and the cathode is a resistor R _71.
Is connected to one end of. The other end of the resistor R ₇₁ is connected to the other end of the capacitor C ₇₁ whose one end is connected to the reference potential point, and the connection point of the resistor R ₇₁ and the capacitor C ₇₁ is (−) of the comparator 73 via the pin P _71. ) Connected to the input side.

The output side of the high frequency side BPF ₆₂ has a pin P ₆₂
Is connected to the anode of a diode D ₇₂ provided in the high frequency side envelope detection circuit 72 via a resistor, and the cathode is a resistor R _72.
Is connected to one end of. The other end of the resistor R ₇₂ is connected to the other end of the capacitor C ₇₂ whose one end is connected to the reference potential point, and the connection point of the resistor R ₇₂ and the capacitor C ₇₂ is (+) of the comparator 73 via the pin P _72. ) Connected to the input side.

The output side of the comparator 73 is connected to the output terminal T ₄ for outputting the FSK demodulated signal f ₆₃ .
In such an FSK demodulation circuit, when the low frequency signal f ₆₁ and the high frequency signal f ₆₂ are sequentially input to the input terminal T ₃ shown in FIG. 4, the waveform shown in FIG. 5A is generated at the input terminal T ₃ . .

When the low frequency signal f ₆₁ passes through the low frequency side BPF ₆₁ , the waveform shown in FIG. 5B is output to P ₆₁ .
This waveform is half-wave rectified by the diode D ₇₁ provided in the low-frequency side envelope detection circuit 71, and the charging current flows to the capacitor C ₇₁ via the resistor R ₇₁ , resulting in the waveform shown in FIG. 5 (C). . When the (−) input side of the comparator circuit 73 becomes H level, the output side of the comparator circuit 73 becomes L level and 0 is output to the output terminal T ₄ as shown in (F) of FIG.

When the high frequency signal f ₆₂ passes through the high frequency side BPF ₆₂ , the waveform shown in FIG. 5 (D) is output to P ₆₂ .
This waveform is half-wave rectified by the diode D ₇₂ provided in the high-frequency side envelope detection circuit 72, and the charging current flows to the capacitor C ₇₂ via the resistor R ₇₂ , resulting in the waveform shown in FIG. 5 (D). When the (+) input side of the comparator circuit 73 becomes H level, the output side of the comparator circuit 73 becomes H level and 1 is output to the output terminal T ₄ as shown in (F) of FIG.

As shown in FIG. 6, the center frequency of the low frequency side BPF 61 and the low frequency signal f passing through the low frequency side BPF 61.
_{It is} preferable that the frequency of ₆₁ and the center frequency of the high frequency side BPF _{62 and} the frequency of the high frequency signal f ₆₂ that passes through the high frequency side BPF ₆₂ exactly match each other, and that the low frequency side BPF ₆₁ and the high frequency side BPF ₆₂ have a narrow pass band.

[0009]

Since the conventional FSK demodulation circuit is configured as described above, the center frequencies of the low frequency side BPF ₆₁ and the high frequency side BPF ₆₂ are equal to the frequencies of the low frequency signal f ₆₁ and the high frequency signal f _62. If not done, there is a problem that the levels of the low-frequency signal f ₆₁ and the high-frequency signal f ₆₂ that have passed are lowered and the noise margin is lost.

Another problem is that other noise signals are likely to pass unless the pass band width is narrowed. Further, the envelope detection is a principle of charging / discharging a capacitor with a current that has been half-wave rectified, so that the time constant becomes long and it is difficult to process a high-speed signal.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and when voice and data are transmitted / received by a wide band leased line such as an intercom device, an arbitrary band is F
The accuracy of a bandpass filter can be set by using a phase filter circuit that can be set as a band for SK demodulation and that delays the phases of two types of data signals by 90 degrees before and after the intermediate frequency of two types of frequencies, low frequency and high frequency, respectively. It is an object of the present invention to provide an FSK demodulation circuit that can receive a higher speed data signal without depending on.

[0012]

In order to achieve such an object, an FSK demodulation circuit according to the present invention is a BPF that passes data signals of two kinds of frequencies, a low frequency and a high frequency.
And a phase filter circuit connected to the output side of the BPF for delaying the phases of the two types of data signals by 90 degrees before and after the intermediate frequency of the two types of data signals, respectively, and a differential connected to the output side of the phase filter circuit. The circuit, the analog switch that turns on and off by the differential signal differentiated by the differentiating circuit, the capacitor that charges and discharges with a constant time constant only when the analog switch is on, and the voltage across the capacitor are predetermined. The threshold voltage is compared to 1 or 0
And a comparator circuit that outputs the logical data of.

[0013]

The BPF allows data signals of two kinds of frequencies, low frequency and high frequency, to pass through. The phases of the two kinds of data signals are delayed by 90 degrees by the phase filter circuit before and after the intermediate frequency of the two kinds of passed data signals. The signal delayed by 90 degrees is differentiated by the differentiating circuit connected to the output side of the phase filter circuit, and the analog switch is turned on and off by the differentiated signal.

Only when the analog switch is on, the capacitor is charged and discharged with a constant time constant, the voltage across the capacitor is compared with a predetermined threshold voltage, and logical data of 1 or 0 is output from the comparator circuit. To do.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the FSK demodulation circuit of the present invention will be described in detail below with reference to the drawings. As shown in FIG. 1, the FSK demodulation circuit according to the present invention includes a BPF 1 that passes data signals f _L and f _H of two types of frequencies, a low frequency and a high frequency,
It is connected to the output side of the PF and is connected to the phase filter circuit 2 that delays the phases of the two types of data signals by 90 degrees before and after the intermediate frequency f _m of the two types of data signals, and to the output side of the phase filter circuit. Differentiating circuit 3, an analog switch 4 which is turned on and off by a differential signal f _D differentiated by the differentiating circuit, a capacitor C ₂ which is charged and discharged with a constant time constant only when the analog switch is on, and a capacitor Of the voltage between the two ends and a predetermined threshold voltage V ₁
And a comparator circuit 5 that outputs 1 or 0 logic data F _R.

As shown in FIG. 1, the input terminal T ₁ to which the data signals f _L and f _H are input is an intermediate frequency f _m via the BPF _1.
Connected to the input side of the phase filter circuit 2 for delaying the phases of two types of data signals before and after the phase filter circuit 2
The output side of is connected to the other end of the resistor R ₁ whose one end is connected to the reference potential point via the capacitor C ₁ provided in the differentiating circuit 3.

The other end of the resistor R ₁ is connected to the anode of the diode D ₁ whose one end is connected to the reference potential point, and the cathode is connected to the other end of the resistor R ₁ . The other end of the resistor R ₁ is connected to the control side of the normally open analog switch 4 via a pin P ₁ that outputs a differential signal f _D. The input side of the analog switch 4 is connected to the output side of the BPF 1,
The output side is connected to the (+) input side of the comparator 5 via the resistor R ₂ .

The (+) input side of the comparator 5 is connected to the other end of the capacitor C ₂ whose one end is connected to the reference potential point, and the (-) input side of the comparator 5 is connected to the reference potential point. The threshold voltage V ₁ is connected. The output side of the comparator 5 is connected to the output terminal T ₂ which outputs the logic data F _R.

Next, characteristics of the BPF 1 and the phase filter circuit 2 used in the FSK demodulation circuit according to the present invention will be described with reference to FIG. As shown in FIG. 2A, the BPF 1 has a characteristic of passing the data signal f _L on the low frequency side and the data signal f _H on the high frequency side.
Noise frequencies other than _L and the data signal f _H on the high frequency side are reliably removed.

As shown in FIG. 2B, the phase filter circuit 2 inverts the phase at the intermediate frequency f _m and changes the phases of the low frequency side data signal f _L and the high frequency side data signal f _H to the intermediate frequency f _m. It has a characteristic that it is delayed by 90 degrees before and after each. That is, the phases of the data signal f _L on the low frequency side and the data signal f _H on the high frequency side are 180 degrees apart from each other about the intermediate frequency f _m , and when passing through the phase filter circuit 2, the data signal on the low frequency side is The phase of f _L has a function of inverting the phase with respect to the data signal f _H on the high frequency side.

In such an FSK demodulation circuit, the input terminal T ₁
When the low frequency side data signal f _L shown in (3) of FIG. 3 is input, the phase filter circuit 2 delays the phase of the low frequency side data signal f _L by 90 degrees. This delayed low frequency side data signal f _L is differentiated by the differentiating circuit 3,
The differentiated signal f _D shown in (B) is sent to the analog switch 4 via the pin P ₁ at the lowest level shown in the low frequency side data signal f _L.

While the analog switch 4 is turned on, the low frequency side data signal f _L sampled and held by the differential signal f _D becomes a potential across the capacitor C ₂ via the resistor R ₂ and the data signal f _L shown in FIG. The waveform is as shown in (C). When this waveform becomes equal to or lower than a predetermined threshold voltage V ₁
As shown in (D), the logic data F _R of the output terminal T ₂ to which the output side of the comparator circuit 5 is connected becomes 0 level.

When the high frequency side data signal f _H shown in FIG. 3A is input to the input terminal T ₁ , the phase filter circuit 2 delays the phase of the high frequency side data signal f _H by 270 degrees. The delayed high frequency side data signal f _H is differentiated by the differentiating circuit 3, and the differential signal f shown in (B) of FIG.
It is sent to the analog switch 4 via the pin P ₁ at the time when _D is at the highest level shown in the high frequency side data signal f _H.

The high-frequency data signal f _H is differentiated at the time of the highest level shown in this waveform, and the differential signal f _D is sent to the analog switch 4 via the pin P ₁ . While the analog switch 4 is turned on, the high-frequency data signal f _H sampled and held by the differential signal f _D becomes the potential across the capacitor C ₂ via the resistor R ₂ , and the high-frequency data signal f _H is generated as shown in FIG.
The waveform is as shown in (C). When this waveform becomes equal to or higher than a predetermined threshold voltage V ₁ , the logic data F _R of the output terminal T ₂ to which the output side of the comparator circuit 5 is connected becomes 1 level as shown in FIG. .

As shown in FIG. 3E, when the high frequency data signal f _H and the low frequency data signal f _L are alternately input to the input terminal T ₁ , the logical data F _R becomes the logical data F _R. As shown in (1), it sequentially changes to 1 level, 0 level, 1 level, and 0 level. In the above embodiment, the circuit using the capacitor, the resistor and the diode in the differentiating circuit has been described, but the same applies to the case where the different circuit is used. Further, although the sample hold and the comparison circuit use the resistor, the capacitor, and the comparator, the same is true even if they are configured by other circuits.

In addition to FSK demodulation, if a specific frequency is detected or the final stage comparator is replaced with an amplifier circuit, F
It can also be applied to an M demodulation circuit.

[0027]

As is apparent from the above description, according to the FSK demodulation circuit of the present invention, a BPF that passes data signals of two types of frequencies, a low frequency and a high frequency, and an output side of the BPF are connected, By a phase filter circuit that delays the phases of two types of data signals by 90 degrees at the intermediate frequency of the two types of data signals, a differentiation circuit connected to the output side of the phase filter circuit, and a differentiation signal differentiated by the differentiation circuit. A logic data of 1 or 0 by comparing the analog switch that turns on and off, the capacitor that charges and discharges with a constant time constant only when the analog switch is on, and the voltage across the capacitor and a predetermined threshold voltage. Since it is equipped with a comparator circuit that outputs the FSK can be set as the demodulation band, can receive high-speed data signal by without depending on the accuracy of the bandpass filter.

[Brief description of drawings]

 .

FIG. 1 is a block diagram showing an embodiment of an FSK demodulation circuit according to the present invention.

2A and 2B are characteristic diagrams of a BPF and a phase filter used in the FSK demodulation circuit according to the present invention.

3 (A), (B), (C), (D), (E),
(F) is an operation waveform showing an operation in one embodiment of the FSK demodulation circuit according to the present invention.

FIG. 4 is a block diagram of a conventional FSK demodulation circuit.

5 (A), (B), (C), (D), (E),
(F) is an operation waveform showing the operation of the conventional FSK demodulation circuit.

FIG. 6 is a characteristic diagram of low-frequency side and high-frequency side BPFs used in a conventional FSK demodulation circuit.

[Explanation of symbols]

1 --- BPF 2--phase filter circuit 3--differential circuit 4--analog switch 5--comparator circuit f _L , f _H・ ・ ・ ・ ・ ・ Data signal f _m・ ・ ・ ・ ・ ・ Intermediate frequency f _D・ ・ Differential signal C ₂・ ・ Capacitor V ₁・ ・ Threshold voltage F _R・... Logical data

Claims (1)

[Claims] 1. A BPF (1) that passes data signals (f _L , f _H ) of two types of frequencies, low frequency and high frequency, and an output side of the BPF, which is connected to an output side of the two types of the data signals of the two types. an intermediate frequency (f _m) phase filter circuit for delaying each of 90 degrees the phase of the two types of data signals before and after (2), connected to the differential circuit to an output side of the phase filter circuit and (3), the Analog switch (4) that turns on and off with the differential signal (f _D ) differentiated by the differentiation circuit
And a capacitor (C ₂ ) that charges and discharges with a constant time constant only when the analog switch is on, and a voltage across the capacitor (C ₂ ) and a predetermined threshold voltage (V ₁ ) are compared to determine 1 or An FSK demodulation circuit, comprising: a comparator circuit (5) for outputting 0 logic data (F _R ).