JPH08274284A - Multi-power supply interface lsi - Google Patents

Abstract

PURPOSE: To enable a multi-power supply interface LSI to meet requirements prescribed for usability and cost by a method wherein the N-wells of I/O cells are separated from each other for each slot, and the N-wells of the adjacent I/O cells are electrically isolated from each other. CONSTITUTION: The N-well 3 of an I/O cell is equipped with a power supply line 3a which supplies a power supply voltage VDD1, a power supply line 3b which feeds a power supply voltage VDD2, and P-channel transistors 3c. The source and the substrate of each of the P-channel transistors 3c are connected to the power supply line 3a or 3b. The N-wells 3 of the I/O cells are separated from each other for each slot P, and the N-wells 3 of the adjacent I/O cells are electrically isolated from each other. By this setup, a multi-power supply interface LSI can be improved in usability without increasing I/O cells in size and lessened enough in cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-power supply interface LSI used for ASIC and the like.

[0002]

2. Description of the Related Art Conventionally, there are few LSIs capable of interfacing a plurality of power sources, and even if such an LSI exists, the specifications thereof are limited, or the chip size becomes large and the cost becomes high. As a result, it was not convenient for the user. Examples of this type of LSI include those shown in FIGS. 4 and 5 (first conventional example) and those shown in FIGS. 6 and 7 (second conventional example).

FIG. 4 is a diagram showing the arrangement of I / O cells in an LSI that interfaces two power supplies. Further, FIG. 5 is a diagram showing an internal configuration example of the I / O cell of FIG.

As shown in FIG. 4, an LSI of the first conventional example has I / O cells arranged in the periphery of a chip by a master slice method. In the figure, 101 is a pad and 102 is an N-channel transistor. Creation area (P-Well), 1
03 is an A power source P-channel transistor creation area (N-W
and 104 are B power P channel transistor formation regions (N-Well). In the figure, P is I
1 slot of an / O cell is shown.

In the first conventional LSI, as shown in FIG. 5, in the N-channel transistor formation region 102,
An N-channel transistor 102b connected to the VSS power supply line 102a is formed, and a P-channel transistor 104b connected to the B power supply line 104a is formed in the B-power supply P-channel formation region 104.

In the first conventional example as described above, even when two kinds of power sources can be interfaced, the interface I / O cells (input and output cells) are arranged in advance at the time of creating the DW. Is set, and the user designing the PW can only design within the limit. This allows the ratio of the number of I / O cells that interface two different power supplies to match the number of two types of I / O cells prepared in the DW even if the total pin count is sufficient for the chip size. If not, there is no choice but to increase the chip size, and there is a problem that not only the pin assignment (assignment of input / output pins) is limited but also the cost increases.

Further, in another conventional example, there is an LSI in which a transistor element capable of handling a different power source is previously mounted in an I / O slot to eliminate the restriction on the arrangement of I / O cells (FIGS. 6 and 7). Second conventional example shown in FIG. 2) When an I / O cell that can handle one power supply is configured, the area of the transistor element that can handle the other power supply becomes an empty area, which also increases the cost due to the increase in chip size. there were. FIG. 6 is a diagram showing the arrangement of I / O cells in an LSI that interfaces two power supplies. Also, FIG.
FIG. 7 is a diagram showing an example of the internal configuration of the I / O cell of FIG. 6, and common components are assigned the same reference numerals.

Further, although there is a user's request to temporarily change the power source of only a specific I / O cell, in the case of the LSI in the above-mentioned first and second conventional examples, adjacent I / O cells are adjacent to each other. Are connected by wells, so to meet this demand, DW redesigned from user D
It was necessary to create W.

[0009]

As described above, in the first conventional example, (1) there are restrictions on the arrangement of I / O cells.
(2) The size of the I / O cell becomes large, (3) Even if you want to temporarily change the power supply for a specific I / O cell, D
There is a problem that it is necessary to create a user-specific DW redesigned from W, (4) it is not possible to interface with three or more types of power supplies, and so it is satisfactory in terms of usability and cost. Was not.

The present invention has been made to solve the above-mentioned conventional problems, and its purpose is to provide a multi-power supply interface L which is satisfactory in terms of usability and cost.
The purpose is to provide SI. The other purpose is to change the PW and not affect the pin assignment. 2
It is an object of the present invention to provide a multi-power supply interface LSI capable of interfacing three or more kinds of power supplies as well as types.

[0011]

In order to achieve the above object, a feature of the present invention is that a plurality of I / O cells are arranged in the periphery of a chip and a master slice type multi-power source for interfacing a plurality of types of power sources. Interface LS
In I, the N-well of the I / O cell is independent for each slot, and the N-wells of adjacent I / O cells are electrically separated.

Further, in the above-mentioned invention, each I / O
It is desirable to arrange a power supply line for supplying power to the cell in a ring shape on the I / O cell.

Further, in the above-mentioned invention, it is desirable that the power supply line for supplying the high power supply is composed of a plurality of electrically separated lines.

[0014]

According to the present invention having the above-described structure, since the N-wells of a plurality of I / O cells arranged around the chip are electrically separated for each I / O cell, other I / O cells are It enables the interface of the power supply different from the O cell.

Further, in the present invention, by arranging a power supply line for supplying power to each I / O cell in a ring shape on the I / O cell, power is supplied to the I / O cell easily and accurately. can do.

Further, in the present invention, the power supply line for supplying a high power supply is composed of a plurality of electrically isolated lines, so that only the PW is changed and the pin assignment is not affected. Power supply interface can be enabled.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the arrangement of I / O cells in a multi-power supply interface LSI according to the first embodiment of the present invention.

This LSI comprises a pad 1 which constitutes a plurality of I / O cells from the outside to the inside of the peripheral portion of the chip,
N-channel transistor creation area (P-Well) 2
And multi-power supply P-channel transistor creation area
Well) 3 are sequentially arranged. Note that P indicates one slot of the I / O cell described above.

FIG. 2 is a diagram showing an internal configuration example of the I / O cell in FIG.

P-channel transistor formation region (N-W
3), a plurality of P-channel transistors 3c are arranged together with a power supply line 3a supplying a power supply voltage VDD1 and a power supply line 3b supplying a power supply potential VDD2, and each P-channel transistor 3c is arranged in the power supply line 3a or 3b. Source and substrate are connected. The N-well 3 of the I / O cell is independent for each slot (P in the figure) and the N-well of each adjacent I / O cell is N-well.
The Well region 3 is electrically isolated.

In the N-channel transistor forming region (P-Well) 2, a power supply line 2a for supplying the ground power supply VSS and a plurality of N-channel transistors 2b are arranged, and each N-channel transistor is provided in the power supply line 2a. The source and substrate of 2b are connected. Here, the power supply lines 3a, 3b, 2a for supplying power to each I / O cell are arranged in a ring shape on the I / O cell.

The drain of the P-channel transistor 3c in the N-Well region 3 is the P-Well region 2
Is connected to the drain of the N-channel transistor 2b. A signal from the connection point between the drains is output to the chip internal circuit or to the pad 1.

As a method of arranging the plurality of power supply lines 3a and 3b in this embodiment, a plurality of power supply lines 3a and 3b are prepared in advance, and the I / OPW cell has the power supply lines 3a and 3b.
The one corresponding to 3b is arranged.

As described above, in this embodiment, the N-wells of a plurality of I / O cells arranged in the periphery of the chip are electrically separated for each I / O cell, so that they are isolated from other I / O cells. Different, power interface is realized. That is,
It is possible to realize an LSI that has no limitation on the arrangement of I / O cells and that can interface with multiple power supplies without increasing the size of the I / O cells. further,
Since the power supply lines 3a, 3b, 2a are arranged in a ring shape on each I / O cell, the power can be supplied to the I / O cell easily and accurately.

FIG. 3 is a diagram showing an internal configuration example of an I / O cell in a multi-power supply interface LSI according to the second embodiment of the present invention.

This embodiment enables the interface of three or more kinds of power supplies, and the arrangement of the I / O cells is the same as that shown in FIG. 1 in the above-mentioned first embodiment.

Even when the corresponding power source is increased as in this embodiment, the power source applied to the sources of the N-Well region 3 and the P-channel transistor 3c is changed as shown in FIG. That is, the N-well regions 3 of adjacent I / O cells are independently electrically separated for each slot,
A part of the P-channel transistor in the N-well region 3 is connected to the power supply line 3d whose source is added.

Further, three or more types of power supply lines 3a, 3b
As an arrangement method, as shown in FIG. 3, when the number of required power supplies is larger than the number of prepared power supply lines, one power supply line is disconnected according to the pin assignment.

In the present embodiment, it is possible to enable the interface of three or more kinds of power sources without changing the pin assignment only by changing the PW, and by temporarily changing the PW, a specific I / O cell is temporarily changed. Only the interface power supply can be changed.

[0030]

As described above in detail, the present invention provides a master slice type multi-power supply interface LSI in which a plurality of I / O cells are arranged around the chip and which interfaces a plurality of power supplies. O
Since the N-well of the cell is independent for each slot and the N-well of each adjacent I / O cell is electrically isolated,
There are no restrictions on the layout of I / O cells and the multi-power supply interface LS can be used without increasing the size of I / O cells
I can be provided. This improves usability and enables low cost.

Further, a specific I can be temporarily changed only by changing the PW.
It is possible to change the interface power supply only for the / O cell, and to interface not only two types but also three or more types.

[Brief description of drawings]

FIG. 1 is a diagram showing an arrangement of I / O cells in a multi-power supply interface LSI according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration example of an I / O cell in FIG.

FIG. 3 is a diagram showing an internal configuration example of an I / O cell in a multi-power supply interface LSI according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an arrangement of I / O cells in a first conventional example.

5 is a diagram showing an example of the internal configuration of the I / O cell of FIG.

FIG. 6 is a diagram showing an arrangement of I / O cells in a second conventional example.

7 is a diagram showing an internal configuration example of the I / O cell of FIG.

[Explanation of symbols]

 1 Pad 2 P-Well 3 N-Well 2a, 3a, 3b, 3d Power supply line 2b N-channel transistor 3c P-channel transistor VDD1, VDD2, VDD3 Power supply voltage VSS Ground power supply

Claims (3)

[Claims] 1. A master-slice-type multi-power supply interface LSI in which a plurality of I / O cells are arranged in the periphery of a chip and which interfaces with a plurality of types of power supplies, wherein the N-well of the I / O cells is provided for each slot. Independent,
A multi-power supply interface LS characterized in that the N-wells of adjacent I / O cells are electrically separated.
I. 2. The multi-power supply interface L according to claim 1, wherein a power supply line for supplying power to each of the I / O cells is arranged in a ring shape on the I / O cell.
SI. 3. The power supply line for supplying high power is composed of a plurality of electrically isolated lines.
The described multi-power supply interface LSI.