JPH08273371A - Ferroelectric memory and its driving method - Google Patents

Abstract

PURPOSE: To provide a ferroelectric memory which can be manufactured to a high degree of integration at a low cost and make nondestructive read feasible and a method of driving it and also a method of manufacturing it. CONSTITUTION: A pulse signal sending circuit is constituted of pulse signal sending circuits 11-13 for sending predetermined pulse signals 8-10 and a changeover switch 14. A memory cell 1 is disposed in a simple matrix form in which a ferroelectric thin-film 4 is held between a first and a second stripe electrodes 19, 20 which are opposed to each other and perpendicularly cross to each other. A ferroelectric cell matrix circuit 32 is constituted of terminal resistive element control circuits 35a, 35b provided with a terminal resistive element 34, memory cell selection circuits 15a, 15b and the ferroelectric cell matrix circuit 32. A ferroelectric memory is constituted of a differential reference cell 36 and a reading part 33 comprising a comparison amplifier and a signal processing circuit 37, and a predetermined pulse is applied to a selected memory cell to constitute two memory states, thereby performing nondestructive reading.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state recording device used in electronic circuits and the like, and more particularly to a ferroelectric memory as a solid-state recording device, a driving method thereof and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, in an electronic device which has been widely used, a recording device having high density and high performance is required especially when a computer and an image device are used. In response to such a demand, conventionally, an external recording device such as a magnetic tape, a floppy disk, a magneto-optical disk, or a semiconductor memory device such as DRAM, SRAM, EPRO
This is supported by M, EEPROM, flash memory and the like.

However, due to the fusion of the multimedia and the computer, which is being realized at present, the recording device has a non-volatile property in which the information stored by reading is not erased, is driven at high speed and low voltage, and operates mechanically. There is a need for a high performance and compact memory device that is a driveless solid-state memory that does not do so. However, such a demand cannot be satisfied by the conventional memory device, and there are various problems.

An example of a memory device that meets this requirement is USP 4,873,664 (S. Sheffield).
d Eaton Jr. , Colorado Spr
ings, CO).

FIG. 28 shows an example of the structure of this ferroelectric memory.

In the ferroelectric memory, the capacitance of the ferroelectric thin film 72 in the memory cell 71 functions as a switching element and is connected to one side of the ferroelectric thin film 72.
By T73, the driven DRAM type storage capacitance is changed to a ferroelectric capacitance.

The memory cell 71 includes a bit line 7
6, the reading is performed by the sense circuit 77 via the word line 74 and the plate line 75.

In this structure, since each element is formed on the Si substrate, the degree of integration and manufacturing cost are about the same as those of other semiconductor memories such as DRAM and FLASH memory. Therefore, when making a card of several hundred Mbytes,
It is also inconvenient in terms of cost.

In contrast, USP 5,060,191
As shown in FIG. 29, the memory device disclosed in the above publication is a system in which a simple matrix structure is made of a ferroelectric material 83 and signals are detected by the read drive circuits 84 and 85. A major problem of the memory device configured with such a simple matrix is that it affects other cells that are not selected.

For example, if a voltage Va is applied when a cell is selected and writing / reading is performed on the cell, unselected cells connected to the electrode lines on the input side / output side of the selected cell are not selected. Also, the voltage Va / 2
Will be applied. Therefore, as the number of cells increases, the number of unselected cells affected increases.

Therefore, in USP 5,060,191, for example, the applied voltage Va to the selected cell is
The write operation is performed by devising that Va / 3 is applied to the non-selected cells. In addition, for reading, a low-impedance voltage is read to cut noise from non-selected cells. However, when the voltage Va required for reversing the polarization of the selected cell is applied at the time of writing, the polarization state of the non-selected cell is destroyed by a large number of applications even at the voltage Va / 3.

Therefore, USP 5,140,548 (C.
J. In Brennan), it was considered that both the space charge layer and the neutral region existed in the ferroelectric substance to create the capacitance-voltage characteristic as shown in FIG.
In a state of 0 and a state of 91 written with a positive voltage, a voltage Vb equal to or lower than a certain coercive voltage Vth is applied, and A superimposed on this voltage Vb.
When the capacitance is measured by the C signal, it is 92 in the "1" state.
In the capacity of "0", the binary value of the capacity of 93 is obtained,
With this difference, a binary value of 92 is obtained in the "1" state, and a binary value of 93 is obtained in the "0" state. With this difference, "1" and "0" are obtained.
Is to determine.

Therefore, after writing, the polarization state is not changed by applying the read voltage of Vb with a time constant longer than the relaxation time of space charge and applying an AC waveform having a frequency component faster than the relaxation time. It is supposed to be able to read.

[0014]

However, one of the drawbacks of the above-mentioned conventional ferroelectric memory is that the combination with the semiconductor element shown in FIG. Switching element or FET on top
Therefore, the integration and manufacturing costs are
Same as M

Further, the ferroelectric memory having the simple matrix structure shown in FIG. 29 does not specifically disclose the guarantee against polarization breakdown of the ferroelectric cell at the time of writing. FIG.
When applied to a simple matrix, the method of using the capacitance change shown in 0 still has the problem of the configuration shown in FIG. 29 at the time of writing. Also when reading
In order to read the S / N ratio well, the read voltage Vb must be set to a high voltage to some extent.
If such an application is performed many times, the polarization of the ferroelectric cell is changed, and non-destructive read is not performed.

Therefore, an object of the present invention is to provide a non-destructive readable ferroelectric memory which can be manufactured with high integration and low cost, and a driving method and manufacturing method thereof.

[0017]

In order to achieve the above object, the present invention comprises first and second stripe electrodes facing each other and orthogonal to each other, and a ferroelectric thin film sandwiched between these stripe electrodes. And a first pulse is simultaneously applied to a matrix memory cell in which the intersecting regions of the stripe electrodes including the ferroelectric thin film are arranged in a matrix as a memory cell and all the memory cells of the matrix memory cell, The "0" information writing means for setting the first polarization state indicating "0" information and the memory cell selected from the memory cells in the first polarization state have a polarity opposite to that of the first pulse. "1" information writing means for applying a second pulse to set the second polarization state indicating "1" information, and a memory cell selected from the memory cells set to "0" and "1" To A read means for applying a third pulse to read information stored as a polarization state and one of the lines formed by the respective stripe electrodes of the matrix memory cell are provided, and when the third pulse is applied, By setting the input line and the output line directly connected to the selected memory cell to high resistance and setting the line connected to the non-selected memory cell to low resistance, and applying the third pulse, Provided is a ferroelectric memory including a read means for discriminating between "1" and "0" of the output signal of the read memory cell.

In the ferroelectric memory, all electrodes of the first stripe electrode and all electrodes of the second stripe electrode are selected, all memory cells are selected, and all selected memory cells are selected. By applying a first pulse having a magnitude of at least twice the coercive voltage of the ferroelectric thin film to the cell and setting the first polarization state indicating "0" information, all memory cells are A method of driving a ferroelectric memory for writing "0" information is provided.

Further, among the memory cells in which "0" information has already been written, each electrode in the first and second stripe electrodes is designated to select the desired memory cell, and the ferroelectric substance is selected. A voltage of 0.3 to 2 times the coercive voltage of the thin film is set as the write voltage Vw, and a voltage of Vw / 3 having a polarity opposite to that of the first pulse is applied to the designated first stripe electrode, and a non-designated voltage is applied. 0V is applied to the electrode of the first stripe electrode,
0 V is applied to the designated second stripe electrode, and 2 Vw / is applied to the non-designated second stripe electrode.
A voltage having a magnitude of 3 V is applied, and a domain having a polarization of the first polarization state showing “1” information to the selected memory cell and a polarization in a direction opposite to the first polarization state are provided. A method of driving a ferroelectric memory is provided by selectively setting "1" information in a desired memory cell by setting a partially polarized state in which domains are mixed.

[0020]

The "0" information is set in the memory cell of the ferroelectric memory having the above-described structure by setting the first stripe electrode and the second stripe electrode.
All electrodes of the stripe electrodes are selected, and a first pulse having a magnitude equal to or more than twice the coercive voltage of the ferroelectric thin film is applied to all the memory cells, and all the memory cells are collectively subjected to the same first voltage. The polarization state (“0” information) is set. "1" to the memory cell
Information is set in a memory cell in which “0” information is set in the matrix memory cell, and a desired memory cell is selected by designating each electrode of the first stripe electrode and the second stripe electrode. select. At the write voltage Vw, which is 0.3 to 2 times the coercive voltage of the ferroelectric thin film for the selected memory cell, Vw / 3 for the selected first stripe electrode and the unselected first stripe electrode To the selected second stripe electrode, and a second pulse having a magnitude of 2Vw / 3 is applied to the selected second stripe electrode 19 and the non-selected second stripe electrode 19 so that the partial polarization state ("1") is applied only to the desired memory cell. Information).

A desired resistance memory cell is selected from the matrix memory cells, and a terminating resistance element connected to the ends of the first stripe electrode and the second stripe electrode serving as the input line and the output line of the selected memory cell has a high resistance. Then, the resistance of the terminating resistance element connected to the first stripe electrode and the second stripe electrode connected to the non-selected memory cell is made low. After that, a third pulse having a read voltage of 0.3 times or less the coercive voltage of the ferroelectric thin film is applied to a desired memory cell to read "0" and "1" information, and a low input impedance circuit. The output from the low input impedance circuit is differentially amplified by a differential amplifier circuit,
Further, it is comparatively amplified by the comparative amplifier circuit to be "1""0".
Is determined and the read operation ends.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A ferroelectric memory as a first embodiment according to the present invention will be described with reference to FIGS.

FIG. 8 shows an example of the structure of the memory cell of the ferroelectric memory in this embodiment. In this memory cell 1, the ferroelectric thin film 4 sandwiched by the pair of upper and lower electrodes 2 and 3 made of platinum or the like, when a predetermined voltage is applied between the electrodes, The polarization amount changes non-linearly and has a hysteresis characteristic as shown in FIG.

This hysteresis characteristic is usually measured by using a continuous sin wave of about 1 KHz or a triangular wave. Here, Pr is the residual polarization amount, Ps is the saturation polarization amount, and V is
Let c ′ be the coercive voltage.

In FIG. 3, for example, Pb (Zr0.4Ti0.6) O
3 For the ferroelectric thin film 4 (hereinafter referred to as PZT),
The relationship between the polarization breakdown amount ΔP when a single pulse is applied and the magnitude Va of the applied pulse is shown. Where the polarization breakdown amount Δ
P expresses how much the polarization amount of the ferroelectric thin film 4 changes by applying a pulse of Va, that is, how much it is destroyed.

In FIG. 3, the coercive voltage Vc is defined by the voltage value at which .DELTA.P becomes 0.5. Generally, the coercive voltage Vc 'is evaluated by applying a continuous wave as shown in FIG. 2 (a). , The coercive voltage found in Figure 3 evaluated while applying a single pulse is different. In the following Examples, the coercive voltage means Vc when showing a quantitative relationship with the coercive voltage. FIG.
The region [I] is a region in which the polarization state set in the first direction does not change even when a pulse having a corresponding magnitude is applied. Hereinafter, in each of the examples, the first polarization state 5 is defined as the point A in the negative direction with respect to the origin in FIG. Then, the digital data “0”
Is defined. Considering the read margin between the first polarization state 5 and the partial polarization state 6 (which will be described later), which is one of the storage states, it is better to make the electric characteristics as different as possible between the two. It is preferable that the first polarization state 5 is a completely polarized state.

However, it goes without saying that the perfect polarization state is not an essential requirement, and the perfect polarization state is not required as long as the read margin amount that can discriminate the data "1" or "0" can be secured. On the other hand, the partial polarization state 6 described later is defined as "1". This is only defined in order not to confuse future explanation, and conversely the first polarization state 5
Is defined as “1” and the partial polarization state 6 is defined as “0”,
It goes without saying that the inventions can be carried out exactly the same.

Here, the first polarization state 5 and the partial polarization state 6 will be described.

In this embodiment, data "1""0"
Are not brought into the saturated polarization state together, but one is made to correspond to the data "0" in the saturated polarization state (first polarization state 5) and the other to the data "1" in the partial polarization state 6.

FIG. 2B shows the hysteresis characteristic of the ferroelectric substance. In this FIG. 2B, a negative voltage −Va sufficient to invert the polarization is applied to the ferroelectric capacitor,
When the applied voltage is removed, the polarization state becomes X. This is data “0”. Then, when a positive partial polarization generating voltage Vp having an appropriate magnitude satisfying at least Va> Vp is applied to the memory cell in the polarization state X, the polarization state becomes
The transition is X → D → E, and the state is a partial polarization state that is neither X nor Z. In the figure, the Y region having the maximum capacitance is in a partially polarized state created by applying a positive pulse having a magnitude similar to the voltage Vc defined in the characteristic obtained by applying a single pulse. Correspondingly, it is difficult to illustrate on a hysteresis characteristic curve which is a characteristic obtained by applying a continuous wave, but the vicinity of the midpoint of X and Z is a partially polarized state.

Therefore, in this embodiment, the first polarization state 5 is located at X in FIG. 2B and the partial polarization state 6 is shown in FIG.
It shall be located at Y in (b).

Further, in FIG. 3, [III] is a region having a state in which the first polarization state 5 is inverted by the applied pulse to the second polarization state 7 which is the other full polarization state. Since the first polarization state 5 is defined by the point A in FIG. 2A, the second polarization state 7 is the point A on the positive side of the origin. [II] is a partially polarized state 6
Area. That is, the partial polarization state 6 is a polarization state having a mixed state of the first polarization and the second polarization.

As can be seen from the above description, this partial polarization changes the polarization state of the ferroelectric thin film 4 to the first by the first pulse having the negative direction from the first pulse sending circuit 11 shown in FIG. The polarization state is set to 5, and then the second pulse having the positive direction from the second pulse transmission circuit 12 is applied.

As described above, FIG. 3 shows the measured data for the ferroelectric thin film 4. In practice, a pulse having a magnitude of 2 to 2.5 times the coercive voltage Vc of the ferroelectric thin film 4 is actually used. By applying, ΔP = 1, and the polarization is completely destroyed. That is, the polarization can be completely inverted.

Therefore, the coercive voltage Vc of the ferroelectric thin film 4 is 2
A negative first pulse from a first pulse power source having a magnitude of 2 to 2.5 times is applied to set the polarization state of the ferroelectric thin film 4 to the first polarization state 5, and then, Ferroelectric thin film 4
The partial polarization state 6 can be formed by applying a positive second pulse from the second pulse transmission circuit 11 having a magnitude of 0.3 to 2 times the coercive voltage Vc of. Of course,
It has been confirmed that the partially polarized state 6 exists extremely stably.

A basic memory operation using the first polarization state 5 and the partial polarization state 6 will be described with reference to FIG.

First, information is written (stored) in the memory cell 1 selected by the memory cell selection circuit 15b,
Conversely, at the time of reading, the desired memory cell 1 is similarly selected by the cell selection circuit 15b, and the stored information is
It is read by an appropriate read circuit 17.

Writing of information is performed as follows. The memory cell 1 has a first polarization state 5 caused by the first pulse sent by the first pulse sending circuit 11.
The polarization is set in the (negative direction), and then the partial polarization state 6 is set by the second pulse sent by the second pulse sending circuit 12.

The changeover of the first pulse transmission circuit 11 and the second pulse transmission circuit 12 is performed by the changeover switch 14
It is performed by At this time, the first pulse is a negative pulse having a magnitude Ve that is 2.5 times or more the coercive voltage Vc of the ferroelectric thin film 4, and the second pulse is a coercive voltage of the ferroelectric thin film 4. It was a positive pulse with a magnitude Vw of one time Vc.

For reading, similarly to writing, the desired memory cell 1 is selected by the cell selecting circuit 15b, the third pulse is applied by the third pulse sending circuit 13, and the information is read by the reading circuit 17 from the memory cell 1. Read out.

FIG. 5 shows the second polarization forming the partially polarized state 6.
And the capacitance value Cp of the ferroelectric thin film 4 having the partial polarization state 6 thus formed. The capacitance value Co at the point of voltage 0 (point X) is the capacitance value of the ferroelectric thin film 4 having the first polarization state 5, but the magnitude Vw of the second pulse forming the partial polarization state 6 is As the capacitance value increases, the capacitance value Cp increases, reaches a maximum, and then decreases.

Therefore, the capacitance value Cp is different between the first polarization state 5 and the partial polarization state 6. The difference between the two capacitance values Δ
C is detected by the read circuit 17 and "1" or "0" is discriminated. As is apparent from FIGS. 3 and 5, the magnitude Vw (absolute value) of the second pulse, that is, the magnitude of the voltage forming the partially polarized state 6 is determined by the coercive voltage Vc of the ferroelectric thin film 4.
Cp can be maximized and, conversely, Co can be minimized by setting the first polarization state 5 to a complete polarization state, and therefore, the difference ΔC in capacitance value, which is a read margin, is maximized. Therefore, it is possible to realize a ferroelectric memory capable of performing a read operation with good S / N.

Next, FIG. 6 shows a ferroelectric memory having a simple matrix arrangement of memory cells for description.

In this ferroelectric memory, one of a pair of electrodes facing each other has a stripe shape, or a plurality of electrodes electrically connected to the electrodes are arranged in a stripe shape in a first stripe electrode. 19 and a second stripe electrode 20 in which the other of the pair of electrodes is in a stripe shape, or a plurality of electrodes electrically connected to the electrodes are arranged in a stripe shape, and the second stripe electrode 20 is arranged in parallel. It is composed of a ferroelectric thin film 5 sandwiched therebetween. That is, as shown in FIG. 8 described above, the upper electrode 2 of the memory cell 1 and
The lower electrodes 3 are formed in stripes so as to be orthogonal to each other. However, either the upper electrode 10 or the lower electrode 11 may be the first stripe electrode 19 or the second stripe electrode 20.

The first stripe electrode 19 and the second stripe electrode 20 are substantially orthogonal to each other with the ferroelectric thin film 4 interposed therebetween, and the memory cell 1 has an intersection region with the first and second stripe electrodes 19 and 20. And

Further, in the DRAM, a MOS transistor is provided as an electrical switch for each cell in order to prevent crosstalk with other cells that are not selected. However, in the memory cell 1 of the embodiment, the MOS transistor is not provided for each memory cell. Next, the write operation to the ferroelectric memory will be described.

First, the first polarization state 5 is set. In this case, the desired cell Cs 21 is selected by the memory cell selection circuits 15a and 15b, and the first pulse is applied only to the cell Cs 21 selected by the first pulse transmission circuit 11. Next, the changeover switch 14 is changed over, and the second pulse sending circuit 12 applies the second pulse only to the selected cell Cs 21.

However, in the case of the simple matrix structure as described above, there is mutual interference (crosstalk) with the adjacent cells, and it is impossible to apply a voltage only to the selected cell Cs 21. Therefore, when the voltage Va is applied to the cell Cs 21, some voltage is also applied to the adjacent non-selected cell Cus.

As shown in FIG. 7A, in the case of forming a simple matrix without an electric switch of a MOS transistor, the capacitance C (cell) is formed in an n × n matrix. Then, when the desired cell Cs 21 is selected and a voltage of Va is applied, the voltage applied to each cell including the non-selected cell Cus is as shown in FIG. 7B.

Therefore, a non-negligible voltage is applied to the unselected cells Cus which are not selected. As the matrix size n × n increases, the voltage applied to the non-selected cells Cy 22 and Cx 23 connected to the input line and the output line is half the voltage Va applied to the selected cell Cs 21, that is, Va / It approaches 2.

FIG. 3 shows the polarization destruction amount ΔP with respect to the magnitude of the applied pulse to the PZT ferroelectric thin film. In order to make the first polarization state 5 a perfect polarization state,
It is necessary to apply at least twice as much as Vc, and preferably to apply the first pulse having a magnitude of 2.5 times Vc.

Then, about half the voltage, that is, a voltage about the same as Vc, is applied to the Cy22 and Cx.
23. And as is clear from FIG.
When a voltage of about c is applied, the polarization is half, 50
% Changes. As will be described later, by setting the partial polarization state 6 written with a magnitude of about Vc to "1", a memory with a good S / N is realized, so "1" is the second magnitude of Vc. The partial polarization state 6 produced by a pulse is used. Therefore, application of a voltage of about Vc to Cy 22 and Cx 23 means that the stored "0" is rewritten to "1", which causes the destruction of the stored state.

FIG. 1 shows an example of the structure of a ferroelectric memory as the first embodiment.

This ferroelectric memory is roughly classified into a pulse signal transmitting section 31 for transmitting a predetermined pulse signal, a ferroelectric cell matrix circuit 32 using a ferroelectric thin film for storing information as a memory cell, It is composed of a reading unit 33.

The pulse signal transmission section 31 includes three pulse transmission circuits 11, 12 and 13 for transmitting the first, second and third pulse signals described above with reference to FIG.
4 and 4.

In the ferroelectric cell matrix circuit 32, the memory cells 1 having the structure shown in FIG. 8 are arranged in a simple matrix structure, and a pair of opposing first stripe electrodes 19 as shown in FIG. A second stripe electrode 20 provided in a direction orthogonal to the first stripe electrode 19 is provided. However, the first stripe electrode 19 and the second stripe electrode 20 may be either the upper electrode 2 or the lower electrode 3. The first of these
A region where the stripe electrode 19 and the second stripe electrode 20 intersect becomes a memory cell 21.

A terminating resistance element control circuit 35a having a terminating resistance element 34 electrically switched to a high resistance or a low resistance and having one end grounded is provided at each end of one of the stripe electrodes 19 and 20. , 35b are provided. In this termination resistance element 34, for example, as shown in FIG. 10, a MOS transistor is connected to each line, and the gate is set to High by the termination resistance element control circuits 35a and 35b.
The resistance value can be changed by setting to h or Low.

The reading section 33 includes a reading circuit 17
And the differential reference cell 36, and the read circuit 17
Is composed of a signal processing circuit 37 and a comparison and amplification circuit 38.

The signal processing circuit 37 includes a low input impedance circuit 39, a differential amplifier circuit 40 and a differential reference cell 4.
Consists of one.

The ferroelectric memory having the above structure is
The first stripe electrode 19 and the second stripe electrode 2
A first pulse having a magnitude Ve larger than the coercive voltage Vc of the ferroelectric thin film 4 (not shown) of the memory cell 21 is applied from 0 to set the polarization state to either one of the two saturation polarization states. , Its polarization state is defined as a first polarization state 5, and the first polarization state 5 and the ferroelectric thin film 4 in the first polarization state 5 are provided with a magnitude Vw having a polarity opposite to that of the first pulse. By applying a second pulse having a partial polarization state 6 in which a domain having a polarization of the first polarization state 5 and a domain having a polarization in the opposite direction are mixed to form two memory states. , The memory state is read by applying a third pulse having a magnitude Vr.

Writing in the ferroelectric memory configured as above will be described in detail.

First, the polarization setting for setting the first polarization state 5 by the application of the first pulse from the first pulse transmission circuit 11 is performed by the memory cell selection circuit 15b to all the stripe electrodes 19 by the 15th. At the same time, all the second stripe electrodes 20 are also selected by the memory cell selection circuit 15a, and the changeover switch 14 is changed over to the first pulse transmission circuit 11 side. For example, Vc of the ferroelectric thin film 4 is changed.
The first pulse with a magnitude of 2.5 times is applied to all cells.

Since all the cells are collectively set to the same first polarization state 5 as described above, it is not necessary to consider the problem of crosstalk. By this operation, all cells are set to data "0".

Next, data "1" is written in the desired memory cell 21.
Writing for setting the partial polarization state 6 corresponding to will be described.

First, a desired cell to be set to "1" is selected by the memory cell selection circuits 15a and 15b, and the changeover switch 14 is changed over to the second pulse transmission circuit 12 side.

Then, the selected first stripe electrode 19
Is Vw / 3, the unselected first stripe electrode 19 is 0 (V), and the selected second stripe electrode 20 is Vw / 3.
0 (V) is applied to the non-selected second stripe electrode 20 by 2 Vw
A voltage having a magnitude of / 3 is applied.

By this application, Vw is applied to the memory cell Cs 21 and Vw / 3 (absolute value) is applied to the non-selected cell Cus. Therefore, only a small voltage of Vw / 3 is applied to the non-selected cell Cus. This drive method is hereafter referred to as 1/3
Called the driving method.

The magnitude of Vw can be set to the partially polarized state 6 by setting Vc of the ferroelectric thin film 4 to 0.3 times to 2 times Vc, and a desired value is selected in this range. Just do it. Further, in order to maximize the S / N at the time of reading as a memory, it is necessary to maximize the capacitance value difference ΔC between “1” and “0” that is the source of the read signal, as described above. It is desirable that the size is about one time Vc (see FIG. 5).

In this embodiment, Vw = 0.9Vc is set in order to set the voltage applied to the non-selected cell Cus to 0.3Vc. By doing so, as can be seen from FIG. 9, at least 0.3 Vc applied to the non-selected cells, at least 10
^The polarization is not destroyed by applying ⁹ pulses.

FIG. 9 shows a memory cell 21 having a first polarization state 14 and a partial polarization state 6 written at Vc,
The amount of change in polarization is shown with the applied voltage having a positive polarity and the number of times of application as parameters. In either polarization state, with an applied voltage of 0.3 Vc or less, the polarization hardly changes at least until the evaluated 10 ⁹ pulse application. That is, if the applied voltage is 0.3 Vc or less, the polarization state of the non-selected cells Cus other than the selected cell Cs21, that is, the storage state is not changed. By performing this operation sequentially and setting a desired memory cell in all the cells to the partially polarized state 6, the write operation of the data "1" is completed.

Next, the read operation in the ferroelectric memory of this embodiment will be described in detail.

First, at the time of reading, a desired memory cell (selected cell Cs) 21 is selected by the memory cell selection circuits 15a and 15b as described above. Then, the changeover switch 14 is changed over, the third pulse of the magnitude Vr is applied from the third pulse sending circuit 13 to the selected memory cell 21, and the response is detected.

At this time, there is crosstalk with the memory cell (non-selected cell Cus) adjacent to the selected memory cell 21, and the same problem as in the above-described writing occurs. That is, the third pulse is applied to the non-selected cells Cus other than the selected cell Cs 21 as well, and the value according to FIG. 7B is applied, and the response is mixed in the output line, so that the read S /
Deteriorate N.

Therefore, as the matrix size n × n becomes larger, as shown in FIG. 7B, 1 / th of the magnitude Vr of the third pulse is applied to each memory cell connected to the input line and the output line. Since the magnitude of 2 is applied, the noise amount becomes large depending on the storage state of the non-selected cell, and even if the storage state of the selected cell is “1”, it is determined as “0” due to the noise amount. , Or vice versa. Further, even if the 1/3 drive method, which is a device devised at the time of writing, is used, a voltage of Vr / 3 is applied to each non-selected cell Cus, and the output line is seen from each non-selected cell Cus. Since it is always at the Low level, all signals (noise) from the non-selected cells Cus are mixed in the output line.

In order to prevent this, in the present embodiment shown in FIG. 1, (1) first stripe electrode 19 and second stripe electrode 2
A terminal resistance element 34 that is electrically switched to a high resistance or a low resistance is connected to each of the 0 ends. (2) A low input impedance circuit 39, a differential amplifier circuit 40, and a comparison amplifier circuit 38 are provided on the output line of the ferroelectric cell matrix circuit 32.

With this configuration, the signal from the selected cell Cs 21 can be read out with good S / N. The operation / effect will be described in detail below.

First, a desired memory cell is selected by the memory cell selection circuits 15a and 15b. At this time, the termination resistance element 34 connected to the termination of the input line and the output line
Is set to a high resistance Roff by the termination resistance element control circuits 35a and 35b. The termination resistance element 34 connected to the other lines has a low resistance Ron.

In the termination resistance element 21, as shown in FIG. 10, the MOS transistor 42 is connected to each line, and the gate is set to High by the termination resistance element control circuits 15a and 15b.
The resistance value can be changed by setting to h or Low. A low resistance value of 1 KΩ and a high resistance value of 10 ¹² Ω can be realized. Alternatively, a bipolar transistor or the like may be used.

Next, at this time, the termination resistance element 34 connected to the termination of the input line and the output line is connected to the high resistance Roff.
The reason for doing so will be described.

Termination resistance element 34 connected to the input line
Will predominantly determine the input impedance Zif of the ferroelectric cell matrix circuit 32 viewed from the third pulse transmission circuit 13. As will be described later, this low resistance Ron is required to have a very small value, and when the termination resistance element 34 connected to the input line is set to Ron having a small resistance value, Ry shown in the equivalent circuit of FIG. Ron, so Z
If becomes very small, current consumption is heavy, and the load on the third pulse sending circuit 13 becomes very large.

On the other hand, when the terminating resistance element 34 of the output line is a low resistance Ron having a small resistance value, Rx of the equivalent circuit shown in FIG. 11 becomes Rx = Ron, so that the low input impedance circuit 39 in the read circuit 17 is Depending on the relationship with the input impedance Zin, the output signal generated from the selected cell Cs 21 passes through Rx having a small impedance to G
The amount of signal that flows into the ND and flows into the read circuit 17 side is reduced.

Therefore, the termination resistance element 34 connected to the termination of the input line and the output line is set to a high resistance Roff by the termination resistance element control circuits 35a and 35b. However, as will be described below, there is a case where Ron does not necessarily need to be reduced to a value that causes the above problem, and the terminating resistance element 34 connected to the ends of the input line and the output line has a high resistance Rof.
It is not always necessary to use f. It may be determined whether or not the above operation needs to be performed according to the value of Ron determined from the performance required for the memory. If it is not necessary, the terminating resistance element 34 does not need to be an element that can electrically switch between the low resistance Ron and the high resistance Roff, and, of course, the terminating resistance element control circuits 15a, 1 for switching.
5b is not necessary either. Fixed low resistance Ron termination resistance element 3
4 may be connected to each line.

Consider a case where a continuous sine wave having a single frequency component with an amplitude of Vr is applied to such a ferroelectric cell matrix circuit 32. At this time, the voltage applied to each memory cell forming the ferroelectric cell matrix is almost "0" except for the cell Cy20 connected to the input line. This state will be described with reference to FIG. 11, which is an equivalent circuit of the ferroelectric cell matrix circuit 32 in FIG.

Here, the terminating resistance element 34 is an element whose resistance value Ron satisfies the following expression when electrically set to a low resistance.

Ω << 1 / CRon ... Eq. (1) ω: Angular frequency of applied voltage C: Capacity value of memory cell 21 As a minimum requirement, it is sufficient that the relationship between ω and C is satisfied. Generally, one of the performances required for a memory is access speed. To increase this, of course, ω becomes large, but the low resistance R
on needs to be small. For example, assuming a 1 Mbit memory and a cell size of 2 × 2 μm ² , the capacitance value of PZT is about 150 fF. Then 10M
When driving at Hz, the low resistance Ron must be Ron << 100 KΩ, preferably Ron = several KΩ.

Focusing on the non-selected cells shown in FIG. 11, FIG. 12 shows a rewritten equivalent circuit in consideration of the potential and current path of each node.

The circuit shown in FIG. 12 constitutes a multi-stage high-pass filter, and under the condition that Eq. (1) is satisfied, the cell Cy 22 connected to the input line 44 receives the third pulse of the third pulse. Although a pulse having the same magnitude as the magnitude is applied, in the equivalent circuit of FIG. 11, Cxy43, Cx23
Almost no voltage is applied to the other non-selected cells indicated by. Because Ron that grounds the line has a sufficiently small value and the impedance is low, the current path is connected through the resistor R connected to the non-selected cell connected to the input line 44 as shown by the size of the arrow in the figure. That is, what flows into GND is dominant.

As described above, since the low resistance Ron has a small value, there is almost no voltage effect on the resistance R. Therefore, the potential at the point a shown in FIG. 11 is almost “0”. Furthermore, since the Cxy 43 and the low resistance Ron have the same configuration, the potential at the point b further approaches "0".
Further, as described in the present embodiment, the current flowing through Cy 22, Cxy 43, that is, the noise from the non-selected cells Cy 22, Cxy 43 flows into GND via the low resistance Ron,
It does not flow into the output line 45. Further, since the low input impedance circuit 39 receives the output signal, the potential at the point c is low, and the magnitude Vr of the applied third pulse is efficiently applied to the selected cell Cs 21, and the selected cell Cs 21 is efficiently supplied. Cs 2
Since the signal from 1 efficiently flows into the low input impedance circuit 39 having a low impedance, it is possible to read with a good S / N.

The magnitude Vr of the third pulse is 0.3 times or less of Vc of the ferroelectric thin film 4. By doing so, as is apparent from FIG. 9 described above, even if the pulse is applied at least 10 ⁹ times, the polarization state of the ferroelectric thin film 4 naturally does not change the capacitance value. That is, the memory state does not change.

Therefore, a termination resistance element 34 that can be electrically switched to a high resistance or a low resistance is connected to one end of each of the first striped electrode 19 and the second striped electrode 20, and the ferroelectric cell matrix circuit 32 is connected. By connecting the low input impedance circuit 39 to the output line of, a high S / N read without crosstalk becomes possible.

Further, by using the third pulse having a magnitude of 0.3 times or less of Vc of the ferroelectric thin film 4, the selected cell C is
Not to mention s21, nondestructive reading is possible without changing the memory state of the non-selected cell Cy22 to which a voltage substantially equal to the applied voltage is applied.

Next, the signal processing from the low input impedance circuit 39 to the subsequent stage will be described. Vc = shown in FIG.
A specific operation will be quantitatively described in the case of a PZT thin film of 2.5V.

FIG. 3 shows the relationship between the magnitude Vw of the second pulse, which is the partial polarization generation voltage for this PZT, and the capacitance value Cp. When Vw = 0 and Vw = 2.5.
Capacitance difference ΔC of “1” and “0” with V (= Vc)
Is about 10 to 20%. In order to amplify only this change, the differential amplifier circuit 40 is arranged in the subsequent stage of the low input impedance circuit 39 as shown in FIG. 13, and the output Ao of the low input impedance circuit 39 is provided at one signal input terminal 40a. The differential reference signal Aref flows into the other differential reference signal input terminal 40b which is input and compared. The magnitude of this differential reference signal Aref may be appropriately determined. Further, the differential reference signal Aref having an appropriate value may be input by a power source such as a current source.

Here, the size of Aref is determined as follows. It is impossible to uniquely determine the storage state of the storage cell 21 in the ferroelectric cell matrix circuit 32,
Generally, "1" and "0" are randomly stored, but can be expressed in the following four cases as extreme cases. The random state is an intermediate state between these cases, and it is sufficient to consider the read operation for these four cases. Case 1 Case 2 Case 3 Case 4 Selected cell Cs “1” “1” “0” “0” All unselected cells “1” “0” “1” “0” Output signal A11 A10 A01 A00 At least A1j> A0k …… Eq. (2) Here, if j, k = 0, 1 is satisfied, it is not limited to the above four cases, and "1" and "0" can be discriminated in all memory states. You can The minimum value Amin of the output signal is A0
1 or A00. This changes depending on the electrical relationship between the ferroelectric cell matrix circuit 32 and the low input impedance circuit 39.

It does not matter whether A11> A10 or A11 <A10, or A01> A00 or A01 <A00. The above relational expression Eq. (2) is satisfied, and ΔA is ΔA ≠
If it is 0, it is possible to determine “1” or “0”. A11
> A10 or A11 <A10 is also A01> A00
Whether A01 <A00 is determined if the memory configuration / circuit is determined. Here, the following description will be given assuming that A10 ≧ A11> A00 ≧ A01. Therefore, Aref = Amin. As is apparent from FIG. 14, by setting Aref = Amin, the base component can be removed and only the difference can be amplified within the power supply voltage, so that the signal difference can be maximized.

Next, the comparison and amplification circuit 38 will be described.
Here, the amplification factor of the low input impedance circuit 39 is "1". When the amplification degree of the differential amplifier circuit 40 is α, the signal difference is multiplied by α within the power supply voltage range after passing through the differential amplifier circuit 40. The output signal Vs is further connected to the read signal input end 38a of the comparison and amplification circuit 38 and compared with the comparison reference signal Vref of the comparison reference cell 36 connected to the other comparison reference signal input end 38b to obtain Vs. > V
In the case of ref, the read signal input end 38a is latched to approximately the power supply voltage Vdd, and the other comparison reference signal input end 38b becomes the GND level.

On the contrary, when Vs <Vref, the opposite is true, and after the operation of the comparison and amplification circuit 38, the read signal input terminal 38a is "1" depending on whether Vdd level or GND level,
"0" can be discriminated.

Generally, the comparison / amplification circuit 38 is known as a flip-flop type sense circuit and is used in a semiconductor memory such as a DRAM. In principle, Vs ≠ Vref
If so, the difference ΔV operates normally even if the difference ΔV is small. However, variations in the performance of the transistors that make up the
Stray capacitance / resistance difference caused by wiring asymmetry,
Further, ΔV is 100 to 100 depending on the required operation speed.
About 200 mV is required. In the case of PZT, Vc
= 2.5V, the magnitude of the third pulse is
In order to guarantee the non-destructive property of polarization, the magnitude of the third pulse is 0.75 V at most because it is not more than 3 times Vc.

For example, the low input impedance circuit 39 has a simple capacitance CL. Low input impedance circuit 39
Alternatively, a simple resistance element, a base-grounded bipolar transistor, or the like may be used. Here, a simple capacitive element will be described.

The input impedance of the low input impedance circuit 39 needs to be at least larger than the capacitance value Cs of the selected cell Cs 21 because of the requirement of lowering it. Here, the value of CL must be properly designed depending on n in the case of n × n memory.
Here, description will be made assuming that CL = 10 Cs. Then, the electric potential Vo of the output line is determined by the ratio of Cs and CL because the amount of noise mixed in is extremely reduced by the above-mentioned device, and Vo = CL / (CL + Cs) at most. In reality, the combined impedance of the non-selected cells connected to the output line cannot be ignored and is smaller than Vo, but here V
Proceed as o.

Furthermore, the capacitance value difference ΔC between “1” and “0”
Is about 10 to 20% as described above, the voltage change ΔV of the output line is about 10 mV. Therefore, the comparison and amplification circuit 38 cannot directly perform comparison and amplification. Therefore, in order to operate normally, the differential amplifier circuit 40
Therefore, it is necessary to amplify ΔV. The condition under which α can be maximized is Aref = Amin described above. Amplification degree α
= 10 to 20, the voltage change of the output line is ΔV =
The voltage can be set to 100 to 200 mV, and the comparison and amplification circuit 38 can be sufficiently operated normally and stably.

As shown in FIG. 15, the comparison reference signal Vref input to the comparison / amplification circuit 38 may be an intermediate value Vref between the read signals V1 and V0 corresponding to the data "1" and "0". With respect to this Vref, the potentials of the read signal input end 38a and the reference signal input end 40a are compared and amplified to High or Low depending on whether the signal input to the signal input end 40a of the comparison and amplification circuit 38 is large or small.

As described above, the ferroelectric thin film 4 sandwiched by the pair of electrodes, the upper electrode 2 and the lower electrode 3 is
A first pulse having a magnitude Ve greater than the coercive voltage Vc of the ferroelectric thin film 4 is applied to set the polarization state to either one of the two saturation polarization states, and the polarization state is set to the first polarization state.
Of the first polarization state 5 and a second pulse having a magnitude Vw opposite in polarity to the first pulse is applied to the first polarization state 5 and the ferroelectric thin film 4 in the first polarization state 5. Then, two memory states are formed by the partial polarization state 6 in which the domain having the polarization of the first polarization state 5 and the domain having the polarization in the opposite direction are mixed, and the size of the storage state is set. In a ferroelectric memory for applying and reading a third pulse having Vr, one of the pair of electrodes is in a stripe shape, or a plurality of electrodes electrically connected to the electrodes are in a stripe shape and are substantially parallel to each other. A first stripe electrode 19 arranged in a row and the other of the pair of electrodes in a stripe shape, or a plurality of electrodes electrically connected to the first stripe electrode in a stripe shape, and a second stripe electrode Electrode consisting of stripe electrode 20 The first stripe electrode 19 and the second stripe electrode 20 are substantially orthogonal to each other with the ferroelectric thin film 4 sandwiched therebetween. The region intersecting with 20 is set as the memory cell 1, and the stripe electrodes 19 and 20 are formed.
A signal composed of a ferroelectric cell matrix circuit 32 having a termination resistance element 34 that is electrically switched to a high resistance or a low resistance at each end of one side, and at least a low input impedance circuit 39 and a differential amplifier circuit 40. The read circuit 17 is characterized by including a processing circuit 37 and a comparison and amplification circuit 38.

By using the ferroelectric memory, it is possible to realize a large-capacity ferroelectric memory which has a high S / N ratio without interference (crosstalk) with other cells and which does not destroy the memory state of the memory cell.

The output terminal of the low input impedance circuit 39 is directly or indirectly input to one signal input terminal 40a of the differential amplifier circuit 40, and the other differential reference signal input terminal is input. 40b is a differential reference signal Aref
Further, the output of the differential amplification circuit 40 is directly or indirectly input to one read signal input end 38a of the comparison amplification circuit 38, and the other comparison reference is input. The comparison reference signal V is applied to the signal input end 38b.
By characterizing that the ref has been entered,
A ferroelectric memory capable of reading at high S / N can be realized.

Further, by setting the differential reference signal Aref to the minimum value Amin of the signal output according to the storage state of the ferroelectric cell matrix circuit 32, the output signal difference ΔA is maximized. It is possible to realize a ferroelectric memory that can be amplified by the amplifier circuit 40, can realize stable and accurate operation of the comparison amplifier circuit 38, and can perform accurate read operation.

Next, a second embodiment of the ferroelectric memory according to the present invention will be described.

In the ferroelectric memory of this embodiment, as shown in FIG. 13, the differential amplifier circuit 40 is arranged at the subsequent stage of the low input impedance circuit 39, and one signal input terminal 40a is provided.
Is connected to the output Ao of the low input impedance circuit 39, and the differential reference signal Aref flows from the other differential reference signal input terminal 40b to be compared. This differential reference signal Are
In the first embodiment described above, the magnitude of f is Aref = Ami
I assumed n. However, as will be described later, the capacitance values of the first polarization state 5 and the partial polarization state 6 change according to temperature and elapsed time. Although a device for that purpose will be described in an embodiment described later, it is still difficult to accurately perform the differential reference signal Aref = Amin.

Here, a more realistic differential reference signal Are
The size of f will be described.

In the signal output according to the storage state of the ferroelectric cell matrix circuit 32 shown in FIG. 1, the minimum output value Am1 when the selected cell Cs 21 is "1" and the selected cell Cs 21 are Maximum value Am2 of output value in case of "0"
It should be a value between and. As described in the first embodiment, since A10 ≧ A11> A00 ≧ A01, Am1 = A11 and Am2 = A00. By doing so, even if Amin fluctuates to some extent, the base component shown in FIG. 14 can be reliably removed, so that the amplification degree α of the differential amplifier circuit 40 can be maximized within the power supply voltage, and the comparative amplification can be performed. The circuit 38 can be easily amplified to a desired signal level that enables stable and accurate operation.

As described above, in the signal that outputs the differential reference signal Aref in accordance with the storage state of the ferroelectric cell matrix circuit 32, the minimum output value Am1 when the selected cell is "1". And the maximum value Am2 of the output value when the selected cell is "0", the base portion of the read signal can be reliably removed, so that the amplification degree α is maximized within the power supply voltage. Therefore, stable differential amplification by the differential amplification circuit 40 and accurate comparison amplification by the comparison amplification circuit 38 are realized.

A ferroelectric memory as a third embodiment according to the present invention will be described.

In this embodiment, the differential reference signal Aref and the comparison reference signal Vref will be described with reference to FIG.

Differential reference signal Aref and comparison reference signal V
If ref is a reference signal having the magnitude of the above-described first embodiment, the reference signal may be input at the same timing as the read signal. For example, a reference power source such as a current source or a voltage source may be provided.

The characteristics of the memory cell 1, that is, the capacitance value according to the memory state may be unchanged in any case, but in reality, it changes as shown in FIG.

FIG. 16 shows changes with temperature. The capacitance value in each polarization state increases with the image of temperature. The change is
Basically keep the Cp-Vp curve and shift overall. Therefore, at a certain temperature, the relationship of "1" and "0",
The difference ΔC is almost maintained. However, the amount of shift with respect to temperature is not a negligible amount, and for example, the maximum value of Cp at room temperature (20 ° C.) Cpa (point A in the figure) and 100
With the minimum value of Cp at C, Cpb (point B in the figure), Cpb> C
Since it is pa, the capacitance value of the first polarization state 5 defined by the data “0” is larger than the capacitance value of the partial polarization state 6 defined by the data “1”. I will end up. Therefore, the differential reference signal Aref and the comparison reference signal Vref also need to be changed according to the state of the memory cell 1. Therefore, the differential reference cell 41 and the comparison reference cell 36, which are composed of the ferroelectric thin film 4 sandwiched by the same pair of electrodes as the memory cell 1, are used as reference cells. The output signals from these reference cells are proportional to the capacitance value C of the cell, so C = ε ₀ εr · S / d Eq. (3) ε ₀ : Dielectric constant of vacuum εr: Dielectric constant S: Area d: It can be changed by the area S rather than the thickness. Therefore,
A cell having an area corresponding to the differential reference signal Aref or the comparison reference signal Vref may be used. Thus memory cell 1
A cell of the same material having the same structure as the differential reference cell 41 and
By using the comparison reference cell 36, the change with temperature is
Since it is exactly the same as the memory cell 1, the differential reference signal Aref and the comparison reference signal Vref automatically change to proper values. Therefore, even if the state of the memory cell 20 changes depending on the temperature and the output signal thereof changes, it is possible to accurately determine "1" or "0".

As described above, the differential reference signal Aref
Is a signal generated from a differential reference cell 41 composed of the ferroelectric thin film 4 sandwiched between at least the lower electrode 3 and the upper electrode 2, and thus the differential amplifier circuit 40 that is accurate with respect to temperature changes. A differential amplification can be obtained, and a ferroelectric memory with a high read S / N can be realized.

Further, by using the comparison reference signal Vref as a signal generated from the comparison reference cell 36 composed of the ferroelectric thin film 4 sandwiched at least by the lower electrode 3 and the upper electrode 2, it is possible to prevent a change in temperature. Even accurate comparison and amplification circuit 3
Comparative amplification by 8 can be obtained, and a ferroelectric memory with a high read S / N can be realized.

Next, a ferroelectric memory as a fourth embodiment according to the present invention will be described with reference to FIGS.

FIG. 17 shows changes in the capacitance value with respect to the elapsed time after setting the polarization state of the memory cell 21 shown in FIG. When the first pulse 10 or the second pulse is applied and the polarization value is set to the first polarization state 5 or the partial polarization state 6, the capacitance value C of the memory cell 21 is left without any access. , The difference ΔC between the capacitance values of the two is maintained, but the capacitance value C decreases according to the elapsed time.

Therefore, similarly to the second embodiment described above, it is necessary to change the differential reference signal Aref from the differential reference cell 41 and the comparison reference signal Vref from the comparison reference cell 36 accordingly.

In this embodiment, the differential reference cell 41 is a single cell composed of the ferroelectric thin film 4 sandwiched by a pair of electrodes, as shown in the above-mentioned embodiments. Then, the polarization is set in synchronization with the write operation to the memory cell 21 in the ferroelectric cell matrix circuit 32. By doing so, the differential reference cell 41 is always polarized in synchronization with the memory cell 21, so that the change over time occurs in the same manner as the memory cell 21, and an appropriate differential reference signal Aref can always be generated. .

On the other hand, the comparison reference cell 36 is constructed as shown in FIG.

As shown in FIG. 18, the ferroelectric thin film 4 is sandwiched between a pair of electrodes (upper electrode 2 and lower electrode 3) facing each other and substantially orthogonal to each other to form a comparative reference cell matrix circuit 50. Form. The region where the striped electrodes of the comparison reference cell matrix circuit 50 intersect is referred to as a comparison reference cell 36. The upper electrode 2 and the lower electrode 3 may be either the third stripe electrode 51 or the fourth stripe electrode 52.

Ferroelectric cell matrix circuit 3 described above
Similar to 2, the termination resistance element 53 that is electrically switched to high resistance or low resistance is provided at at least one end of the stripe electrode. The switching in the termination resistance element is performed by the termination resistance element control circuit 54 in exactly the same manner as in the ferroelectric cell matrix circuit 32 described above. Further, a signal processing circuit 63 having the same configuration as the ferroelectric cell matrix circuit 32 is connected to the comparison reference input terminal 38b of the comparison amplification circuit 38. Comparison reference signal Vre
f is generated as follows.

In general, the capacitance value C is expressed by Eq. (3). Therefore, in the case of the same ferroelectric material, the same polarization state, and the same thickness, C = kS ... Eq. (4) k: It can be expressed as a proportional constant. The capacitance value C is proportional to the area S. Therefore,
The read signal is also proportional to S. In the memory cell 21 in the ferroelectric cell matrix circuit 32, the first polarization state 5 is defined as "0" and the partial polarization state 6 is defined as "1", and the respective capacitance values are C0, C1. Then, C0 <C1 as described above. The potentials V0 and V1 formed at the signal end of the comparison / amplification circuit 38 are equally subjected to linear signal processing such as differential amplification according to their capacitance values.
<V1.

As described above, there are several methods for generating the comparison reference signal Vref. First, using the relationship of Eq. (4), the comparison reference cell 36 with respect to the area Sf of the memory cell 21 is first used.
Area Sr is increased to set the polarization state of the comparative reference cell 36 to the first polarization state 5 defined in the memory cell 21. In the comparison reference signal Vref, the potential Vr at the input terminal 38b of the comparison reference signal of the comparison amplifier circuit 38 is a read signal (V0, V0).
For 1), it may be decided to be expressed by the following equation.

Vr = (V0 + V1) / 2 Therefore, assuming that the same signal amplification as on the memory cell 21 side is performed, the capacitance value Cr of the comparison reference cell 36 may be set as follows.

Cr = (C0 + C1) / 2 Cr defined in the above equation can be expressed as Cr = kr C0 with respect to C0, and therefore the first polarization state 5 which is the source of C0.
The area Sr of the comparative reference cell 36 in the first polarization state 5 exactly the same as the above is set as follows.

Sr = kr S0 By doing so, the capacitance value of the comparison reference cell 36 becomes Cr = Cr C0, and the comparison reference signal V input to the comparison amplification circuit 38.
r becomes Vr = krV0. This Vr is defined by the definition of kr as Vr = (V0 + V1) / 2 ... Eq. (5). Therefore, the comparison reference cell 36
By setting the area of s to kr S0 and setting the first polarization state 5, the comparison reference signal Vref can be formed.

On the contrary, the area of the comparison reference cell 36 may be determined by using the partial polarization state 6 of the data "1". In this case, as compared with the area of the memory cell 21, the same relationship as described above is derived, and the area is reduced by the coefficient. The area can be easily changed, and the region intersected by the third stripe electrode 51 or the fourth stripe electrode 52 is the comparison reference cell 36. Therefore, the width of the intersecting region formed by these stripe electrodes may be increased or decreased.

Next, the comparison reference cell 3 configured as described above.
The operation of No. 6 will be described.

The operation is similar to that of the first embodiment described above, but the polarization setting for setting the first polarization state 5 is performed by the comparison reference cell selection circuits 55a and 55b for all the third stripe electrodes 51 and the fourth stripes. The electrodes 52 select all comparison reference cells 36. And the changeover switch 64
To connect to the fourth pulse transmission circuit 59,
A fourth pulse is applied to all comparison reference cells 36.

This is a ferroelectric cell matrix circuit 3
As in the case of No. 2, since all comparison reference cells 36 are set to the same first polarization state 5, it is not necessary to consider the problem of crosstalk.

Next, the read operation of the entire memory using the comparison reference cell matrix circuit 59 to the comparison reference cell 36 will be described.

For reading, first, a desired memory cell 21 is selected by the memory cell selection circuits 15a and 15b, and then,
By switching the changeover switch 14, it is connected to the third pulse transmission circuit 13, a third pulse is applied to the memory cell 21, and its response is the low input impedance circuit 3.
Detect at 9. Then, while referring to the differential reference signal Aref, the differential amplification circuit 40 differentially amplifies the signal and sends it to the comparison amplification circuit 38. On the other hand, in the comparison reference cell 36, similarly, the desired comparison reference cell 36 is selected by the comparison reference cell selection circuits 55a and 55b, and is connected to the sixth pulse transmission circuit 61 by the changeover switch 64. The sixth pulse is applied to 36, and the comparison reference signal Vref is passed through at least the low input impedance circuit 62.
Is sent to the comparison reference input terminal 38b of the comparison amplification circuit 38. Here, from the comparison reference cell matrix circuit 50 to the comparison amplification circuit 38, the ferroelectric cell matrix circuit 3
The signal processing circuit 37 which is completely the same as that of 2 may be used. Also,
The fourth pulse and the sixth pulse may be exactly the same as the first pulse and the third pulse. That is, it is sufficient that the signal only from the selected comparison reference cell 36 flows to the signal line, and its value satisfies the magnitude of the comparison reference signal Vref.

In this way, the read signal and the comparative reference signal Vref are comparatively amplified by the comparative amplifying circuit 38 to discriminate between "1" and "0". At this time, in the comparison reference cell matrix circuit 50 as well as in the ferroelectric cell matrix circuit 32, at least one end of each stripe electrode is electrically terminated with a high resistance, a low resistance and a resistance value that can be changed. A plurality of resistance elements 53 are connected,
Similar to the first embodiment, the comparison reference signal Vref is predominantly created from the selected comparison reference cell 36.

There are the same number of memory cells 21 and comparison reference cells 36. Therefore, the memory cell 21 and the comparison reference cell 3
6 is made to correspond one-to-one, and when a certain memory cell 21 is selected at the time of reading, the comparison reference cell 36 for obtaining the signal for comparison and reference selects the corresponding comparison reference cell 36.

In writing, the same operation as the ferroelectric cell matrix circuit 32 side is also performed on the comparison reference cell matrix circuit 50 side. That is, at the same timing as the ferroelectric cell matrix circuit 32 side, all the third stripe electrodes 51 and the fourth stripe electrodes 52 are selected by the comparison reference cell selection circuits 55a and 55b, and the changeover switch 64 is switched to the fourth switch. Pulse transmission circuit 6
Connect to 1 and apply a fourth pulse to all comparison reference cells 36. Here, in the present embodiment, the magnitude of the fourth pulse is
It is assumed to be the same as the first pulse. Therefore, the same first pulse sending circuit 11 may be used instead, and the first pulse may be shunted instead of the fourth pulse.

Next, the ferroelectric cell matrix circuit 32.
Also in writing for setting the partial polarization state 6 on the side, −Vw / 3 is applied to the selected third stripe electrode 51 and 0 V is applied to the non-selected third stripe electrode 51 by the comparison reference cell selection circuits 55a and 55b. Comparison reference cell selection circuit 55
A fifth pulse having a magnitude of −2Vw / 3 is applied to the fourth stripe electrode 52 selected by a and 55b in synchronization with 0 and an unselected fourth stripe electrode 52 is applied in synchronization with the second pulse.

By this operation, the selected comparison reference cell 36 is "-Vw", and the non-selected comparison reference cell 36 is ". +-. Vw".
/ 3 ″ is applied. Similar to the fourth pulse, the fifth pulse may use the second pulse.

The comparison reference cell matrix circuit 5
On the 0 side, when the polarization state of the comparison reference cell 36 is used as the first polarization state 5, only the operation of applying the fourth pulse 56 is necessary.
The corresponding comparison reference cell 36 at the timing set to
Again, the fifth polarization for setting the first polarization state 5
Pulse is applied.

By such application, the memory cells 21 and 1
The polarization state is always set at the same time and the same number of times as that of the comparison reference cell 36 corresponding to 1: 1. Therefore, an appropriate comparison reference signal Vref is always obtained and it is always possible to accurately discriminate "1" or "0".

As described above, in this embodiment, the differential reference signal Aref is generated from the differential reference cell 41 composed of the ferroelectric thin film 4 sandwiched at least by the lower electrode 3 and the upper electrode 2. By using a signal, a differential reference signal Aref, which is appropriate for changes over time, can be obtained, and a ferroelectric memory capable of high S / N read can be realized.

Further, by making the comparison reference signal Vref a signal generated from the comparison reference cell 36 composed of the ferroelectric thin film 4 sandwiched at least by the lower electrode 3 and the upper electrode 2, it is possible to prevent a change with time. However, an appropriate differential reference signal Aref can be obtained, and a ferroelectric memory capable of high S / N reading can be realized.

Further, in the comparative reference cell 36, one of the pair of electrodes 3 and 2 is formed in a stripe shape, or a plurality of electrodes electrically connected to the electrodes are formed in a stripe shape.
The third stripe electrodes 51 arranged substantially in parallel and the other of the pair of electrodes are arranged in a stripe shape, or a plurality of electrodes electrically connected to the electrodes are arranged in a stripe shape in substantially parallel. The ferroelectric thin film 4 is sandwiched between electrodes including a fourth stripe electrode 52,
The striped electrode 51 and the fourth striped electrode 52 are substantially orthogonal to each other with the ferroelectric thin film 4 sandwiched between them, and the third and fourth
A comparison reference cell matrix, which is a region intersecting with the stripe electrodes 51 and 52, and further includes a terminating resistance element 53 which is electrically switched to a high resistance or a low resistance at each one end of the stripe electrodes 51 and 52. By configuring the circuit 50, the comparison reference signal Vref from the desired comparison reference cell 36 can be taken out with good S / N.

By connecting the comparison reference cell matrix circuit 50 to the comparison amplification circuit 38 at least through the low input impedance circuit 62, a high S / N ratio can be obtained.
Thus, the desired comparison reference signal Vref from the desired comparison reference cell 36 can be input to the comparison reference signal input terminal 38b of the comparison amplification circuit 38, and a ferroelectric memory capable of accurate read motion difference can be realized.

Further, the comparison reference cell matrix circuit 50 has the same number of comparison reference cells 36 as the ferroelectric cell matrix circuits 32 and the storage cells 21, and is arranged in the same arrangement as the storage cells 21. By doing so, memory cell 2
Since 1 and the comparison reference cell 36 can be made to correspond one-to-one and the polarization can be set the same number of times at the same timing, an appropriate comparison reference signal Vref can always be obtained even with a change over time. A ferroelectric memory capable of reading with S / N can be realized.

Next, with reference to FIG. 19, a ferroelectric memory as a fifth embodiment according to the present invention will be described.

In this embodiment, in the configuration of the fourth embodiment described above, the memory cell 21 and the low input impedance circuit 39 in the ferroelectric cell matrix circuit 32, and the comparison reference cell 36 in the comparison reference cell matrix circuit 50. And the low input impedance circuit 62 will be considered. Here, the electrical characteristics of each electrode or stripe electrode will be described. In particular, when the striped electrodes are formed on the semiconductor substrate, the electrical characteristics of the striped electrodes are multi-stage Rm as shown in FIG. 19 due to the resistance value Rm of the electrodes themselves and the stray capacitance Cm formed by the electrodes. , Cm can be equivalently expressed as a low-pass filter.

Therefore, since the length of the striped electrode changes depending on the relative position of the storage cell 21 or the comparison reference cell 36 with respect to the low input impedance circuits 39 and 62, the magnitude of the signal generated from the cells 21 and 36, The speed to reach and the waveform are different. Therefore, even if the characteristic of the comparison reference cell 36 is uniformly determined with respect to the read signal from the memory cell 21 and the signal processing circuit uniformly processes the read signal, all the memory cells 21 are always processed. However, the appropriate comparison reference signal Vref is not always obtained. Therefore, the comparison reference cell matrix circuit 50 is arranged in the same number with the same number of comparison reference cells 36 as the ferroelectric cell matrix circuit 32 and the number of the storage cells 21, and the storage cells 2 are arranged.
1 and the comparison reference cell 36 are made to correspond one-to-one including the existing location.

With such a configuration, the signals of the memory cell 21 and the comparison reference cell 36 having the same relative relationship to the low input impedance circuits 39 and 62 can be compared,
Since the signals are equally changed by the electrical characteristics of the striped electrodes, the signals of the memory cell 21 and the comparison reference cell 36 can maintain an appropriate relationship with each other.

As described above, according to this embodiment, at the time of reading, the comparison reference signal Vref is located at a position equivalent to the memory cell 21 in the ferroelectric cell matrix circuit 32 which generates the read signal. Since the signal is generated from the comparison reference cell 35 in the comparison reference cell matrix circuit 50, the signal is equally affected by the electrical characteristics of the striped electrodes, so that the signals of the memory cell 21 and the comparison reference cell 36 are the same. , Can maintain a proper relationship with each other. Therefore, a ferroelectric memory capable of stable and accurate reading can be realized.

Next, a ferroelectric memory as a sixth embodiment according to the present invention will be described with reference to FIG.

In this embodiment, in the above-described third embodiment, the comparison reference signal Vref sets the area of the comparison reference cells 36 appropriately, and all the comparison reference cells 36 are set to the first polarization state 5.
Alternatively, the partial polarization state 6 is set so that the following expression is satisfied. Further, assuming that the read signals of the storage states "1" and "0" of the storage cell 21 are V1 and V0, Vr becomes Vr = (V0 + V1) / 2, that is, an intermediate signal between V0 and V1. Is set.
In this case, the input difference ΔV between the read signal from the low input impedance circuit 39 that determines the S / N of the comparison and amplification circuit 38 and the comparison reference signal Vref from the comparison and reference cell 36.
Is ΔV = (V1-V0) / 2. In the present embodiment, the ferroelectric memory having the configuration exemplified in the third embodiment is provided as a memory capable of obtaining a double input difference ΔV.

The memory states of the memory cells 20 and the comparison reference cells 35 corresponding to each other on a one-to-one basis are made complementary (FIG. 20). That is, when the memory cell 20 is set to "1", the corresponding comparison reference cell 35 is "0". Conversely, when the memory cell 20 is "0", the corresponding comparison reference cell 35 is "1". ”
Write so that Writing has been sufficiently described in the above embodiment, and may be performed in the same manner. Thus, when the memory cell 20 is "1", the signal input to the signal input terminal 28 of the comparison / amplification circuit 26 becomes V1, and the comparison reference signal 33 and the comparison reference signal 33 input to the input terminals 32 and 28. Becomes V0. In the opposite case, V0,
And it becomes V1. Therefore, the input difference ΔV is ΔV = | V1−V0 |, which is twice as much as Eq. (1), and the S / N ratio is higher.
Good read operation.

As described above, in this embodiment, the comparison reference cell matrix circuit 50 has the same number of comparison reference cells 36 as the ferroelectric cell matrix circuits 32 and the memory cells 21, By arranging the memory cell 21 and the comparison reference cell 36 in a one-to-one correspondence with the same array as the cell 21, the polarization state of the comparison reference cell 36 is always complementary to the corresponding memory cell 21. And the input difference ΔV can be doubled,
It is possible to realize a ferroelectric memory capable of reading with a high S / N.

A ferroelectric memory as a seventh embodiment according to the present invention will be described with reference to FIGS.

In the first embodiment described above, the termination resistance element 34
Terminate the electrode with a low input impedance element, or
By receiving the read signal in the circuit, it was possible to read at high S / N without crosstalk.

In this embodiment, a read circuit 17 which can perform a read operation with a higher S / N is proposed. The conditions of the ferroelectric cell matrix circuit 32 proposed in the present invention have been described in the first embodiment. That is, if the capacitance value of the memory cell 21 made of the ferroelectric thin film 4 is C, the resistance value of the termination resistance element 34 is R, and the frequency of the applied voltage is ω, then Eq.
(1) Satisfaction was a necessary condition for preventing crosstalk in the first embodiment. Read-out is preferably performed with a single rectangular pulse in consideration of the access speed to the memory. But a single pulse
Since it has many frequency components, it is impossible to completely satisfy Eq. (1).

Therefore, when reading is performed with a single rectangular pulse, the output of the low input impedance element having the amplification factor of 1 is qualitatively shown in FIG.
q. (1) is no longer satisfied, and becomes the same as the output Ifloat from the simple matrix circuit of the ferroelectric cell when not terminated by the termination resistance element 34. That is, the output includes all signals (noise) from the non-selected cells Cus.

Then, as time passes, for example, as shown in FIG.
1, at time t2, Eq. (1) is satisfied, the potential of each node is determined by the terminating resistance element 34 as described in the first embodiment, and unselected cells are generated. The signal (noise) that flows flows to GND through the termination resistance element 34.

Therefore, at time t2, the signal Io is only from the selected cell Cs, so that high S / N can be read.

Therefore, as shown in FIG. 22, the signal processing circuit 37 is provided with a signal line connected to GND or a control switch 44 for disconnecting the signal line. Until time t2, the control switch 44 is turned on and the signal line is GN.
Ground to D level and drop the output to GND. Eq. (1)
Is turned off at a time when, for example, t2 is satisfied. With such a configuration, only the signal from the selected cell Cs reaches the comparison / amplification circuit 38. This on / off control may be performed at any timing, but here, it is performed via the delay circuit 45 by using a signal which is used in some memory or is generated. In addition, the trigger may use the third pulse applied for reading, or may be an intentionally created reference. Here, using the output signal, the peak Ifloat that occurs in the initial stage of the output signal is used as a trigger to delay a certain time Δt by the delay circuit 45 to control the control switch 44. In this way, the control signal 44 can be accurately driven by using the output signal itself as a trigger, so that the reading with good S / N can be performed.

As described above, according to this embodiment, the signal processing circuit 25 is connected to the signal line connected to GND, or
By providing the control switch 44 for disconnection, low S /
Since the N read signal area is dropped to GND and read can be performed in the high S / N read signal area, a ferroelectric memory capable of high S / N read operation can be realized.

Further, the control switch 44 is replaced with the delay circuit 4
By driving at 5, the control switch 44 can be automatically controlled by using a certain reference signal as a trigger.

Further, by driving the control switch 44 by using the read signal as a trigger, it is not necessary to provide a reference signal as a new trigger, and moreover, by using the read signal itself for reading as a trigger, it is possible to achieve accurate reading. Since the control switch 44 can be controlled at timing, accurate reading can be performed.

As another modification, FIG. 27 (a)
In place of the control switch 44, as shown in FIG.
Inside, you may provide suitably. Here, like the control switch 44, it is provided between the low input impedance element and the differential amplifier circuit 40. As the simplest example of this low-pass filter 50, as shown in FIG. 27 (b), by configuring with a resistance element Rq and a capacitance element Cq, fq = 1 / (2πCq Rq) It becomes difficult to pass a waveform having a frequency component, and a waveform having a frequency component of fq or less is likely to pass.

Therefore, the peak-shaped signal corresponding to the rising edge of the third pulse composed of high-frequency components is removed, and the signal component satisfying Eq. (1) reaches the comparison and amplification circuit 38 predominantly. , Read with better S / N can be performed.

Next, a ferroelectric memory as an eighth embodiment according to the present invention will be described with reference to FIGS. The present embodiment is a ferroelectric memory having a high read S / N, no crosstalk, and nondestructive read.

At the time of reading this ferroelectric memory, if a desired cell is selected and a third pulse of Vr is applied to the selected cell, the voltage applied to each cell is as follows.

[0173]

[Table 1]

A voltage substantially equal to that of the selected cell Cs 21 is applied to the non-selected cell Cy 22. Since the magnitude of the third pulse is set to 0.3 Vc or less from the requirement that polarization is not destroyed, the voltage applied to Cy 22 is at most 0.
It is 3 Vc.

It has been described with reference to FIG. 9 that at this voltage value, the polarization change, that is, the destruction amount is 10% or less even if the pulse is applied at least 10 ⁹ times. Here, a method of further reducing the amount of polarization destruction of the non-selected cell will be exemplified.

As shown in FIG. 23, the bias pulse 64 is applied to the node b connecting Cy 22 and Cxy 43 at the time of reading. The characteristics of the bias pulse 64 will be described. The magnitude of the bias pulse 64 is Vb. In order to perform the read operation here, as in the above-described embodiment,
It is assumed that a desired memory cell 21 is selected and a third pulse of magnitude Vr is applied. At this time, the bias pulse 64 is applied in synchronization with the third pulse. Then, the voltage dropped in the non-selected cell Cy 22 decreases. Because the bias pulse 64 is forcibly applied to the node b, for the reason explained in the first embodiment, the voltage drop of Vr in the non-selected cells is caused by the non-selected cells Cy 22 and C.
It is distributed with xy47 as the following equation.

Vr = Vy + Vxy Vy: voltage applied to Vy: Cy Vxy: voltage applied to Cxy Here, since Vxy = Vb, Vy <Vr. For example, if Vb is determined so that Vy = Vxy, the voltage applied to the non-selected cell Cy22 can be reduced to approximately Vs / 2, and conversely Cxy4.
The applied voltage to 3 is increased from almost "0" to approximately Vs / 2, but the change in polarization with respect to the applied voltage is
However, the same applies to Cxy43, and there is no problem even if a voltage is applied to Cxy43. Rather, the non-destructive property of polarization is remarkably improved by reducing the applied voltage to the non-selected cells by half. Also, by applying a voltage to Cxy43, Cxy
A signal (noise) is generated from 43, but for the same reason explained in the first embodiment, it flows out to GND via R and is hardly mixed into the output line.

Further, as described in the first embodiment, the potential at the node C is almost 0, so that there is almost no signal generation from Cx 23. To effectively apply the bias pulse 66, as shown in FIG. 24, the bias pulse 66 is applied before the application of the third pulse, and is lowered to the GND level after the fall of the third pulse. It is impossible to perform the rising time tr and the falling time tb at exactly the same timing with all the storage cells 21 being symmetrical.

Therefore, it is preferable that the bias pulse 66 rise earlier and fall later than the third pulse. With this timing, the voltage applied to the non-selected cell does not exceed Vr / 2, and the performance against the breakdown of the polarization of the non-selected cell is improved.

Further, if the driving method described in this embodiment is used, this ΔS can be doubled. The magnitude of the third pulse is 0.6 Vc, and the magnitude of the bias pulse 66 is 0.3 Vc. With this setting, .DELTA.S is at least doubled as compared with the case of driving at 0.3 Vc, and the read S / N is proportionally improved. However, a new problem of polarization breakdown arises.

That is, since only 0.3 Vc is applied to the non-selected cell, 0.6 Vc is applied although the polarization does not change even if the pulse is applied at least 10 ⁹ times as described several times. It is clear from FIG. 9 that the polarization of the selected cell changes.

However, as shown in FIG. 25, in the case of applying the bipolar pulse, it is experimentally shown that the polarization state after the application pulse is removed up to about Vc maintains the state before the pulse application. I chose Considering the correspondence with FIG. 9, it is considered that the polarization is not destroyed but is restored to the original state by applying a pulse of one cycle of positive and negative. Maintaining state is very important.

Therefore, if the third pulse of the opposite polarity is applied to the selected cell after the read operation is completed, the polarization state of the selected cell can be returned to the original state. At this time, according to the ⅓ drive described in the writing, the applied voltage to the non-selected cell is −0.2 Vc, so that the polarization of the non-selected cell does not change at all.

Therefore, by setting the magnitude of the third pulse to 0.6 Vc and the magnitude of the bias pulse 66 to 0.3 Vc as described above, a double signal difference can be obtained and a higher S A ferroelectric memory that can be read with / N can be realized. Furthermore, non-destructive reading is also possible by writing back the polarization state of the selected cell.

As described above, according to the present embodiment, when the stored information is read from the selected memory cell 21 by applying the third pulse, the ferroelectric cell matrix circuit 32 is used.
Applied voltage Vs (2 to the selected memory cell Cs 21 in the
πfst + ts), the applied voltage Vy to the non-selected ferroelectric cell Cy 22 connected to the selected stripe electrode on the input side
(2πfyt + ty), applied voltage Vxy (2πfxyt + txy) to the non-selected cells Cxy43 other than the non-selected cells Cx23 connected to the selected output-side stripe electrode of Cy22.
The bias pulse 66 is set to Cy 2 so that the relation of Vs = Vy + Vxy is satisfied.
The voltage applied to the non-selected cell can be reduced by applying the voltage to the connection node 65 of 2 and the Cxy 43 to perform reading, and the breakdown of the polarization of the non-selected cell can be further reduced.

By applying the bias pulse 66 whose magnitude relationship between the applied voltage Vy and the applied voltage Vxy is Vs = 2Vy = 2Vxy, the applied voltage to the non-selected cells is reduced to 1/2. Therefore, the breakdown of polarization of the non-selected cells can be further reduced.

Furthermore, the frequency fr of the third pulse and the frequency fb of the fourth pulse 56 are such that fr ≧ fb, and the rising time tr of the third pulse and the rising time tb of the bias pulse 66 are By setting tr ≧ tb, it is possible to prevent the third pulse from being applied to the non-selected cell with the same magnitude, so that the voltage applied to the non-selected cell can be reliably and stably reduced. Therefore, the breakdown of polarization of the non-selected cells can be further reduced.

Next, referring to FIG. 26, a ferroelectric memory as a ninth embodiment of the present invention will be described.

The memory cell of this ferroelectric memory has a structure similar to that shown in FIG. 8, and is sandwiched between a pair of lower electrode 3 and upper electrode 2 facing each other and these lower electrode 3 and upper electrode 2. The first pulse shown in FIG. 1 is applied to the memory cell 21, which is composed of the ferroelectric thin film 4 thus formed, to bring it into the first polarization state 5. Then, the second pulse is applied to bring about the partial polarization state 6, and the capacitance value Cp is evaluated in this state.

The magnitude of the first pulse is set to -5V and the second pulse is set to
The measurement of Cp using Vw as a parameter and the pulse size of 1 has already been described with reference to FIG. However, although the cause is unknown, immediately after the memory cell 21 is formed, the polarization state of the ferroelectric thin film 4 in the cell is indefinite, and the electrical characteristics at the interface with the electrode are also unstable. Alternatively, in the memory cell 21 to which no pulse is applied immediately after the formation, as shown in FIG. 26, in the region where Vw is small, the capacitance value C is small.
p indicates a maximum.

From the capacitance value Cpo at Vw = 0V, Cp decreases as Vw increases, and Vw further increases.
Conversely, Cp increases. Then, as described above, when Vc and Vw are almost equal to the coercive voltage Vc of the ferroelectric thin film 4, Cp shows the maximum value at Vw, and thereafter Cp decreases as Vw increases. .

Cpo at Vw = 0 is a capacitance value in the first polarization state 5 which is defined as one storage state in the above embodiment, and is an important characteristic for this memory. As described above, in order to maximize the read S / N of the memory, it is necessary to maximize the difference between the capacitance values of the two storage states. By setting one memory state as the first memory state 5 and the other memory state as the partially polarized state 6 in which Vc and Vw are made almost equal,
As described above, the above requirements can be satisfied.

However, in FIG. 26, the first value at Vw = 0
Cpo in memory state 5 is not the minimum value, and Vw is 0
When the value Vwm is slightly larger, Cp shows the minimum value. If this characteristic is stable, instead of the first polarization state 5 defined previously, the partial polarization state 6 produced at Vw = Vwm,
Data "0" may be defined as one of the storage states. However, as shown in FIGS. 3 and 26, the behavior is different near Vw = 0. That is, FIG. 26 shows that the state is not stable.

On the other hand, it has been confirmed that the characteristics shown in FIG. 3 exhibit the same characteristics no matter how many times they are measured, and they are very stable. Therefore, for example, in the case of Vc of 2 to 2 is applied to the memory cell 21 to which no pulse is applied immediately after the production showing the characteristics of FIG.
A 2.5-fold aging pulse is applied for one cycle, and then the first pulse 10 having a magnitude of −5 V is applied for the first time.
When the polarization state is set to 5, the Cpo shown in FIG. 5 is exhibited, and the Cpo becomes very stable with respect to subsequent pulse application.

Although the magnitude of this aging pulse is the magnitude of the first pulse 10 having the maximum voltage value during the operation of the ferroelectric memory of this embodiment, the same effect can be obtained even if the magnitude is larger. It is confirmed that it can be obtained. On the contrary, when the size is small, the effect is small depending on the size, or when the size is less than Vc, almost no effect is observed.

As described above, according to the ferroelectric memory of this embodiment, after the ferroelectric memory is manufactured, the aging pulse is applied to all the memory cells and all the reference cells for at least one cycle, A stable memory operation can be realized.

Furthermore, by setting the magnitude of the aging pulse to be equal to or larger than that of the first pulse, the instability of Cpo can be effectively eliminated and a stable memory operation can be realized.

Although the description has been made on the basis of the above embodiments, the present invention also includes the following inventions.

(1) A first pulse having a magnitude Ve greater than or equal to the coercive voltage Vc of the ferroelectric thin film is applied to the ferroelectric thin film sandwiched by a pair of opposing upper and lower electrodes, The polarization state is set to either one of the two saturation polarization states, and the polarization state is set to the first polarization state,
The first polarization state and the ferroelectric thin film in the first polarization state are applied with a second pulse having a magnitude Vw having a polarity opposite to that of the first pulse, and the first polarization state is applied. Two memory states are constituted by a partially polarized state in which a domain having a state polarization and a domain having a polarization in the opposite direction are mixed, and the memory state is applied with a third pulse having a magnitude Vr. In a ferroelectric memory for reading by reading, one of the pair of electrodes is formed in a stripe shape, or a plurality of electrodes electrically connected to the electrodes are arranged in a stripe shape, and a first stripe electrode is arranged in parallel. The other of the pair of electrodes is in a stripe shape, or a plurality of electrodes electrically connected to the electrodes are sandwiched by an electrode composed of a plurality of stripe-shaped electrodes and second stripe electrodes arranged substantially in parallel. Composed of dielectric thin film The first striped electrode and the second striped electrode are substantially orthogonal to each other with the ferroelectric thin film sandwiched therebetween, and a region where the first striped electrode and the second striped electrode intersect each other serves as a memory cell. Ferroelectric cell matrix circuit having a termination resistance element electrically switched to high resistance or low resistance at each end, a signal processing circuit including at least a low input impedance circuit and a differential amplification circuit, and a comparison amplification circuit A ferroelectric memory comprising a read circuit in combination with.

In such a ferroelectric memory, the polarization setting for setting the first polarization state by applying the first pulse is such that all the first stripe electrodes are selected by the selection circuit and at the same time, the second stripe electrodes are selected. Then, all are selected by the selection circuit, and the changeover switch is switched to the side of the first pulse sending circuit, and, for example, the first pulse having a magnitude 2.5 times Vc of the ferroelectric thin film is applied to all the memory cells.

All memory cells are selected at once and the same first
Therefore, it is not necessary to consider the problem such as crosstalk, because the polarization state is set to. By this operation, all memory cells are set to data "0". Writing to set the partial polarization state corresponding to data "1" is performed as follows by selecting a desired memory cell to be set to "1" and switching the changeover switch to the second pulse sending circuit side.

Vw / 3 for the selected first stripe electrode of the X-line, 0V for the non-selected first stripe electrode, Y
A voltage of 0 V is applied to the selected second stripe electrode of the line, and a voltage of 2 Vw / 3 is applied to the non-selected second stripe electrode. By doing so, the selected memory cell C
Vw is applied to s and Vw / 3 (absolute value) is applied to the non-selected memory cell Cus.

Therefore, Vw is applied to the non-selected memory cell Cus.
Only a small voltage of / 3 is applied. Hereinafter, this driving method is referred to as a 1/3 driving method. A partially polarized state can be produced by setting the magnitude of Vw to 0.3 to 2 times Vc with respect to Vc of the ferroelectric thin film. This operation is performed sequentially, and among all the memory cells, the memory cell to be set to the partially polarized state is set to the partially polarized state, whereby the write operation is completed.

For reading, a third pulse of magnitude Vr is applied and the response is detected. At this time, the termination resistance elements connected to the ends of the input line and the output line have high resistance Roff, and the termination resistance elements connected to the other lines have low resistance Ron. By doing so, a pulse having substantially the same magnitude as the third pulse is applied to the memory cell Cy connected to the input line, but to the other non-selected memory cells indicated by Cxy and Cx. , Almost no voltage is applied. The noise from the non-selected memory cells Cy and Cxy is R
It flows into GND via on and does not flow into the output line. Further, since the output signal is received by the low input impedance circuit, the magnitude of the applied third pulse is efficiently applied to the selected storage cell Cs, and the signal from the selected storage cell Cs has the impedance. Since it efficiently flows into a low input impedance circuit having a low S, the reading with a good S / N becomes possible. The magnitude of the third pulse is 0.3 times or less of Vc of the ferroelectric thin film. This applied voltage does not change the capacitance value as well as the polarization state of the ferroelectric thin film even if a pulse is applied at least 10 ⁹ times.
That is, it does not change the memory state. The output from the low input impedance circuit is differentially amplified by the differential amplifier circuit and further compared and amplified by the comparison amplifier circuit to determine "1" or "0", and the read operation is completed.

Therefore, there is no interference (crosstalk) with the non-selected storage cell, and the high S
It is possible to realize a large-capacity ferroelectric memory that is / N and does not destroy the memory state of the memory cell.

(2) In the ferroelectric memory according to (1), the output of the low input impedance circuit is directly or indirectly input to one signal input terminal of the differential amplifier circuit, The differential reference signal is input to the other differential reference signal input terminal, and the output of the differential amplification circuit is directly or alternatively input to one read signal input terminal of the comparison amplification circuit. , Indirectly entered,
A ferroelectric memory in which a comparison reference signal is input to the other comparison reference signal input terminal.

In such a ferroelectric memory, the differential amplifier circuit is arranged in the subsequent stage of the low input impedance circuit, the output Ao of the low input impedance circuit is connected to one signal input terminal, and the other is compared. A at the differential reference signal input end
Ref is flowed in and differentially amplified. This output signal Vs is further connected to the read signal input terminal of the comparison amplifier circuit and compared with the comparison reference signal Vref connected to the other comparison reference signal input terminal. If Vs> Vref, the read signal The input end is latched to approximately the power supply voltage Vdd, and the other comparison reference signal input end is at the GND level. Reverse Vs
In the case of <Vref, the opposite is true, and after the operation of the comparison and amplification circuit, the read signal input terminal can determine "1" or "0" depending on the Vdd level or the GND level.

Therefore, it is possible to realize a ferroelectric memory capable of reading at high S / N.

(3) In the ferroelectric memory according to (1) or (2), the differential reference signal is the minimum value Amin of the signal output according to the storage state of the ferroelectric cell matrix circuit. A ferroelectric memory characterized by:

In such a ferroelectric memory, the read signal is differentially amplified using the minimum value Amin of the output signal of the ferroelectric cell matrix circuit as the magnitude of the differential reference signal.

Therefore, the output signal can be amplified to the maximum extent by the differential amplifier circuit, stable and accurate operation of the comparison and amplification circuit can be realized, and a ferroelectric memory capable of accurate read operation can be realized.

(4) In the ferroelectric memory according to (1) or (2), the differential reference signal is a signal output according to the storage state of the ferroelectric cell matrix circuit Is a value between a minimum output value Am1 when the selected cell is "1" and a maximum output value Am2 when the selected cell is "0".

In such a ferroelectric memory, in the signal output according to the storage state of the ferroelectric cell matrix circuit, the minimum output value Am1 when the selected cell Cs is "1" is selected cell Cs. Is differentially amplified as a value between the maximum output value Am2 and the maximum output value Am2.

Therefore, since the base portion of the read signal can be reliably removed, the amplification degree α can be maximized within the power supply voltage, and the differential amplification by the stable differential amplification circuit and the accurate comparison amplification circuit can be performed. Comparative amplification is realized.

(5) In the ferroelectric memory according to any one of (1) to (4), the differential reference signal is a differential reference including the ferroelectric thin film sandwiched at least by a lower electrode and an upper electrode. A ferroelectric memory characterized by being a signal generated from a cell.

In such a ferroelectric memory, a ferroelectric thin film sandwiched by a pair of opposing upper and lower electrodes is used as a differential reference cell to generate a differential reference signal by applying a voltage.

Therefore, it is possible to obtain accurate differential amplification by the differential amplifier circuit even with respect to temperature changes, and to realize a ferroelectric memory with high read S / N. Further, it is possible to obtain a ferroelectric memory capable of obtaining an appropriate differential reference signal even with a change over time and capable of reading with a high S / N.

(6) In the ferroelectric memory according to any one of (1) to (5), the comparative reference signal is from a comparative reference cell composed of the ferroelectric thin film sandwiched at least by a lower electrode and an upper electrode. A ferroelectric memory characterized in that it is a generated signal.

In such a ferroelectric memory, a ferroelectric thin film sandwiched by a pair of opposing upper and lower electrodes is used as a comparison reference cell to generate a comparison reference signal by applying a voltage.

Therefore, it is possible to obtain the comparative amplification with the accurate comparing and amplifying circuit even with respect to the temperature change, and to realize the ferroelectric memory with a high read S / N ratio. Further, it is possible to obtain a ferroelectric memory capable of obtaining an appropriate differential reference signal even with a change over time and capable of reading with a high S / N.

(7) In the ferroelectric memory as described in (6) above, in the comparative reference cell, one of the pair of upper and lower electrodes has a stripe shape, or an electrode electrically connected to the electrode has a stripe shape. A plurality of third stripe electrodes arranged substantially parallel to each other and the other of the pair of electrodes in a stripe shape, or a plurality of electrodes electrically connected to the electrodes in a stripe shape, substantially parallel to each other. Arranged in 4th
A ferroelectric thin film sandwiched between electrodes composed of a stripe electrode, and the third stripe electrode and the fourth stripe electrode are substantially orthogonal to each other with the ferroelectric thin film sandwiched therebetween,
A comparison reference cell matrix circuit which is an intersection region with the third and fourth stripe electrodes and further has a terminal resistance element which is electrically switched to a high resistance or a low resistance at each one end of the stripe electrode. A ferroelectric memory comprising:

Such a ferroelectric memory is described in (1) above.
It has the same operation as the ferroelectric memory described, and the comparison reference signal from the desired comparison reference cell can be taken out with good S / N.

(8) In the ferroelectric memory according to (6) or (7), the comparison reference cell matrix circuit is connected to the comparison amplification circuit via at least a low input impedance circuit. And ferroelectric memory. Such a ferroelectric memory has the same operation as the ferroelectric memory described in (1) above, and has a high S / N ratio, and outputs a comparison reference signal from a desired comparison reference cell to a comparison reference signal input terminal of a comparison amplifier circuit. It is possible to realize a ferroelectric memory that can be input to the memory and can accurately read out the difference.

(9) In the ferroelectric memory according to (6) or (7), the comparison reference cell matrix circuit has the same number of comparison reference cells as the ferroelectric cell matrix circuit and the number of memory cells. And has the same arrangement as the memory cells.

For reading in such a ferroelectric memory, a desired memory cell is selected, a third pulse is applied, and the response is detected by a low input impedance circuit,
The signal is differentially amplified while referring to the differential reference signal and input to the comparison and amplification circuit. On the other hand, the comparison reference cell is exactly the same,
A desired comparison reference cell is selected, the same third pulse is applied, and the comparison reference signal is connected to the comparison reference input terminal of the comparison amplifier circuit through at least the low input impedance circuit. Next, at the time of writing to set the partially polarized state on the ferroelectric cell matrix circuit side, the selected third
A fifth pulse having a magnitude of -Vw / 3 is applied to the stripe electrode, 0V is applied to the non-selected third stripe electrode, 0 is applied to the selected fourth stripe electrode, and a non-selected fourth stripe electrode is applied with a second pulse of -2Vw / 3. By applying in synchronism with the 2 pulse, -Vw is applied to the selected comparison reference cell and ± Vw / 3 is applied to the non-selected comparison reference cell. In this way, the polarization state of the comparison reference cell 35, which corresponds to the storage cell on a one-to-one basis, is always set at the same time and the same number of times.

As described above, in the ferroelectric memory, the storage cells and the comparison reference cells can be made to correspond one to one, and the polarization can be set the same number of times at the same timing. An appropriate comparison reference signal can always be obtained, and a ferroelectric memory capable of reading at high S / N can be realized. In addition, the polarization state of the comparison reference cell can always be made complementary to the corresponding memory cell, and the input difference ΔV in the previous period can be doubled, and the high S
It is possible to realize a ferroelectric memory capable of a read motion difference at / N.

(10) In the ferroelectric memory as described in (9) above, when reading, the comparison reference signal is located at a position equivalent to a memory cell in the ferroelectric cell matrix circuit which generates a read signal. A method of driving a ferroelectric memory, wherein the signal is generated from a comparison reference cell in the comparison reference cell matrix circuit.

The driving method of such a ferroelectric memory is as follows.
The comparison reference cell matrix circuit has the same number of comparison reference cells as the number of ferroelectric cell matrix circuits and memory cells,
The memory cells and the comparison reference cells are arranged in the same arrangement, including the existing portions, in a one-to-one correspondence, and the signals of the storage cells and the comparison reference cells having the same relative relationship to the low input impedance circuit are compared.

Therefore, the signals of the memory cell and the comparison reference cell are equally affected by the electrical characteristics of the striped electrodes, so that the signals of the memory cell and the comparison reference cell can maintain an appropriate relationship with each other. Therefore, a ferroelectric memory capable of stable and accurate reading can be realized. In addition, the polarization state of the comparison reference cell can always be made complementary to the corresponding memory cell, and the input difference Δ
V can be doubled, and a ferroelectric memory capable of read operation with high S / N can be realized.

(11) In the ferroelectric memory according to (1), the signal processing circuit is provided with a control switch for connecting or disconnecting a signal line to GND. .

In such a ferroelectric memory, a control switch for connecting or disconnecting the signal line to GND is provided in the signal processing circuit. And the output signal is high S / N
The control switch is turned on to ground the signal line to the GND level, the output is dropped to GND, and the output is turned off at the time t2 when the output signal becomes high S / N.

Therefore, the read signal area of S / N is G
It is possible to realize a ferroelectric memory capable of performing a read operation with a high S / N since it can be read in the read signal area with a high S / N after being dropped to ND.

(12) In the ferroelectric memory as described in (11) above, the control switch is driven by a delay circuit.

In such a ferroelectric memory, on / off control is performed via a delay circuit using a signal which is being used or is generated in this memory as a trigger. Therefore, the control switch can be automatically controlled by using a certain reference signal as a trigger.

(13) In the ferroelectric memory according to (11) or (12), the control switch is driven by using a read signal as a trigger.

The driving method of such a ferroelectric memory is as follows.
The peak generated in the initial stage of the output signal is used as a trigger to delay a certain time Δt from the peak by a delay circuit to control the control switch.

Therefore, by driving the read signal as a trigger, it is not necessary to provide a reference signal as a new trigger, and by using the read signal itself for reading as a trigger, the control switch can be operated at accurate timing. Since control is possible, accurate reading can be performed.

(14) The ferroelectric memory as described in (1) above, wherein the signal processing circuit includes a low-pass filter circuit.

Such a ferroelectric memory has a low S corresponding to the rising edge of the third pulse composed of high frequency components.
The peak-like signal of / N is removed, and the high S / N signal component is predominantly allowed to flow into the comparison / amplification circuit, so that good S / N reading can be performed. (15) In the ferroelectric memory according to any one of (1) to (14) above, when reading stored information by applying a third pulse, the selected ferroelectric in the ferroelectric cell matrix circuit is selected. Applied voltage Vs (2πfst +) to body cell Cs
ts), the applied voltage Vy (2πfyt + t to the non-selected ferroelectric cell Cy connected to the selected input-side stripe electrode
y), and the magnitude of the applied voltage Vxy (2πfxyt + txy) to the non-selected cells Cxy other than the non-selected cells Cx connected to the selected output-side stripe electrode is Vs = Vy + Vxy. So that the bias pulse is set to Cy and Cxy
A method for driving a ferroelectric memory, characterized in that the voltage is applied to the connection node to read.

Such a ferroelectric memory has a low S corresponding to the rising edge of the third pulse composed of high frequency components.
The peak-like signal of / N is removed, and the high S / N signal component reaches the comparison amplification circuit predominantly, so that good S / N reading can be performed. A bias pulse is applied to the junction node of Cy and Cxy in synchronization with the third pulse.

Therefore, the voltage applied to the non-selected cells can be reduced, and the breakdown of the polarization of the non-selected cells can be further reduced.

(16) In the ferroelectric memory according to (15), a bias pulse having a magnitude relationship between the applied voltage Vy and the applied voltage Vxy is Vs = 2Vy + 2Vxy is applied. A method for driving a characteristic ferroelectric memory. In such a ferroelectric memory driving method, a bias pulse having a magnitude Vb is applied to the junction node of Cy and Cxy in synchronization with the third pulse so that Vy = Vxy.

Therefore, the voltage applied to the non-selected cells is halved.
The breakdown of polarization of non-selected cells can be reduced to
It can be further reduced.

(17) In the ferroelectric memory according to (15) or (16), the frequency f of the third pulse is
r and the frequency fb of the fourth pulse are fr ≧ fb, and the rising time tr of the third pulse and the rising time tb of the bias pulse are tr ≧ tb. Driving method for dielectric memory.

The driving method of such a ferroelectric memory is as follows.
The frequency fr of the third pulse and the frequency fb of the bias pulse 48 are fr ≧ fb, and the rising time tr of the third pulse and the rising time tb of the bias pulse are tr ≧ tb, Cys the bias pulse in synchronism with the pulse of 3
And Cxy to the junction node.

Therefore, even if the third pulse is momentary,
Since it can be prevented from being applied to the non-selected cells with the same size, the voltage applied to the non-selected cells can be reliably and stably applied.
It is possible to reduce the breakdown of polarization of non-selected cells.

(18) In the ferroelectric memory according to any one of (1) to (17), after the ferroelectric memory is manufactured, all the memory cells, all the differential reference cells, and the comparison reference cells are large. A method of manufacturing a ferroelectric memory, characterized in that an aging pulse having a height Vg is applied for at least one cycle or more.

The manufacturing method of such a ferroelectric memory is as follows.
One cycle of aging pulse is applied to the memory cell to which no pulse has been applied immediately after fabrication.

Therefore, the ferroelectric memory performs stable memory operation.

(19) In the method for manufacturing a ferroelectric memory as described in (18) above, the magnitude of the aging pulse is the same as or larger than that of the first pulse. Memory manufacturing method.

The manufacturing method of such a ferroelectric memory is
An aging pulse having the same magnitude as or larger than the first pulse is applied to the memory cell to which no pulse has been applied immediately after the production for one cycle.

Therefore, the instability of Cpo can be effectively eliminated, and a ferroelectric memory capable of stable memory operation can be provided.

[0253]

As described in detail above, according to the present invention, it is possible to provide a non-destructive readable ferroelectric memory which can be manufactured with high integration and low cost, and its driving method and manufacturing method.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a ferroelectric memory as a first embodiment according to the present invention.

FIG. 2 is a diagram showing a hysteresis characteristic of a memory cell (ferroelectric thin film) of a ferroelectric memory.

FIG. 3 is a diagram showing a relationship between a polarization breakdown amount ΔP and a magnitude Va of an applied pulse when a single pulse is applied to a ferroelectric thin film.

FIG. 4 is a diagram showing a configuration of a basic memory device.

FIG. 5 is a diagram showing a relationship between a capacitance value Cp of a ferroelectric thin film PZT and a partial polarization manufacturing voltage Vw.

FIG. 6 is a diagram showing a configuration example of a ferroelectric memory in which memory cells are arranged in a simple matrix.

7A is a diagram showing a configuration example of a simple matrix, and FIG. 7B is a diagram showing voltages applied to selected and non-selected memory cells.

FIG. 8 is a diagram showing an example of a configuration of a memory cell of a ferroelectric memory.

9A and 9B are diagrams showing nondestructive characteristics of polarization.

FIG. 10 is a diagram showing an example of a termination resistance element.

11A is a diagram showing a configuration of a ferroelectric cell matrix circuit, and FIG. 11B is a diagram showing an equivalent circuit thereof.

FIG. 12 is a diagram showing an equivalent circuit focusing on a non-selected cell.

FIG. 13 is a diagram showing a configuration example of a read circuit in the ferroelectric memory according to the second embodiment of the present invention.

FIG. 14 is a diagram showing the magnitude of a differential reference signal in the second embodiment.

FIG. 15 is a diagram showing the magnitude of a comparison reference signal in the second embodiment.

FIG. 16 is a diagram showing a relationship of temperature change of Cp-Vw characteristics of a ferroelectric memory as a third embodiment according to the present invention.

FIG. 17 is a diagram showing changes with time of Cp of a ferroelectric memory as a fourth embodiment according to the present invention.

FIG. 18 is a diagram showing a configuration of a comparison reference cell in the ferroelectric memory according to the fourth example.

FIG. 19 is a diagram showing an electrical equivalent circuit of a striped electrode in a ferroelectric memory as a fifth embodiment according to the present invention.

FIG. 20 is a diagram showing complementary data in the ferroelectric memory as the sixth embodiment according to the present invention.

FIG. 21 is a diagram showing the output characteristic of the low input impedance circuit in the ferroelectric memory as the seventh embodiment according to the present invention.

FIG. 22 is a diagram showing a connection configuration of control switches in the ferroelectric memory of the seventh example.

FIG. 23 is a diagram showing an equalizing circuit for applying a bias pulse in a ferroelectric memory as an eighth embodiment according to the present invention.

FIG. 24 is a diagram showing a Cp-Vw characteristic of a memory cell immediately after manufacturing in an eighth example according to the present invention.

FIG. 25 is a diagram showing a non-destructive characteristic of polarization when a bipolar pulse is applied in an eighth example according to the present invention.

FIG. 26 is a diagram showing a relationship between a bias pulse and a third pulse in the ferroelectric memory as the ninth embodiment according to the present invention.

FIG. 27 is a diagram showing a modification of the eighth embodiment.

FIG. 28 is a diagram showing an example of a circuit configuration of a conventional ferroelectric memory.

FIG. 29 is a diagram showing an example of a structure of a conventional ferroelectric memory.

FIG. 30 is a diagram showing the relationship between the write voltage and the capacity of a conventional ferroelectric memory.

[Explanation of symbols]

1 ... Memory cell, 2 ... Upper electrode, 3 ... Lower electrode, 4 ... Ferroelectric thin film, 5 ... First polarization state, 6 ... Partial polarization state, 1
1, 12, 13 ... Pulse sending circuit, 14 ... Changeover switch, 17 ... Read circuit, 19 ... First stripe electrode, 20 ... Second stripe electrode, 21 ... Storage cell, 31
... Pulse signal sending unit, 32 ... Ferroelectric cell matrix circuit, 33 ... Reading unit, 34 ... Terminal resistance element, 35
a, 35b ... Termination resistance element control circuit, 36 ... Differential reference cell, 37 ... Signal processing circuit, 38 ... Comparison amplification circuit, 39 ...
Low input impedance circuit, 40 ... Differential amplifier circuit, 41
... differential reference cells.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroyuki Yumori 2-43-2 Hatagaya, Shibuya-ku, Tokyo Inside Olympus Optical Co., Ltd. (72) Inventor Shuzo Hiraide 2-43 Hatagaya, Shibuya-ku, Tokyo No. 2 Olympus Optical Co., Ltd. (72) Inventor Takashi Mihara 2-43-2 Hatagaya, Shibuya-ku, Tokyo Olympus Optical Co., Ltd.

Claims (3)

[Claims] 1. An intersecting region of the stripe electrodes including first and second stripe electrodes facing each other and orthogonal to each other, and a ferroelectric thin film sandwiched between these stripe electrodes, and including the ferroelectric thin film. To the memory cells arranged in a matrix as memory cells and all the memory cells of the matrix memory cell, the first pulse is simultaneously applied to set the first polarization state indicating "0" information. A 0 "information writing unit and a memory cell selected from the memory cells in the first polarization state are applied with a second pulse having a polarity opposite to that of the first pulse, thereby indicating a" 1 "information. The third pulse is applied to the "1" information writing means for setting the polarization state of No. 2 and the storage cell selected from the storage cells set to "0" and "1", and is stored as the polarization state. Ru Read-out means for reading out information, and an input line and an output line which are provided on one of the lines consisting of the stripe electrodes of the matrix memory cell and which are directly connected to the selected memory cell when the third pulse is applied. Is set to a high resistance and a line connected to a non-selected memory cell is set to a low resistance, and "1", "" of the output signal of the memory cell read by the application of the third pulse. A ferroelectric memory comprising: a reading unit that determines 0 ". 2. An intersecting region of the stripe electrodes, comprising first and second stripe electrodes facing each other and orthogonal to each other, and a ferroelectric thin film sandwiched between these stripe electrodes, and including the ferroelectric thin film. A matrix memory cell in which the memory cells are arranged in a matrix as a memory cell, selecting all the electrodes of the first stripe electrode and all the electrodes of the second stripe electrode, and selecting all the memory cells; A step of applying a first pulse having a magnitude equal to or more than twice the coercive voltage of the ferroelectric thin film to all the memory cells, and setting the first polarization state indicating “0” information, A method for driving a ferroelectric memory, which is characterized by writing "0" information in all memory cells. 3. An intersecting region of the stripe electrodes, comprising first and second stripe electrodes facing each other and orthogonal to each other, and a ferroelectric thin film sandwiched between these stripe electrodes, and including the ferroelectric thin film. In the matrix memory cell in which the memory cells are arranged in a matrix as memory cells, by designating each electrode in the first and second stripe electrodes among the memory cells in which "0" information has already been written, the desired memory A step of selecting cells, and a voltage of 0.3 to 2 times the coercive voltage of the ferroelectric thin film is set as a write voltage Vw, and the designated first stripe electrode has Vw having a polarity opposite to that of the first pulse A voltage of / 3 V is applied, 0 V is applied to the electrode of the non-designated first stripe electrode, and 0 V is applied to the electrode of the designated second stripe electrode.
V is applied, a voltage of 2Vw / 3V is applied to the electrode of the non-designated second stripe electrode, and polarization of the first polarization state indicating "1" information is given to the selected memory cell. By selectively writing "1" information in a desired memory cell by setting a partial polarization state in which a domain having a polarization state and a domain having a polarization direction opposite to the first polarization state are mixed. A method for driving a characteristic ferroelectric memory.