JPH08273369A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To prevent the generation of noise by providing means for sequentially delaying an activation signal being fed to a sense amplifier provided in each mat area. CONSTITUTION: A plurality of pairs of bit line are connected through select transistors QP1, QP2 with a pair of output lines DL, *DL connected with specific pair of bit lines BK, *BL. A sense amplifier SA1 corresponding to a first mat M1 is fed with an activation signal ϕ1 and a sense amplifier SA2 corresponding to a second mat is fed with an activation signal ϕ2 being delayed through a delay circuit D1. Since a circuit for sequentially delaying the activation signal is provided, the sense amplifier SA for transferring the data from a memory on the output lines DL, *DL shifts the switching timing thus preventing the generation of noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a sense amplifier in which a memory cell array is divided into a plurality of mat areas and data of the memory cells is provided for each mat area. The present invention relates to prevention of generation of noise due to switching of an output buffer or the like in a semiconductor memory device which is output to an output terminal corresponding to the matte region via the semiconductor memory device.

[0002]

2. Description of the Related Art A conventional static RAM is constructed, for example, as shown in FIG. In the figure, the memory cell array region is, for example, four mat regions M1 and M.
It is divided into 2, M3 and M4. The memory cell MC is
The mat areas are arranged in a matrix and are connected between the bit line pairs BL and * BL to which one word line WL is supplied. A memory cell MC is selected by selecting one word line WL by a row address decoder (not shown) and selecting bit lines BL and * BL by a column address decoder (not shown).

A plurality of bit line pairs are connected to the selection transistor Q.
The bit line pair BL, * BL is connected to a pair of output lines DL, * DL via S1 and QS2, and the selection transistor is turned on in accordance with the output CY of the column address decoder, so that a specific bit line pair BL, * BL is output to the output line DL. , * DL. The data of the memory cell MC read from the bit line to the output line is sensed by the sense amplifier SA that operates based on the activation signal φs and then sufficiently amplified by the read amplifier AMP before being output to the corresponding output terminal O. To be done.

In the above semiconductor memory device, data is simultaneously read from the memory cells in the four mat areas and simultaneously output to the respective output terminals, so noise is generated due to the sense operation of the sense amplifier and the switching of the output buffer. There was a problem that it occurred. So, in the past,
In order to reduce noise, measures have been taken to reduce noise for each sense amplifier and each output buffer.

[0005]

However, conventionally,
Since the noise is adjusted for each sense amplifier or output buffer, there is a problem that the circuit design becomes complicated.

[0006]

In order to solve the above problems, the present invention provides a delay circuit means for sequentially delaying an activation signal supplied to a sense amplifier provided for each mat area. As a result, the sense amplifiers corresponding to the respective output terminals are driven with a time difference.

[0007]

The data read from the memory cell is output to the output line through the selection transistor, and the voltage difference between the output line pair is amplified to a certain level by the sense amplifier connected to the output line. Therefore, the sense amplifier determines the timing of generation of the data output to the output terminal. Therefore, by delaying the activation signal and making a difference in the operation start time, the sense amplifier and the output are eventually output. It is possible to shift the switching timing of the buffer and prevent the generation of noise in the semiconductor memory device.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A semiconductor memory device according to an embodiment of the present invention will be described below with reference to FIGS. Figure 1
It is a circuit diagram showing a configuration of a static RAM. In the figure, the memory cell array region is divided into, for example, four mat regions M1, M2, M3 and M4. The number of divisions can be appropriately increased or decreased according to the number of output bits of the memory.

As shown in FIG. 2, the memory cell MC includes a flip-flop and a pair of transfer transistors QT1 and QT.
2 and. The memory cells are arranged in a matrix in each of the above mat areas, each connected between the bit line pair BL, * BL, and one word line WL is supplied. To select a memory cell MC,
One word line WL is selected by the row address decoder, and bit line B is selected by the column address decoder.
This is done by selecting L, * BL.

The plurality of bit line pairs are, as shown in FIG.
It is connected to the pair of output lines DL and * DL via the selection transistors QS1 and QS2, and when the selection transistor is turned on by the output CY of the column address decoder, the specific bit line pair BL, * BL outputs its output. Connected to lines DL, * DL. The data of the memory cell MC read from the bit line to the output line is sensed by each sense amplifier SAj that operates based on the activation signal φs1 and amplified by the read amplifier AMPj, and then the corresponding output terminal Oj. Is output to.

A feature of the present invention is that a delay circuit Dj for sequentially delaying the activation signal supplied to the sense amplifier SAj is provided. That is, the activation signal φs1 is supplied to the sense amplifier SA1 corresponding to the first mat M1.
The sense amplifier SA2 corresponding to the second mat is supplied with the activation signal φs2 delayed by the delay circuit D1,
The sense amplifier SA3 corresponding to the third second mat is
The activation signal φs2 delayed by the delay circuit D2 is supplied (the same applies hereinafter).

FIG. 3 is a diagram showing a concrete circuit configuration of the sense amplifier SAj and the delay circuit Dj. The sense amplifier SAj includes P-channel MOS transistors QP1 and QP2.
And an amplifying section composed of N-channel MOS transistors QN1 and QN2, and a P-channel MOS which is a driving transistor
Transistor QPD and N-channel MOS transistor Q
It is composed of ND and.

The activation signal φsj is the P channel MO described above.
It is supplied to the gates of the S transistor QPD and the N channel MOS transistor QND. Then, the activation signal φsj + 1 delayed by the delay circuit Dj including the inverter chain is supplied to the sense amplifier SAj + 1 at the next stage. According to the static RAM described above, when a certain word line WLi is selected and a column address CYk is selected, the data of the memory cells are transferred from the respective mat areas to the data lines DL and * DL at substantially the same time.

However, in the sense amplifier SA for sensing the data, the activation signal is sequentially delayed, so that the start timing of the sensing operation is shifted, and as a result, as shown in FIG. The switching timing is also shifted. This makes it possible to prevent the generation of noise.

[0015]

As described above, the semiconductor memory device of the present invention is provided with the delay circuit means for sequentially delaying the activation signal supplied to the sense amplifier provided for each mat area. Thus, the sense amplifiers corresponding to the output terminals are driven with a time difference. Therefore, the operation timings of the sense amplifiers and the output buffers are shifted, and it is possible to prevent the generation of noise.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing a memory cell of a semiconductor memory device according to an exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing a sense amplifier and a delay circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

FIG. 4 is a waveform diagram illustrating an operation of the semiconductor memory device according to the exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a semiconductor memory device according to a conventional example.

[Explanation of symbols]

 MC memory cell WL word line BL, * BL bit line QS1, QS2 select transistor DL, * DL data line CY column address line SAj sense amplifier AMPj amplifier Oj output terminal φs sense amplifier activation signal D1, D2, D3 delay circuit

Claims (3)

[Claims] 1. A memory cell array area arranged in a matrix is divided into a plurality of mat areas, and data of the memory cells is output to an output terminal corresponding to the mat area via a sense amplifier provided for each mat area. The semiconductor memory device according to claim 1, further comprising delay circuit means for sequentially delaying the activation signal supplied to the sense amplifier. 2. A pair of bit lines to which a plurality of memory cells are connected, a pair of output lines, a pair of select transistors provided between the bit lines and the output lines, and the pair of select transistors are controlled. A plurality of memory mat areas each including a column address decoder and a sense amplifier that is connected to a pair of output lines and starts a sensing operation by an activation signal are arranged, and data of the memory cell is transmitted through the sense amplifier to the mat area. A semiconductor memory device outputting to an output terminal corresponding to a region, further comprising delay circuit means for sequentially delaying an activation signal supplied to a sense amplifier provided for each mat region. . 3. The semiconductor memory device according to claim 1, wherein the delay circuit means is composed of an inverter chain.