JPH08265564A - Picture input device - Google Patents

Abstract

PURPOSE: To accurately input a picture by detecting whether the document picture is a multilevel picture or a binary picture based on whether or not the picture element density level is a halftone level between the black reference and the white reference. CONSTITUTION: In a document picture discriminating device, a comparator 21 compares an output signal Sout from a CCD sensor with the black reference, and a comparator 22 compares the output signal Sout from the CCD sensor with the white reference. An exclusive OR circuit 23 which operates exclusive OR between the comparison result of the comparator 21 and that of the comparator 22 is provided. The output from the circuit 23 is latched in a latch circuit 24 by a clock CLK, and a detection circuit 25 discriminates whether the original picture is binary or multilevel based on the output from the latch circuit 24 and outputs the discrimination result. The circuit 25 discriminates the document picture as a multilevel picture when the output signal from the circuit 24 goes to the high level at least once, for example, in one prescanning, but the circuit 25 discriminates it as a binary picture when the output signal from the circuit 24 is fixed to the low level then.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device such as a copying machine or an electronic file.

[0002]

2. Description of the Related Art Conventionally, an image input device as disclosed in, for example, JP-A-5-122436 is known. In this image input device, when necessary image data can be read by giving priority to speed over sensor output signal accuracy like binary data, high-speed basic clock is used during normal reading to perform high-speed reading. When the required image data is multi-valued data and the accuracy of the sensor output signal is important, the basic clock with a lower frequency than the basic clock is used for reading, and the reading speed is increased as a whole. I am trying.

[0003]

In the above-described image input apparatus, in order to perform the proper switching selection of the clock, it is possible to accurately determine whether the image data is binary data or multi-valued data. However, in the past, a technique for accurately discriminating whether image data is binary data or multi-valued data has not been established, and therefore, accurate clock switching selection, that is, accurate clock There is a problem that it is not possible to input various images.

According to the present invention, whether the original image is a multi-valued image or not
It is an object of the present invention to provide an image input device capable of accurately determining whether a value image is input and inputting an appropriate image.

[0005]

In order to achieve the above object, the inventions according to claim 1 and claim 2 are image pickup means for picking up and reading an original image, and the original image is a binary image. A manuscript image discriminating means for discriminating whether the image is a multivalued image or not, and for driving the image pickup means depending on whether the discrimination result of the manuscript image in the manuscript image discriminating means is a binary image or a multivalued image. The original image discrimination means compares the pixel density level from the image pickup means with a preset black reference and white reference, respectively. Whether the original image is a multi-valued image or a binary image is detected based on whether or not the pixel density level is at a halftone level between the black reference and the white reference.
As a result, it is possible to accurately determine whether the original image is a multi-valued image or a binary image, make an appropriate clock switching selection, and input an appropriate image. In particular, the document image discriminating means can be made to have a simple structure, and multi-valued / binary discrimination of the document image can be easily performed in real time.

According to the third aspect of the invention, as the black reference and the white reference, the average value of the pixel density levels of the respective pixels in the black reference read image and the average value of the pixel density levels of the respective pixels in the white reference read image. Are used respectively. This makes it possible to more stably discriminate between multi-value and binary.

Further, in the invention according to claim 4, the original image discrimination means sets the number of pixels or the halftone level at which the pixel density level from the image pickup means is at the halftone level between the black reference and the white reference. The number of non-existing pixels is counted, and when the count value is larger than a predetermined threshold value, it is discriminated as a multi-valued image or a binary image, and when it is not larger than the predetermined threshold value, it is discriminated as a binary image or a multi-valued image. This makes it possible to reliably determine whether the original image is a binary image or a multi-valued image.

Further, in the invention according to claim 5, the original image discrimination means counts the number of consecutive pixels whose pixel density level from the image pickup means is at a halftone level or not. When the count value is larger than a predetermined threshold value, it is determined to be a multi-valued image or a binary image, and when it is not larger than the predetermined threshold value, it is determined to be a binary image or a multi-valued image. This makes it possible to reliably determine whether the original image is a binary image or a multi-valued image.

The inventions according to claims 6 and 7 are:
The type of the original image can be easily specified by an external input, and the fine scan can be directly performed without performing the prescan. Even in this case, the accurate image input can be performed.

According to the present invention, the A / D conversion means, the binarization means, and the bit distribution means are provided, and the document image is discriminated as a multi-valued image by the document image discrimination means. If the image data is instructed, or if the image data instructing means indicates a multi-valued image, the output signal from the imaging means is digitized by the A / D converting means,
Further, when the original image is discriminated by the original image discriminating means as a binary image, or when the image data instructing means is instructed as a binary image, the output signal from the image pickup means is set to the binary image. The binarizing means binarizes the binarized data and the bit distributing means multi-bits the binary data. In the configuration example of FIG. 14, the binary image data is binarized and distributed at high speed. The A / D conversion means is used only for digital conversion processing for multi-valued image data which is not required to be as fast as binary image data. As a result, A /
It is not necessary to use an expensive high-speed A / D converter as the D conversion means, and the image input device can be made low in cost. That is, binary image data can be digitally converted at high speed without using a high-speed A / D converter, and optimum image input can be performed for both binary and multi-valued images. .

According to a ninth aspect of the invention, the A / D conversion means, the frequency division means for dividing the clock synchronized with the pixel by n, the binarization means, and the frequency division signal from the frequency division means are used. A serial / parallel conversion means for synchronously outputting the digital outputs from the binarization means collectively in n-pixel units, a storage device, and an address generation means for generating an address of the storage device are provided. When the image is discriminated as a multi-valued image by the document image discriminating means, or when the image data instructing means is instructed to be a multi-valued image, the output signal from the image pickup means is outputted by the A / D conversion means. The data is digitized and given to the memory device, and a clock synchronized with the pixel is added to the address generation means, and the address generation means generates the address of the memory device in synchronization with one pixel, whereby the memory is stored. To one address of the location to store the digital data for one pixel from the A / D converting means,
When the document image is discriminated by the document image discriminating means as a binary image, or when the image data instructing means is designated as a binary image, the output signal from the image pickup means is digitalized by the binarizing means. And outputs the output from the binarizing means to the storage device in units of n pixels by the serial / parallel converting means, and the address generating means divides the clock synchronized with the pixels into n by the dividing means. Is added,
The address generating means generates an address of the storage device in units of n pixels, and thereby stores one pixel of digital data from the serial-parallel conversion means in one address of the storage device. The binary image data is subjected to high-speed digital conversion processing by the binarization means and the serial / parallel conversion means, and the A / D conversion means is for multi-valued image data which is not required to be as fast as the binary image data. Used only for digital conversion processing. As a result, A /
It is not necessary to use an expensive high-speed A / D converter as the D conversion means, and the image input device can be made low in cost. That is, similar to the invention of claim 8, the A / D
Binary image data can be digitally converted at high speed without using a high-speed converting means, and optimum image input can be performed for both binary images and multivalued images. Further, in the invention according to claim 9, the original image is 2
In the case of a value image, a sensor output is digitized by a binarization circuit, and data of n pixels is stored in a storage device having an n-bit memory cell for one memory address, which requires a large-capacity storage device. Without doing so, it is possible to obtain a stable image with a large reading area (a large number of reading pixels).

According to the invention of claim 10, the above-mentioned 2
The binarizing means digitizes the output signal from the imaging means based on the average value of the pixel density levels of the black reference read image and the average value of the pixel density levels of the white reference read image read at the start of the fine scan. As a result, even when the driving clock of the sensor is switched to the high-speed clock CLK ₂ , or when a light source variation or the like occurs, appropriate binarization is always performed and a stable image can be obtained.

According to the eleventh aspect of the invention, when the original image is a multi-valued image, the integrating process is executed by the integrating and averaging means, and when the original image is a binary image, the integrating process by the integrating and averaging means is executed. By not performing it, better reading quality can be obtained in the multi-valued image, and the reading time can be shortened in the binary image.

According to the twelfth aspect of the present invention, the original image is read with an optimum light amount according to the type of the original image. As a result, a good original image can be obtained, and when the original image is a binary image, the light amount of the light source is made lower than that in the case of a multi-valued image, thereby preventing heat generation of the device and reducing power consumption. Labor saving is possible.

According to the thirteenth aspect of the present invention, when the original image is a binary image, the sensor drive clock is switched to a high-speed clock, and the light amount of the light source is made lower than in the case of a multi-valued image. The reading time can be shortened according to the original image data, and the original image is read with an optimum light amount according to the type of the original image. This allows
A good original image can be obtained, heat generation of the device can be prevented, and power can be saved.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram of an embodiment of an image input apparatus according to the present invention. Referring to FIG. 1, the image input device is
A light source 4 for irradiating the original 1 on the original table (contact glass) 2 with light, a light source driving means (light source drive circuit) 14 for driving the light source 4, and a motor 5 for moving the original table 2 in the direction of arrow x. , A motor drive controller 15 for controlling the drive of the motor 5.
A reflected light from the original 1 enters through the mirror 3 and the imaging lens 6, and a CCD sensor 7 for picking up an image of the original 1;
A sample and hold means (sample and hold circuit) 8 for sampling and holding the output signal from the CCD sensor 7, and an output signal (pixel density level) from the sample and hold circuit 8.
A / D conversion means (A / D) for converting S _out into a digital signal
(Conversion circuit) 9, a dark output correction circuit 10 that corrects a dark output for a signal from the A / D conversion circuit 9, a shading correction circuit 11 that performs shading correction, and a linear density conversion circuit that performs linear density conversion. 12, an interface circuit 13 that functions as an interface with an output device or a storage device, and an original that determines whether the original image data is binary or multivalued based on an output signal S _out from the sample hold circuit 8. An image discriminating means 17, a clock switching means 18 for switching the driving clock of the CCD sensor 7 based on the discrimination result of the original image, and an image pickup drive for driving the CCD sensor 7 based on the clock from the clock switching means 18. And means (CCD drive circuit) 16.

FIG. 2 is a view showing an example of the arrangement of the original image discrimination means 17. In the example of FIG. 2, the document image discrimination means 17 is
The output signal (pixel density level) S _out from the CCD sensor 7 (sample and hold circuit 8) and the output signal from the CCD sensor 7 (sample and hold circuit 8) and the first comparator 21 for comparing the magnitude of the black reference. An exclusive OR that takes an exclusive OR of the second comparator 22 that compares the magnitude of S _out and the white reference, and the comparison result of the first comparator 21 and the comparison result of the second comparator 22. Based on the circuit 23, the latch circuit 24 that latches the output from the exclusive OR circuit 23 by a predetermined clock CLK, and whether the original image is binary or multivalued based on the output from the latch circuit 24, this is determined. It has a detector 25 which outputs as a discrimination result.

The clock CLK applied to the latch circuit 24 is the hold pulse of the sample hold circuit 8.
It is synchronized with a pixel whose phase is behind that (not shown), and the latch circuit 24 latches the comparison result with this clock CLK. Further, the detector 25 detects that the original image is a multi-valued image when the output signal from the latch circuit 24 becomes “H” at least once in one pre-scan, and the latch 25 also latches. When the output signals from the circuit 24 are all "L",
The original image is detected as a binary image, and the detector 25 is cleared every prescan.

The white reference is, for example, the minimum value (minimum value) of the pixel density level of the white reference read image output from the sensor when the white reference plate is read at the start of prescan.
Is set in advance. The black reference is set in advance as the maximum value (peak value) of the pixel density level of the black reference read image output from the sensor when the black reference plate is read at the start of prescan.

The clock switching means 18 uses the high-speed clock CL as a clock for driving the CCD sensor 7.
The clock is switched to either K ₁ or the low speed clock CLK ₂ . That is, when the original 1 is a multi-valued image, the low-speed clock CLK ₁ is switched to, and when the original 1 is a binary image, the high-speed clock CLK ₂ is switched to read the original image at high speed. However, as the high-speed clock CLK ₂ , one that can be read by the sensor 7 is used. Further, the clock CLK applied to the latch circuit 24 of the document image discrimination means 17 is
By the clock switching means 18, for example, the low speed clock CL
When K ₁ is selected and the original image is read, this low speed clock CLK ₁ is used.

In the image input apparatus having such a structure, the original 1 set on the contact glass 2 is irradiated with the light from the light source 4, and the reflected light is passed through the mirror 3 and the imaging lens 6 to the CCD sensor 7. The original 1 on the CCD sensor 7
Form an image of. At this time, the sub-scanning is performed by moving the original 1, that is, the contact glass 2 by the motor 5 in the direction of the arrow x.

The output signal from the CCD sensor 7 has the transfer clock component of the sensor removed by the sample and hold circuit 8 and is added to the A / D conversion circuit 9 as S _{out and} converted into a digital signal in the A / D conversion circuit 9. To be converted. Thereafter, the digital signal from the A / D conversion circuit 9 is read by the dark output correction circuit 10 for each pixel, for example, by reading out the data of the correction memory stored in advance, and the calculated signal is calculated for each pixel of the CCD sensor 7. The dark output is corrected, and in the shading correction circuit 11, similarly to the dark output correction, prestored data is read out from the correction memory and calculated for each pixel, so that the illumination system and the image forming system are used. Correction of variations in brightness and variations in sensitivity of the CCD sensor 7 is performed. Thereafter, the linear density conversion circuit 12 performs density conversion in the main scanning direction as necessary, and the density conversion is sent to the output device or the storage device via the interface circuit 13.

Here, the light source 4 and the CCD sensor 7 are
The light accumulation time is set and driven so that a sufficient sensor output can be obtained even in a multi-valued image.

FIG. 3A is a diagram showing an example of one-line output of the CCD sensor 7. In the line output of FIG. 3 (a), DS (E) is the output of a pixel having no photosensitive section and only the transfer section, and DS (S) is the output of a pixel whose photosensitive section is optically shielded. Following DS (S), document reading data is output.

When the sensor output as shown in FIG. 3A is given to the sample and hold circuit 8, the sample and hold circuit 8 removes the transfer clock component from the sensor output as shown in FIG. Use analog signals as shown in.

FIG. 3 from this sample hold circuit 8
Of the output signals as shown in (b), for example, the value of DS (E) is sampled and held by another sample and hold circuit (not shown) to obtain the upper limit reference voltage V _{refT of} the A / D conversion circuit 9, and white. The peak value of the output when the reference plate is read is detected and held by a peak hold circuit (not shown) and the lower limit reference voltage V of the A / D conversion circuit 9 is held.
_{By setting refB} , the dynamic range of the A / D conversion circuit 9 is determined.

In this way, the actual reading of the original 1 is performed.
Although (fine scan) is performed, a prescan is performed prior to this fine scan to determine whether the original 1 is a binary image or a multi-valued image, and the CCD sensor 7 of the CCD sensor 7 is determined according to the determination result. It is necessary to set driving conditions in advance.

Therefore, in the image input apparatus of FIG. 1, the prescan is performed prior to the fine scan, and the original image is the binary image in the original image discriminating means 17 based on the image of the original 1 read during the prescan. It is determined whether the image is a multivalued image.

More specifically, the document image discrimination means 17 is
The output signal from the sample hold circuit 8 (more specifically, sample the output signal from the hold circuit 8 without a predetermined amplifier (shown) amplified signal) S _out (In the following, for convenience, the S _out (Referred to as sensor output) is compared with the black reference and the white reference obtained by reading, for example, a black reference plate and a white reference plate at the start of prescan.

FIG. 4 shows a halftone region IM of an image which is larger than the black reference and smaller than the white reference. CCD sensor 7 when reading document 1 during prescan
When the level of the output signal S _out from the (sample and hold circuit 8) is in this halftone region IM, the comparison result of the first comparator 21 becomes the high level “H”, and
Since the comparison result of the second comparator 22 becomes the low level "L", the output from the exclusive OR circuit 23 becomes the high level "H". As a result, the output of the latch circuit 24 becomes "H", and the detector 25 detects that the original image is a multi-valued image.

On the other hand, when the level of the output signal S _out from the CCD sensor 7 (sample hold circuit 8) is not in the halftone region IM, the comparison result of the first comparator 21 and the second comparator 22 Both become low level "L", or both become high level "H", so the output from the exclusive OR circuit 23 becomes low level "L". As a result, the output of the latch circuit 24 is "L", and the detector 25 detects that the original image is a binary image.

Specifically, when the sensor output S _out is as shown in FIG. 5, the first comparator 21 is "H" and the second comparator 22 is "L" at the timing of t _1. Next to
Since the output from the exclusive OR circuit 23 becomes "H" and the output of the latch circuit 24 becomes "H" at this time, the detector 25 determines that the original image is a multi-valued image. Output.

Further, even when the sensor output is as shown in FIG. 6, the output of the exclusive OR circuit 23 becomes "H" at the timing of t ₁ , t ₂ , and t ₃ , and the latch Since the output of the circuit 24 becomes “H” multiple times, the detector 25
The determination result that the original image is a multi-valued image is output.

On the other hand, the output of the CCD sensor 7 is shown in FIG.
, The output of the exclusive OR circuit 23 becomes “L” at all timings t _{0 to} t ₄ .
Since the output of the latch circuit 24 remains "L", the detector 25 outputs the result of the determination that the original image is a binary image.

When the document image discriminating means 17 discriminates that the document image is a multi-valued image, it outputs a signal to the clock switching means 18 to the effect that it is a multi-valued image. By this signal, the clock switching means 18 switches to the low-speed clock CLK ₁ as the driving clock of the CCD sensor 7 and causes the CCD sensor 7 to perform fine scanning of the original 1.

On the other hand, when the manuscript image discriminating means 17 discriminates that the manuscript image is a binary image, it outputs a signal indicating that the manuscript image is a binary image to the clock switching means 18. In response to this signal, the clock switching means 18 switches to the high-speed clock CLK ₂ as the driving clock of the CCD sensor 7, and causes the CCD sensor 7 to perform fine scanning of the original 1.

8A and 8B show a low speed clock CLK ₁ and a high speed clock CLK ₂ , respectively. 8 (a) and 8 (b), _TL and _TH are the scanning time of one line, that is, the light accumulation time, and when switching to the low-speed clock CLK ₁ as shown in FIG. 8 (a), large enough so that the sensor output is obtained, the light accumulating time T _L has been the (slower clock CLK ₁ cycle × read pixel number + alpha), the high-speed clock CLK ₂ as shown in FIG. 8 (b) At the time of switching, the light accumulation time T _{H is set} to about (the cycle of the high-speed clock CLK ₂ × the number of read pixels).

As described above, in this embodiment, the document image discriminating means 17 outputs the sensor output S during the prescan.
_Out is compared with a black reference and a white reference as a reference to determine whether the original image is binary or multi-valued. Therefore, whether the original image is binary is determined. It is possible to accurately determine whether it is multi-valued, it is possible to accurately switch the clock according to the original image, and when the image is fine-scanned, the original image is binary or multi-valued. Appropriate processing can be performed depending on the existence.

In the above-mentioned embodiment, the original image discriminating means 17 is explained as having the constitutional example shown in FIG. 2, but various modifications and improvements are added to the constitutional example of FIG. Is also possible.

FIG. 9 is a diagram showing another example of the configuration of the document image discrimination means 17. In the configuration example of FIG. 9, a counter 27 is provided instead of the detector 25 in the configuration example of FIG. 2, and the counter 27 includes the latch circuit 24.
Is counted "H", and whether the original image is binary or multi-valued is determined based on this count value.

That is, the CCD sensor 7 (sample hold circuit 8) outputs the output signal S _out for each pixel of the original image, and the output signal S _out is added to the original image discriminating means 17.
From the exclusive OR circuit 23, the determination result for each pixel,
That is, the determination result of whether the pixel level is in the halftone area IM (multi-value level) or not in the halftone area IM (binary level) of FIG. 4 is output and the latch circuit is output. In addition to 24, the latch circuit 24 outputs "H" when the pixel level is a multi-valued level and outputs "L" when the pixel level is a binary level. Count the number of level pixels
(Counting), and when the number of pixels (the number of pixels at the multi-valued level) is less than the preset number, it is determined that the original image is a binary image, and the number of pixels is determined in advance. When the number is larger than the set number, it is determined that the original image is a multi-valued image.

With such a configuration, it is possible to determine whether the original image is a binary image or a multi-valued image based on the determination result for each pixel, so that more reliable determination can be performed.

FIG. 10 is a diagram showing still another configuration example of the document image discrimination means 17. In the configuration example of FIG. 10, the integrator 29 is provided in the preceding stage of the detector 25 in the configuration example of FIG.
The outputs of 4 are integrated and given to the detector 25.

In such a configuration, the integrator 29 can count the continuous number of pixels of multi-valued level as the integrated value, and the output of the integrator 29, that is, the integrated value is equal to or larger than the predetermined threshold value Vt. Then, the detector 25 becomes "H", and it can be determined that the original image is a multi-valued image. Here, the time constant of the integrator 29 and the predetermined threshold value Vt of the detector 25 are set in advance in accordance with the number of continuous pixels required to discriminate the multi-level image.

FIG. 11 shows a state in which the sensor output S _out t ₁ -t ₂ has a multi-valued level only during the output, and the multi-valued level has only one pixel. At this time, the output of the latch circuit 24 becomes “H” for only one clock cycle, and the output of the integrator 29 cannot reach the predetermined threshold value Vt. In this case, the detector 25 outputs the binary image of the original image. The result of determination that the image is an image is output.

Further, in FIG. 12, the sensor output S _out is t ₁
During the ~t _4, a multi-level continuously, state is shown when the multi-level continues for three pixels or more. At this time, the output of the latch circuit 24 becomes “H” for three clock cycles, and the output of the integrator 29 reaches the predetermined threshold value Vt. In this case, the detector 25 determines that the original image is a multi-valued image. Is output.

Further, in FIG. 13, the sensor output S _out is t _0.
It is shown that all the pixels are at the binary level at all timings up to t ₄ and all the pixels are at the binary level. At this time, all the outputs of the latch circuit 24 become “L” and the output of the integrator 29 does not reach the predetermined threshold value Vt, so the detector 25 outputs the determination result that the original image is a binary image.

In the above-described embodiment, the maximum value of the pixel density level in the black reference read image and the minimum value of the pixel density level in the white reference read image are used as the black reference and the white reference. Alternatively, the average value of the pixel density levels in the black reference read image and the average value of the pixel density levels in the white reference read image can be used. More specifically, in the configuration examples of FIGS. 2, 9 and 10, the original image discrimination means 17 is provided with an averaging means for obtaining an arithmetic mean value of the sensor output S _out , and for example, a black reference plate is read at the start of prescanning. The average value of the pixel density level of each pixel in the black reference read image at the time of scanning is used as the black reference, and, for example, the pixel density level of each pixel in the white reference scan image when the white reference plate is read at the start of prescan The average value can be used as the white reference, and in this case, the determination can be performed more stably.

In the configuration example of FIG. 9, the halftone level is
The counter 27 counts the number of pixels at the (multi-valued level), but the counter 27 counts the number of pixels that are not at the halftone level, and when the count value is larger than a predetermined threshold value, it is a binary value. It is also possible to determine that the image is a multi-valued image when it is not larger than a predetermined threshold value.

Similarly, in the configuration example of FIG.
Is configured to integrate the continuous number of pixels at the halftone level (multilevel), but instead is configured to integrate the continuous number of pixels that are not at the halftone level. Is also good. In this case, when the output of the integrator 29 is equal to or higher than a predetermined threshold value, it can be determined as a binary image, and when it is equal to or lower than the predetermined threshold value, it can be determined as a multi-value image.

FIG. 14 is a partial block diagram of another embodiment of the image input apparatus according to the present invention. Note that, in FIG. 14, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In the image input device of FIG. 14, in the configuration of FIG. 1, switches are provided at the front stage and the rear stage of the A / D conversion circuit 9 for digitizing the output signal S _out from the CCD sensor 7 (sample hold circuit 8). Means 31 and 32 are provided, and a binarization means (binarization circuit) 33 and a distribution means (distributor) 34 are provided in parallel with the A / D conversion circuit 9.

Here, the switch means 31, 32 are adapted to switch according to the discrimination result of the document image discrimination means 17, and when the document image discrimination means 17 discriminates the document image as a binary image. The switch means 31 _supplies the sensor output S _out to the binarization circuit 33 and the distributor 34, digitizes the sensor output S _out by the binarization circuit 33, and then the distributor (for example, an n-bit distributor) 34. When the original image discriminating means 17 discriminates the original image as a multi-valued image, the switch means 31
The output signal from the CCD sensor 7 is given to the A / D conversion circuit 9, digitized by the A / D conversion circuit 9, and the switch means 3 is provided.
2 to the dark output correction circuit 10.

In the configuration shown in FIG. 14, when the original image is multi-valued, the signal from the original image discrimination means 17 causes
The switch means 31 gives the sensor output S _out to the A / D conversion circuit 9, the A / D conversion circuit 9 digitizes the sensor output S _out to, for example, n bits, and the switch means 32 makes the A / D.
The n-bit digital signal from the conversion circuit 9 can be output to the dark output correction circuit 10.

When the original image is binary, the switch means 31 gives the sensor output S _out to the binarizing circuit 33 and the distributor 34, and the binarizing circuit 33 makes the sensor output S _out 1 bit. And digitized (i.e., binarized) into a digital signal from the binarization circuit 33 (1
(Bit signal) into the same n-bit signal as in the A / D conversion circuit 9 (n-bit conversion), and the switch means 32 converts the n-bit digital signal from the distributor 34 into linear density conversion. It can be output to the circuit 12. When the original image is a binary image, the n-bit digital signal can be directly output to the linear density conversion circuit 12 without performing the dark output correction and the shading correction.

As described above, in the configuration example of FIG. 14, the binary image data is subjected to high-speed digital conversion processing by the binarization circuit 33 and the distributor 34, and the A / D conversion circuit 9 outputs 2 bits.
Since it is used only for digital conversion processing for multi-valued image data that is not required to be as fast as value image data, it is not necessary to use an expensive high-speed A / D converter for the A / D conversion circuit 9. The image input device can be made low cost. That is, binary image data can be digitally converted at high speed without using a high-speed A / D conversion circuit 9, and optimal image input can be performed for both binary images and multi-valued images. it can.

FIG. 15 is a diagram showing a modification of the image input device of FIG. In FIG. 15, the digitized data is converted into the dark output correction circuit 10, the shading correction circuit 11, the linear density conversion circuit 12, and the interface 13.
It is assumed that the data is written in the external storage device 36 instead of being given to

Referring to FIG. 15, in this image input device, in the image input device of FIG. 14, instead of providing a distributor 34 between the binarization circuit 33 and the switch means 32, a serial / parallel conversion means ( (Serial-parallel converter) 38 is provided, and between the serial-parallel converter 38 and the external storage device 36,
A frequency dividing means (frequency divider) 39, a switching means 40, and an address generating means (address counter) 41 are provided.

Here, the serial-parallel converter 38, the frequency divider 39,
A clock CLK synchronized with the pixel data (hold pulse) shown in FIG. 2 is applied to the switch means 40, and a frequency divider 39 divides the clock CLK by _n to generate a synchronization signal S _n and a divided clock CLK _n . And outputs to the serial-parallel converter 38 and the switch means 40, respectively, and the serial-parallel converter 38
Synchronizes pixel data (1 bit), which is sequentially input in synchronization with the clock CLK, with the frequency-divided signal S _n in n pixel units (n
(Bit) is output to the external storage device 36 via the switch means 32. Therefore, as the external storage device 36, one having n-bit memory cells for one memory address (that is, one capable of storing n-bit data) is used.

Further, each switch means 31, 32, 40
Is adapted to switch the signal according to the discrimination result from the document image discriminating means 17 whether the document image is a multi-valued image or a binary image. When the document image is multi-valued, the switch means 31 is used.
_Supplies the sensor output S _out to the A / D conversion circuit 9, and the switch means 32 outputs the digital data of one pixel unit (1 bit) from the A / D conversion circuit 9 to the external storage device 36. The switch means 40 outputs the clock CLK as the clock of the address counter 41, whereby data is stored in the external storage device 36 pixel by pixel.

On the other hand, when the original image is binary, the switch means 31 outputs the sensor output S _out to the binary circuit 3.
3, the switch means 32 outputs the digital data in n pixel units (n bits) from the serial-parallel converter 38 to the external storage device 36, and the switch means 40 divides the frequency. A frequency-divided clock CLKn obtained by dividing the clock CLK by n is output as a clock of the address counter 41 by the device 39, whereby data of n pixels is stored in the external storage device 36 at one time. .

FIG. 16 is a time chart for explaining the operation of the image input device of FIG. 15 when the original image is binary. Note that FIG. 16 shows a case where the frequency division ratio n of the frequency divider 39 is 4.

In the image input device of FIG. 15, the original image is 2
When it is a value, the sensor output S _out is digitized by the binarization circuit 33 and added to the serial-parallel converter 38. At this time, the serial-parallel converter 38 sequentially takes in the digital data (pixel data) from the binarization circuit 33 with the clock CLK. On the other hand, the frequency divider 39 generates a clock CLKn (CLK ₄ ) obtained by dividing the clock CLK by n (= 4) and a synchronization signal Sn (S ₄ ) for every four divisions, and the serial-parallel converter 38 has A synchronization signal Sn (S ₄ ) is given. As a result, the serial-parallel converter 38
Outputs to the external storage device 36 in units of 4 pixels in synchronization with the signal Sn (S ₄ ) generated by the frequency divider 39.
Further, the switch means 40 outputs the clock signal CLKn (CLK ₄ ) divided by the frequency divider 39 as a clock of the address counter 41, whereby the address counter 41 uses the divided clock CLKn (CLK ₄ ) as an external signal. The memory address of the storage device 36 is set.

In this way, in the serial-parallel converter 38, the pixel data sequentially fetched by the clock CLK is output from D ₀ to D _{0 at} the timing P ₀ of the synchronizing signal Sn (S ₄ ).
D ₃ is output at one time and stored in the memory address A ₀ of the external storage device 36, and then D _{4 to} D ₇ are output at _one time at the timing P ₁ of the synchronization signal Sn (S ₄ ), and the external storage device 36 is output. of so that they are stored in the memory address a _1, stored in the external storage device 36 at a time by 4 pixel minutes, high-speed processing is possible.

Thus, also in the configuration example of FIG.
The binary image data is subjected to high-speed digital conversion processing by the binarization circuit 33 and the serial / parallel converter 38, and the A / D conversion circuit 9 is a multi-valued image which is not required to be as fast as the binary image data. Since the A / D conversion circuit 9 is used only for digital conversion processing of image data, expensive high-speed A
Since it is not necessary to use the / D converter, the image input device can be manufactured at low cost. That is, binary image data can be digitally converted at high speed without using a high-speed A / D conversion circuit 9, and optimal image input can be performed for both binary images and multi-valued images. it can. Further, in the configuration example of FIG. 15, when the original image is a binary image, the sensor output is digitized by a binarization circuit,
By storing n-pixel data in a memory device having n-bit memory cells for one memory address, a large read area (a large number of read pixels) can be obtained without requiring a large-capacity memory device. A stable image can be obtained.

When the image data thus written in the external storage device 36 is read out from the external storage device 36, although not shown, an n-bit parallel-serial converter is provided and the frequency divider is operated in the same manner as described above. Is used to set the memory address, and if necessary, the n-bit distributor may be used to convert the binary data into the number of bits of the output device (printer, display, etc.).

The binarization threshold value of the binarization circuit 33 shown in FIGS. 14 and 15 is, for example, a black reference plate and a white reference plate read at the start of the fine scan, and the average value of the respective pixel density levels is read. Can be set as the lower limit value and the upper limit value of the threshold. In this way, by generating the reference of the binarization circuit from the average value of the pixel density levels of the black reference read image and the average value of the pixel density levels of the white reference read image read at the start of the fine scan,
Even when the driving clock of the sensor is switched to the high-speed clock CLK ₂ or when the light source changes or the like, appropriate binarization is always performed and a stable image can be obtained.

FIG. 17 is a block diagram of still another embodiment of the image input apparatus according to the present invention. In the image input device of FIG. 17, the read line signal is further averaged in the sub-scanning direction by a predetermined number of lines (m times) in the image input device of FIG. A cumulative averaging means 43 which is a signal is provided in the subsequent stage of the A / D conversion circuit 9, and the motor 5 is sub-scanned at a predetermined scanning speed in accordance with such a cumulative averaging process. Line integration processing control means 45 for controlling is provided.

In the image input device having such a structure, when the document image discriminating means 17 discriminates that the document image is multi-valued at the time of prescan, at the time of fine scan,
In the integration and averaging means 43, the line data of the document 1 from the A / D conversion circuit 9 is set for a predetermined number of lines (m times) set in advance, based on the determination result that the document image is multivalued.
Simultaneously averaging and outputting to the dark output correction circuit 10, at the same time, the line integration processing control means 45 controls the motor drive control unit 15 so that the document 1 is scanned at a scanning speed of 1 / m of a preset scanning speed. To do.

When the document image discrimination means 17 discriminates that the document image is binary during the prescan,
At the time of fine scanning, the dark output correction circuit 10 does not perform the integration and averaging process on the digital data (line data) from the A / D conversion circuit 9 based on the determination result that the original image is binary. Output.

FIG. 18 is a time chart for explaining the integration and averaging process. Here, FIG. 18A shows an input signal from the A / D conversion circuit 9 to the integration and averaging means 43, and L1, L2, ..., L17 respectively represent signals for one line, that is, line data. ing. 18B and 18C show control signals CTL ₁ and CTL ₂ when the number of integrations m is 4, and FIGS. 18D and 18E show when the number of integrations m is 8. The control signals CTL ₁ and CTL ₂ are shown.

Note that these control signals CTL ₁ and CTL ₂
Is generated in the integrating and averaging means 43 in synchronization with the clock CLK. Further, these control signals CTL ₁ and CTL ₂ are supplied to the original image discrimination means 17
Is used only in the integrated averaging process when the original image is discriminated as a multi-valued image, and when the integrated averaging process is not performed, that is, when the original image discriminating means 17 discriminates the original image as a binary image. Control signals CTL ₁ , CT
L ₂ is not used, and in this case, the digital data from the A / D conversion circuit 9 is directly output from the integration / averaging means 43 to the dark output correction circuit 10 as it is.

Now, the case where the integration of m = 4 is performed will be described. In this case, first, when the control signal CTL ₁ of FIG. 18B becomes low level “L”, only the line data L 1 of the input signal is written in the memory of the integrating / averaging means 43. Next, the control signal CTL ₁ is high level “H”.
At the timing, the next input signal, that is, the line data L2 is input. At this time, the line data L1 written in the memory is read and this is used as the dot position data corresponding to the line data L2 of the input signal. It is integrated and written as L1 + L2 again in the memory. Next, at the next timing when the control signal CTL ₁ is “H”, the line data L3 is input. At this time as well, similarly to the previous timing, the line data L1 + L2 written in the memory is read, This is added to the line data L3 and written as L1 + L2 + L3 in the memory again. Then, at the next timing, when the control signal CTL ₂ of FIG. 18C becomes low level “L”, L1 + L2 + L3 is integrated with the line data L4 of the input signal to become L1 + L2 + L3 + L4, and then this is averaged (for example, (Divided by 4) and output to the dark output correction circuit 10 as new 1-line data L1 ′.

Next, when the control signal CTL ₁ becomes "L" again, only the line data L5 of the input signal is written in the memory, and thereafter, the same operation as described above is repeated to integrate and average the line data L5 to L8. It is output as new 1-line data L2 ', and line data L9-L1 is output.
2 can be integrated and averaged and output as new 1-line data L3 ′.

Also in the case of integration of m = 8, FIGS. 18 (c) and 18 (d)
Are similarly performed using the control signals CTL ₁ and CTL ₂ of
The line data L1 to L8 are integrated and averaged and output as new 1-line data L1 ″.
~ L16 is integrated and averaged to create new 1-line data L2 "
Output as

In the above-described processing, the data written in the memory of the integration / averaging means 43 is updated every time one line data is input. One line is enough. In addition, since the number of bits of line data increases as integration is performed, for example, the number of data buses (bit number) is prepared in advance according to the number of integrations. For example, when m = 16, 4 bits are additionally required.

As described above, when the original image is a multi-valued image,
The original image is 2 after the integration processing by the integration and averaging means is executed.
In the case of the value image, by omitting the integration processing by the integration and averaging means, better reading quality can be obtained in the multivalued image and the reading time can be shortened in the binary image.

In each of the above-described embodiments and configuration examples, the clock switching means 18 switches the clock for the CCD sensor 7 in accordance with the discrimination result from the document image discrimination means 17. Instead of this, it is also possible to control the light amount of the light source 4 according to the discrimination result from the document image discrimination means 17.

FIG. 19 is a diagram showing a configuration example of such an image input device. Referring to FIG. 19, a light source control unit 47 is provided in place of the clock switching unit 18 of FIG. 1, and the light source control unit 47 outputs a determination result that a document image is multi-valued during prescan. Then, at the time of fine scanning, the light source 4 is controlled so that the light amount of the light source 4 becomes a preset light amount, and at the time of pre-scanning, the document image discriminating means 17 determines that the document image is binary. When output, the light source 4 is controlled so as to reduce the light amount of the light source 4 during fine scanning as compared with the case of a multi-valued image.

With such a configuration, since the original image is read with an optimum light amount according to the type of the original image, a good original image can be obtained and the original image is 2
In the case of the value image, the light amount of the light source is made lower than that in the case of the multi-value image, so that heat generation of the device can be prevented and the power consumption can be saved.

Further, as shown in FIG. 20 by combining FIG. 1 and FIG. 19, the clock switching means 18 switches the clock according to the discrimination result from the document image discrimination means 17, and the light amount is changed. It is also possible to control the light amount of the light source 4 by the control means 47. With such a configuration, when the original image is a binary image, the sensor driving clock is switched to a high-speed clock, and the light amount of the light source is set to be lower than that in the case of a multi-valued image, so that the original image data is read. The time can be shortened, and the original image is read with the optimum light amount according to the type of the original image, so that a good original image can be obtained, and
It is possible to prevent heat generation of the device and save power.

In each of the above-described embodiments and configuration examples, the original image discriminating means 17 is provided in the preceding stage of the A / D conversion circuit 9. Therefore, the original image discriminating means 17 uses the analog signal to output the original image 2 Although it is determined whether the original image is multivalued or not, the original image discriminating means 17 is provided in the subsequent stage of the A / D conversion circuit 9 and configured to discriminate whether the original image is binary or multivalued by using a digital signal. You can also

In each of the above-mentioned embodiments and configuration examples,
Instead of the document image discrimination means 17, it is also possible to use an image data designating means for instructing from the outside whether the document is a binary image or a multi-valued image. In FIG. 21, FIG.
In the configuration example of the above, instead of the document image discrimination means 17,
An image input device provided with an image data instructing means 60 for instructing to input the type of a document image from the outside is shown.

In the image input device as shown in FIG. 21, when the type of the original image is designated from the outside, the type of the original image is given to the clock switching means 18. As a result, the clock switching unit 18 switches the clock according to the type of document image. Specifically, the image data instruction means 60
When a binary image is designated from the outside by the, the clock switching means 18 switches the clock to the high-speed clock CLK ₂ , and thereby high-speed reading can be performed. Further, in the image input device of FIG. 21 provided with the externally input image data instructing means 60, when the simple reading mode is provided as the reading mode, when the binary image is instructed from the outside, the pre-scan is not executed. No
Fine scan can be performed immediately.

Further, in each of the above-described embodiments and configuration examples, the original image is obtained by the reflected light from the original 1, but the original image is obtained by the light (transmitted light) transmitted through the original 1 depending on the type of the original 1. It is also possible to obtain an image.

Although the CCD sensor is used as the image sensor in each of the above-described embodiments and configuration examples, it is possible to use an image sensor other than the CCD sensor. Further, the image pickup device and the sample hold circuit 8 can be included and can be regarded as an image pickup unit for reading an original image as an image pickup.

[0087]

As described above, according to the first and second aspects of the invention, the image pickup means for picking up and reading the original image and the original image are binary images or multivalued images. The driving clock of the image pickup means is set to a high-speed clock according to the manuscript image discrimination means for discriminating whether there is an image, and whether the discrimination result of the manuscript image in the manuscript image discrimination means is a binary image or a multivalued image. Or a clock switching means for switching to a low-speed clock, and the original image discrimination means compares the pixel density level from the imaging means with a preset black reference and white reference, respectively, and Since it is detected whether the original image is a multi-valued image or a binary image on the basis of whether or not it is at a halftone level between the black reference and the white reference, it is possible to detect whether the original image is a multi-valued image. Value image or binary image Whether or accurately determined, performs accurately clock switching selection can be performed accurately image input. In particular, the document image discriminating means can be made to have a simple structure, and multi-valued / binary discrimination of the document image can be easily performed in real time.

According to the third aspect of the invention, as the black reference and the white reference, the average value of the pixel density levels of each pixel in the black reference read image and the pixel density level of each pixel in the white reference read image are used. Since the respective average values of are used, it is possible to more stably discriminate between multi-value and binary.

According to the fourth aspect of the invention, the original image discrimination means is the number of pixels or the halftone of which the pixel density level from the image pickup means is in the halftone level between the black reference and the white reference. The number of pixels that are not in the level is counted, and when the count value is larger than a predetermined threshold value, it is discriminated as a multi-valued image or a binary image, and when it is not larger than the predetermined threshold value, 2
Since it is determined that the original image is a binary image or a multi-valued image, it is possible to reliably determine whether the original image is a binary image or a multi-valued image.

According to the fifth aspect of the invention, the original image discriminating means counts the number of consecutive pixels whose pixel density level from the image pickup means is at the halftone level or not. However, when the count value is larger than a predetermined threshold value, it is determined as a multi-valued image or a binary image,
Since the image is determined to be a binary image or a multi-valued image when it is not larger than the predetermined threshold value, it is possible to reliably determine whether the original image is a binary image or a multi-valued image.

According to the sixth and seventh aspects of the present invention, the type of the original image can be easily designated by external input, and the fine scan can be directly performed without performing the prescan. Even in this case, it is possible to perform accurate image input.

According to the invention described in claim 8, A /
A D conversion means, a binarization means, and a bit distribution means are provided, and when a document image is discriminated as a multivalued image by the document image discrimination means, or a multivalued image by the image data instruction means. Is output, the output signal from the image pickup means is digitized by the A / D conversion means, and the original image is detected by the original image discriminating means.
When it is determined that the image is a value image, or when the image data instructing unit indicates a binary image, the output signal from the image capturing unit is binarized by the binarizing unit,
The binarized data is made to be multi-bit by the bit distribution means. In the configuration example of FIG. 14, the binary image data is subjected to high-speed digital conversion processing by the binarization means and the distribution means. Since the A / D conversion means is used only for digital conversion processing for multi-valued image data which is not required to be as fast as binary image data,
It is not necessary to use an expensive high-speed A / D converter as the conversion means, and the image input device can be made low in cost. That is, binary image data can be digitally converted at high speed without using a high-speed A / D converter, and optimum image input can be performed for both binary and multi-valued images. .

According to the invention of claim 9, A /
The digital output from the binarizing unit is synchronized with the D converting unit, the frequency dividing unit that divides the clock synchronized with the pixel by n, the binarizing unit, and the frequency dividing signal from the frequency dividing unit. A serial / parallel conversion means for collectively outputting in pixel units, a storage device, and an address generation means for generating an address of the storage device are provided, and the document image is discriminated as a multi-valued image by the document image discrimination means. In the case, or when the image data instructing means indicates a multi-valued image, the output signal from the imaging means is digitized by the A / D converting means and given to the storage device, and the address generating means , A clock synchronized with the pixel is added, and the address generation means generates the address of the storage device in synchronization with one pixel, whereby A is added to one address of the storage device.
When one pixel of digital data from the / D conversion means is stored and the original image is discriminated by the original image discrimination means as a binary image, or when the image data instruction means indicates a binary image. In addition, the output signal from the image pickup means is digitized by the binarization means, the output from the binarization means is given to the storage device in n-pixel units by the serial-parallel conversion means, and the address generation means , A frequency-divided clock obtained by frequency-dividing a clock synchronized with the pixel by the frequency dividing means is added, and the address generating means generates an address of the memory device in units of n pixels, whereby one address of the memory device is generated. Digital data for n pixels from the serial / parallel conversion means is stored, and binary image data can be digitally converted at high speed by the binarization means and the serial / parallel conversion means. Is, A / D conversion means, since only used digitally converting the multivalued image data that is not high-speed requirements smaller the difference in comparison with the binary image data, A
It is not necessary to use an expensive high-speed A / D converter for the / D conversion means, and the image input device can be manufactured at low cost. That is, as in the invention according to claim 8, A /
Binary image data can be digitally converted at high speed without using a high-speed D conversion means.
Optimal image input can be performed for both multi-valued images. Further, in the invention described in claim 9, when the original image is a binary image, the sensor output is digitized by a binarizing circuit, and n pixel data is stored in a memory device having n bit memory cells for one memory address. By storing the data, it is possible to obtain a stable image with a large reading area (a large number of reading pixels) without requiring a large-capacity storage device.

According to the tenth aspect of the invention, the binarizing means averages the pixel density level of the black reference read image read at the start of the fine scan and the average pixel density level of the white reference read image. Since the output signal from the image pickup means is digitized on the basis of the value, even when the sensor driving clock is switched to the high-speed clock CLK ₂ , or when a light source fluctuation or the like occurs, the binarization is always appropriate. Is performed and a stable image can be obtained.

According to the eleventh aspect of the present invention, when the original image is a multi-valued image, the integrating process is executed by the integrating and averaging means, and when the original image is a binary image, the integrating and averaging means integrates it. By not performing the process, it is possible to obtain better reading quality in the multi-valued image and shorten the reading time in the binary image.

According to the twelfth aspect of the invention, since the original image is read with an optimum light amount according to the type of the original image, a good original image can be obtained and the original image is binary. In the case of an image, by making the light amount of the light source lower than that in the case of a multi-valued image, it is possible to prevent heat generation of the device and save power.

According to the thirteenth aspect of the invention, when the original image is a binary image, the sensor drive clock is switched to the high speed clock, and the light amount of the light source is made lower than that in the case of the multivalued image. As a result, the reading time can be shortened according to the original image data, and the original image can be read with the optimum light amount according to the type of the original image, so that a good original image can be obtained and the heat of the apparatus can be prevented. It is possible to prevent the power consumption and save electricity.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of an image input device according to the present invention.

FIG. 2 is a diagram showing a configuration example of a document image discrimination means.

FIG. 3 is a diagram for explaining the operation of a sample hold circuit.

FIG. 4 is a diagram showing a halftone region of an image.

FIG. 5 is a diagram for explaining how to determine a document image.

FIG. 6 is a diagram for explaining how to determine a document image.

FIG. 7 is a diagram illustrating a method of determining a document image.

FIG. 8 is a diagram showing a low-speed clock and a high-speed clock.

FIG. 9 is a diagram showing another configuration example of the document image discrimination means.

FIG. 10 is a diagram showing another configuration example of the document image discrimination means.

FIG. 11 is a diagram for explaining how to determine a document image.

FIG. 12 is a diagram for explaining how to determine a document image.

FIG. 13 is a diagram for explaining how to determine a document image.

FIG. 14 is a partial configuration diagram of another embodiment of the image input device according to the invention.

FIG. 15 is a diagram showing a modification of the image input device of FIG.

16 is a time chart for explaining the operation of the image input device in FIG.

FIG. 17 is a configuration diagram of another embodiment of the image input device according to the invention.

FIG. 18 is a time chart for explaining a cumulative averaging process.

FIG. 19 is a configuration diagram of another embodiment of the image input device according to the invention.

FIG. 20 is a configuration diagram of another embodiment of the image input device according to the invention.

FIG. 21 is a configuration diagram of another embodiment of the image input device according to the invention.

[Explanation of symbols]

 1 Document 2 Document Platen 3 Mirror 4 Light Source 5 Motor 6 Imaging Lens 7 CCD Sensor 8 Sample Hold Circuit 9 A / D Conversion Circuit 10 Dark Output Correction Circuit 11 Shading Correction Circuit 12 Linear Density Conversion Circuit 13 Interface Circuit 14 Light Source Driving Circuit 15 Motor drive control unit 16 CCD drive circuit 17 Original image discrimination means 18 Clock switching means 21 First comparator 22 Second comparator 23 Exclusive OR circuit 24 Latch circuit 25 Detector 27 Counter 29 Integrators 31, 32, 40 switch means 33 binarization circuit 34 distributor 36 external storage device 38 serial-parallel converter 39 frequency divider 43 integrating and averaging means 45 line integrating and averaging means 47 light source control means

Claims (13)

[Claims] 1. An image pickup unit for picking up and reading a document image, a document image discriminating unit for discriminating whether the document image is a binary image or a multi-valued image, and discriminating the document image in the document image discriminating unit. A manuscript image discriminating means, and a clock switching means for switching a driving clock of the image pickup means to a high speed clock or a low speed clock depending on whether the result is a binary image or a multivalued image. Pixel density levels from the image pickup means are respectively compared with preset black reference and white reference, and based on whether or not the pixel density level is a halftone level between the black reference and the white reference, An image input device, which is adapted to detect whether a document image is a multi-valued image or a binary image. 2. The image input device according to claim 1,
An image input device characterized in that a maximum value of a pixel density level in a black reference read image and a minimum value of a pixel density level in a white reference read image are used as the black reference and the white reference, respectively. 3. The image input device according to claim 1, wherein
As the black reference and the white reference, the average value of the pixel density level of each pixel in the black reference read image and the average value of the pixel density level of each pixel in the white reference read image are used, respectively. . 4. The image input device according to claim 1,
The original image discrimination means counts the number of pixels whose pixel density level from the image pickup means is in a halftone level between the black reference and the white reference or the number of pixels which are not in the halftone level,
An image input device characterized in that when the count value is larger than a predetermined threshold value, it is discriminated as a multi-valued image or a binary image, and when it is not larger than a predetermined threshold value, it is discriminated as a binary image or a multi-valued image. 5. The image input device according to claim 1, wherein
The document image discrimination means counts the number of consecutive pixels whose pixel density level from the image pickup means is at the halftone level or is not at the halftone level, and when the counted value becomes larger than a predetermined threshold value, it is often determined. An image input device characterized by being discriminated as a value image or a binary image, and discriminated as a binary image or a multi-valued image when it is not larger than a predetermined threshold value. 6. An image pickup means for picking up and reading an original image, an image data instructing means for instructing whether the original image is a binary image or a multivalued image by an external input, and the image data instructing means. And a clock switching means for switching the driving clock of the image pickup means to a high-speed clock or a low-speed clock according to the instruction of whether the image is a binary image or a multi-valued image. Image input device. 7. The image input device according to claim 6,
An image input device, wherein when a binary image is instructed by the image data instructing means, a fine scan is directly performed without performing a prescan. 8. The image input device according to claim 1 or 6, further comprising an A / D conversion means, a binarization means, and a bit distribution means, and the original image is the original image. When it is judged as a multi-valued image by the judgment means,
Alternatively, when a multi-valued image is instructed by the image data instructing means, the output signal from the imaging means is set to the A
If the document image is digitized by the D / D conversion unit and the document image is discriminated by the document image discrimination unit,
Alternatively, when the image data instructing means instructs a binary image, the output signal from the imaging means is changed to the
An image input device, wherein the binarizing means binarizes the binarized data and the bit distributing means multi-bits the binarized data. 9. The image input device according to claim 1, further comprising an A / D conversion unit, a frequency dividing unit that divides a clock synchronized with a pixel by n, and a binarizing unit.
A serial / parallel conversion means for collectively outputting the digital output from the binarization means in units of n pixels in synchronization with the frequency division signal from the frequency division means, a storage device, and an address generation for generating an address of the storage device. Means is provided, and when the document image is discriminated as a multi-valued image by the document image discriminating means, or when the image data instructing means instructs the document image as a multi-valued image, Output signal is A
The data is digitized by the D / D conversion means and given to the storage device, and a clock synchronized with the pixel is added to the address generation means, and the address generation means generates the address of the storage device in synchronization with one pixel. By this, when one pixel of digital data from the A / D conversion means is stored in one address of the storage device, and when the document image is discriminated by the document image discrimination means as a binary image, or When the instruction means indicates a binary image, the output signal from the image pickup means is digitized by the binarization means, and the output from the binarization means is stored in n-pixel units by the serial / parallel conversion means. A frequency-divided clock obtained by frequency-dividing a clock synchronized with a pixel by the frequency-dividing means is added to the address generating means. Generates an address of the storage device, thereby, an image input apparatus characterized by storing the n pixels of the digital data from the serial-parallel conversion means into one address of the memory device. 10. The image input device according to claim 8 or 9, wherein the binarizing unit averages the pixel density levels of the black reference read image read at the start of the fine scan and the pixels of the white reference read image. An image input device, wherein an output signal from the image pickup means is digitized based on an average value of density levels. 11. The image input apparatus according to claim 1 or 6, wherein the line signals imaged and read by the image pickup means are integrated and averaged in a sub-scanning direction for a predetermined number of lines, and the integrated and averaged. A cumulative averaging unit that outputs a new one-line signal is further provided, and when the document image is discriminated by the document image discriminating unit as a multivalued image, or by the image data instructing unit. The image input device is characterized in that the integrated averaging processing is executed by the integrated averaging means when the above is instructed. 12. The image input apparatus according to claim 1 or 6, wherein a light source control means is provided instead of the clock switching means, and the document image discrimination means discriminates the document image as a binary image. In this case, or when a binary image is instructed by the image data instructing means, the light source control means reads the original image by lowering the light amount of the light source as compared with the reading of the multivalued image. Image input device. 13. The image input device according to claim 1 or 6, further comprising a light source control means, when the document image discrimination means discriminates the document image as a binary image, or image data. The image input device wherein the light source control means reads the image by lowering the light amount of the light source when reading the multi-valued image when the instruction means indicates the binary image.