JPH08265392A - Hdlc frame processor - Google Patents

Abstract

PURPOSE: To provide an HDLC frame processor which is capable of processing frame data at high speed. CONSTITUTION: The sizes of a primary buffer 2 and a secondary buffer 3 are set so that the total sizes of the both buffers may be larger than a one-frame data maximum length, the size of the secondary buffer 3 is made larger than that of the primary buffer 2, the number of surfaces of the primary buffer 2 is increased and the number of surfaces of the secondary buffer 3 is decreased. A writing processing part 6 and a reading processing part 8 use the primary buffer 2 and the secondary buffer 3 in turn, and when the one-frame data length exceeds the size of the primary buffer 2, the secondary buffer 3 is also used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to HDLC (high-
HDLC for storing / reading frame data in level data link control)
The present invention relates to a frame processing device.

[0002]

2. Description of the Related Art HDLC frames (LAPB frames,
A conventional configuration of a memory (frame buffer) that stores frame data in a device that processes LAPD frames and the like will be described below. FIG. 3 is a block diagram showing a buffer configuration of a conventional frame processing device.

This is because the frame data 201 having a certain size has a plurality of large size buffers 203 having a size larger than the maximum frame length as the frame buffer 202, and a large size buffer 203 is stored in order to store the frame data 201 of one frame. One side of the buffer 203 is used. At the start of writing the frame data to the frame buffer 202, a write processing unit (not shown) hunts one empty large size buffer 203 from the empty buffer pool and writes the frame data from the head position of the buffer.

After the frame data writing is completed, a buffer number and an offset from the beginning of the page (hereinafter referred to as a final pointer) are notified to a reading processing unit (not shown) as frame management information. In the frame data read from the frame buffer 202, the above-mentioned read processing unit reads from the head to the last pointer of the buffer notified from the write processing unit, and releases the buffer to the free buffer pool.

FIG. 4 is a block diagram showing another buffer structure of a conventional frame processing device. This has a large number of memory blocks of the same size (hereinafter referred to as page 303) as a frame buffer 302 for a frame data 301 having a certain size, and a chain of pages 303 having the number of pages according to the frame length. , Frame data 3
01 is stored, and each page 303 of the frame buffer 302 has a chain presence flag, a next page number, and a final pointer (only in the case of the final page) as management information.

At the start of writing frame data, a write processing unit (not shown) hunts an empty page from the empty page pool, stores the page number as the first page number of frame management information, and stores the frame data from the beginning of the page. To write. If you write to the end of the page and still have frame data, hunt a new page from the free page pool again. Then, the chain presence / absence flag of the management information of the written page is set to “with chain”, and the newly hunted new page number is written to the next page number of the management information of the written page. This chain process is repeated as long as the frame data continues.

When the final data of the frame has been written, the chain presence flag of the management information of the page being written is set to "no chain", and the final write pointer is written to the final pointer of the management information of the page being written. Then, the first page number of the frame management information stored in advance is notified to a read processing unit (not shown).

In reading the frame data from the frame buffer 302, the above-described read processing unit first sets the first page number of the frame management information received from the write processing unit as the read page. And the chain presence flag of the management information of the page is "no chain"
In this case, the final pointer of the management information is read, the frame data is read up to the final pointer, and the data read processing is completed. Then, the page is released to the free page pool.

When the chain presence flag of the management information of the page is "chained", the next page number of the management information is read and the frame data is read to the end of the page. Then, the page is released to the free page pool. Subsequently, the next page is set as a read page, and the same processing is repeated until the chain presence flag of the management information of the page becomes “no chain”.

[0010]

However, with the first conventional buffer configuration, even when storing frame data of any size, one frame buffer larger than the maximum frame length is used, and therefore, the maximum frame length is increased. When storing short frame data in a frame buffer having a large length, the frame buffer is less efficiently used.

Further, since a large number of buffers must be provided in order to realize sufficient throughput, a large-capacity frame buffer memory is required, resulting in high cost. With the conventional second buffer configuration, the chain processing of the frame buffer is complicated and the memory for storing the management information is accessed many times, so a high-speed (short access time) memory is required. Therefore, it is difficult to apply it to a system that processes frame data at high speed.

[0012]

In order to solve the above-mentioned problems, the present invention provides an HDLC frame processing apparatus equipped with a buffer for processing data transmitted in frame units. Each buffer size is set so that the total size of the above buffers is larger than the maximum length of one frame data, and a buffer of a plurality of planes is provided for a plurality of frame data, and one frame data is determined as described above. Among the buffers having the different number of surfaces, a processing unit that uses each buffer once in order is provided.

[0013]

According to the present invention having the above-described structure, a buffer having a predetermined number of planes is assigned to one frame data and the order of using the buffers is decided.
When receiving frame data, first store the data in a buffer that is determined to store the data, and if the frame data has a length that cannot be stored in this buffer, store it in the next buffer. Then, one frame data is stored in a buffer having a predetermined number of faces.

[0014]

FIG. 1 is a block diagram of a frame processing device representing a first embodiment of the present invention, which is applied to a device for processing a LAPB frame. Where now L
The maximum I (information) field length of the APB frame is 409.
Since it is 9 bytes, when the AC (address, control) field is 3 bytes, a maximum of 4102 bytes is required to store one frame as a frame buffer.

A frame buffer 1 is composed of a primary buffer 2 having a size of several tens to several hundreds of bytes and a secondary buffer 3 having a size of several kbytes. The primary buffer 2 is composed of a plurality of buffers of the same size, and the secondary buffer 3 is composed of a buffer of a plurality of surfaces of the same size.
Is used with a relatively low frequency, and is configured with a smaller number of surfaces than the primary buffer 2. Then, the sum of the size of one side of the primary buffer 2 and the size of one side of the secondary buffer 3 is set to be larger than the maximum frame length (4102 bytes), and both the primary buffer 2 and the secondary buffer 3 are set. If used, one frame data can be stored. The size and the number of surfaces of the primary buffer 2 and the secondary buffer 3 are determined by the traffic conditions of the applicable system.

A frame buffer management unit 4 manages the empty primary buffer and the empty secondary buffer in the primary buffer 2 and the secondary buffer 3. The frame buffer management unit 4 is connected to the write processing unit 6 via the transmission line 5, connected to the read processing unit 8 via the transmission line 7, connected to the primary buffer 2 via the transmission line 9, and the transmission line 10
Is connected to the secondary buffer 3 by.

The write processing unit 6 receives the frame data of the LAPB frame via the transmission line 11. The read processing unit 8 also transmits the frame data of the LAPB frame via the transmission line 12. When storing one frame data, the write processing unit 6 first stores it in the primary buffer 2 and then stores it in the secondary buffer 3, and so on. And the secondary buffer 3 is used in order. As a result, when the 1-frame data length does not exceed the size of the primary buffer 2, only the primary buffer 2 is used and 1
If the frame data length exceeds the size of the primary buffer 2, the secondary buffer 3 is also used. Further, when reading one frame data, the read processing unit 8 first reads from the primary buffer 2 and then from the secondary buffer 3 so that one frame data is read from the primary buffer 2 and then read from the secondary buffer 3. The secondary buffer 3 is used in order.

At this time, the read processing unit 8 reads the frame data based on the management information notified from the write processing unit 6, but the number of buffers required for one frame data is determined in advance. , And if you decide the order of using the primary and secondary buffers,
Since the information required as the management information can be reduced, the access to the management information by the read processing unit 8 can be reduced.

According to the above configuration, L is provided via the transmission line 11.
When receiving the frame data of the APB frame,
The write processing unit 6 first writes the frame data in the empty primary buffer 2 via the frame buffer management unit 4. When the frame data continues beyond the size of one side of the primary buffer 2, the write processing unit 6 writes the rest of the frame data to the empty secondary buffer 3 via the frame buffer management unit 4. Here, as mentioned above,
Since the sum of the size of one side of the primary buffer 2 and the size of one side of the secondary buffer 3 is set to be larger than the maximum frame length, one frame data is stored in both the primary buffer 2 and the secondary buffer 3. If used, they can be stored without fail, and the primary buffer 2 is stored first.

When receiving the frame data of the LAPB frame, the write processing unit 6 indicates the number of the primary buffer 2 used and the secondary buffer use flag (whether the secondary buffer is used or not) as management information. ), The number of the used secondary buffer 3 and the information of the final pointer are sent to the read processing unit 8 to notify the writing of the frame data to the frame buffer 1.

Here, the read processing unit 8 has a management information memory for storing the above-mentioned management information. The frame buffer management unit 4 may have it. When the read processing unit 8 reads frame data from the frame buffer 1, the management information received from the write processing unit 6 and stored in the management information memory is accessed,
When the corresponding primary buffer 2 is read from the primary buffer number and the secondary buffer is not used by referring to the secondary buffer use flag, the final pointer is read and the frame data is read up to the final pointer. , Data read processing is completed. When the secondary buffer is used, the relevant secondary buffer 3 is read from the secondary buffer number, the final pointer is read, the frame data is read up to the final pointer, and the data read processing is completed.

As described above, in this embodiment, two types of buffers are used for one frame depending on the frame length, and these buffers are used as the primary buffer and the secondary buffer, and when receiving frame data. If you use the primary buffer first, and then use the secondary buffer if the frame data has a length that cannot be stored in the primary buffer, you will need complicated chain processing if you use it one by one in this order. Since the number of accesses to the management information memory is reduced, it is possible to use a relatively low-speed (long access time) memory as the management information memory and apply it to a high-speed frame processing system. In particular, when applied to a system that transmits and receives frames of multiple channels by time division multiplexing, access to the management information necessary for channel switching of frame buffer access and buffer management information necessary for hunting a new buffer However, in the present embodiment, since the chain processing associated with the new buffer hunt is not performed, the processing is not complicated and is very effective.

Further, the primary buffer 2 is a small size buffer, the secondary buffer 3 is a large size buffer, only the primary buffer 2 is used for a short frame, and a long frame with a small occurrence frequency (size of the primary buffer is used). If the secondary buffer 3 is also used only in the case of (larger than 1), a large number of small-sized primary buffers 2 are required, but a small number of large-sized secondary buffers 3 are sufficient, and buffer memory usage efficiency is increased. Can be expected to improve.

In the above-described embodiment, the case where the invention is applied to the apparatus that processes the LAPB frame has been described, but the invention can also be applied to the apparatus that processes the LAPD frame by changing the buffer size. FIG. 2 is a block diagram of a frame processing device showing a second embodiment of the present invention.
This is the case when applied to a device that processes PD frames.

CCITT Recommendation Q. Since the maximum I-field length of the LAPD frame is 260 bytes (default) according to 921, when the AC field is 4 bytes, a maximum of 264 bytes is required to store one frame as a frame buffer. Therefore, 1
The total size of one side of the secondary buffer and the size of one side of the secondary buffer is set to be larger than the maximum frame length (264 bytes), and the primary buffers have the same size (10 to 10).
It can be applied to a LAPD frame processing device by being configured with a plurality of buffers of several hundred bytes) and the secondary buffer with a plurality of buffers of the same size (several tens to several hundred bytes).

That is, 21 is a frame buffer, and the frame buffer 21 is composed of a primary buffer 22 having a size of several tens to several hundreds of bytes and a secondary buffer 23 having a size of several tens to several hundreds of bytes. The primary buffer 22 is composed of a plurality of buffers of the same size.
The next buffer 23 is composed of a plurality of buffers of the same size.

The sum of the size of one side of the primary buffer 22 and the size of one side of the secondary buffer 23 is made larger than the maximum frame length (264 bytes).
If both the secondary buffer 22 and the secondary buffer 23 are used,
One frame data can be stored. It should be noted that the size and the number of surfaces of the primary buffer 22 and the secondary buffer 23 are determined by the traffic conditions of the applied system.

Reference numeral 24 is a frame buffer management unit,
The empty primary buffer and the empty secondary buffer in the next buffer 22 and the secondary buffer 23 are managed. The frame buffer management unit 24 is connected to the write processing unit 26 via a transmission line 25, and the read processing unit 28 via a transmission line 27.
Connected to the primary buffer 22 via a transmission line 29, and connected to the secondary buffer 23 via a transmission line 30.

The write processing unit 26 receives the frame data of the LAPD frame via the transmission line 31.
Further, the read processing unit 28 uses the LAP via the transmission line 32.
The frame data of the D frame is transmitted. According to the above configuration, when the frame data of the LAPD frame starts to be received via the transmission path 31, the write processing unit 26 causes the empty primary buffer 2 to operate via the frame buffer management unit 24.
Write the frame data to 2. Frame data is 1
When continuing beyond the size of one side of the next buffer 22,
The write processing unit 26 writes the rest of the frame data to the empty secondary buffer 23 via the frame buffer management unit 24.

When receiving the frame data of the LAPD frame, the write processing unit 26 stores the management information as the management information.
The number of the primary buffer 22 used, the secondary buffer use flag (indicating whether or not the secondary buffer is used), the number of the secondary buffer 23 used, and the information of the final pointer are sent to the read processing unit 28, and the frame The writing of frame data to the buffer 21 is notified.

Here, the read processing unit 28 has a management information memory for storing the above-mentioned management information.
Note that the frame buffer management unit 24 may have it. When the read processing unit 28 reads the frame data from the frame buffer 21, the write processing unit 26
When the management information received from the management information memory is stored in the management information memory, the corresponding primary buffer 22 is read from the primary buffer number, and the secondary buffer 23 is not used by referring to the secondary buffer use flag. Reads the final pointer, reads the frame data up to the final pointer, and completes the data read processing. When the secondary buffer 23 is used, the corresponding secondary buffer 23 is read from the secondary buffer number, the final pointer is read, the frame data is read up to the final pointer, and the data read processing is completed. .

As described above, even in a device that processes LAPD frames, two types of buffers are used for one frame data, and these buffers are used as primary buffers and secondary buffers, one by one. When used in this order, complicated chain processing is not required and the number of accesses to the management information memory is reduced. Therefore, a relatively slow (long access time) memory is used as the management information memory, and a high-speed frame processing system is used. Can be applied to.

In each of the above-mentioned embodiments, two types of buffers are used one by one, and a maximum of two buffers are used according to the length of the frame data, but one frame is used. Up to 3 for data
Two or more types of buffers may be used one by one, if it is determined in advance how many buffers are to be assigned to one frame data, such as four or four.

That is, in the conventional page system, it is necessary to provide management information corresponding to each buffer to check whether another buffer is used and which buffer is used. Will increase,
If the number of buffers to be used for one frame data is determined and the access order is determined, even if one frame data is stored in multiple buffers, it can be used for each buffer. You don't have to have management information to reduce the number of accesses,
It becomes possible to process frame data at high speed.

[0035]

As described above, according to the present invention, each buffer size is set so that the total size of two or more kinds of buffers having a predetermined number of faces is larger than the maximum length of one frame data, A buffer for a plurality of planes is provided for a plurality of frame data, and for each frame data, it is decided to use each of the buffers once in order among the buffers having the predetermined number of planes. Even if you store the data in multiple buffers,
It is not necessary to perform complicated chain processing and can be applied to a system that processes frames at high speed.

Further, since it is not necessary to use a large capacity frame buffer, the cost can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram of a frame processing device representing a first embodiment of the present invention.

FIG. 2 is a block diagram of a frame processing device representing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a buffer configuration of a conventional frame processing device.

FIG. 4 is a block diagram showing another buffer configuration of a conventional frame processing device.

[Explanation of symbols]

 1 frame buffer 2 primary buffer 3 secondary buffer 4 frame buffer management unit 6 write processing unit 8 read processing unit

Claims (2)

[Claims] 1. An HDLC frame processing apparatus having a buffer for processing data transmitted in frame units, wherein the total size of two or more buffers having a predetermined number of planes is larger than the maximum length of one frame data. Each buffer size is set as described above, and a buffer for a plurality of planes is provided for a plurality of frame data. For one frame data, each buffer is once in sequence among the buffers with the determined number of planes. An HDLC frame processing device comprising a processing unit that uses each of them. 2. The HDLC frame processing device according to claim 1, wherein the size of the buffer is different, and the number of large size buffers is smaller than the number of small size buffers.