JPH08265153A - A/d conversion method - Google Patents

Abstract

PURPOSE: To reduce noise of an analog signal by converting a signal obtained by shifting a phase of a clock signal by 360/N degrees each into digital data and by calculating a mean value of N-sets of the digital data. CONSTITUTION: A clock signal S1 generated by a clock generator 2 is fed to a phase conversion circuit 11. The circuit 11 shifts the phase of the signal S1 by 360/N degrees each sequentially and the resulting signals are respectively fed to N-sets of A/D converters 3A1 -3An . The A/D converters 3A1 -3An make conversion synchronously with a clock signal corresponding to the analog signal. The phase of reference data being one of the obtained N-sets of the digital data is used to match the phases of the other remaining (N-1) sets of digital data by interpolating the other remaining data based on the phase of the reference data. A digital signal processor 5 calculates the mean value of the N-sets of the data whose phases are matched and provides an output of the mean value. Thus, the mean value of the N-sets of the digital data is improved for the signal component by 3×NdB and for the noise component by 3/2×NdB.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problem to be Solved by the Invention Means for Solving the Problem (FIGS. 1 to 12) Action (FIGS. 1 to 12) Working Example (1) First Working Example (1-1) ) When using two AD converters (FIGS. 1 and 2) (1-2) When using N AD converters (FIGS.
(FIG. 5) (1-3) Operation of the first embodiment (FIG. 6) (1-4) Effect of the first embodiment (2) Second embodiment (2-1) When using two AD converters ( (FIG. 7) (2-2) When N AD converters are used (FIG. 8) (2-3) Operation of second embodiment (FIGS. 9 and 10) (2-4) Effect of second embodiment 3) Third embodiment (3-1) When using two AD converters (see FIG. 1)
1) (3-2) When using N AD converters (see FIG. 1)
2) (3-3) Operation of the third embodiment (3-4) Effect of the third embodiment (4) Other embodiment Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog digital conversion method, which is suitable for analog digital conversion using, for example, an analog digital converter used for audio equipment.

[0003]

2. Description of the Related Art Currently, as an analog digital (AD) converter used for audio equipment, 20 [bi
There is proposed a high-resolution IC such as t] or 24 [bit]. However, 20 [bit] or 24 [bi
The theoretical S / N (Signal Noi
It is very difficult at present to obtain the se ratio). For example, since the theoretical value of S / N obtained by quantizing n [bit] is generally expressed by 6.02 × n + 1.7 [dB],
The theoretical value of S / N in the case of [bit] is 6.02 × 20 + 1.7 = 12
It becomes 2.1 [dB]. However, in practice, the S / N in the case of 20 [bit] obtained by the AD converter is 110-115.
It will be about [dB].

[0004]

It is considered that white noise such as thermal noise of an analog system is a major factor that cannot reduce the noise of the analog signal during the AD conversion as described above. Generation of thermal noise is unavoidable due to the use of devices such as resistors and transistors. Therefore, in order to reduce this, an advanced technique such as trimming the device used inside the chip of the IC to match the theoretical value of S / N is required. Further, there is a technical limit to suppressing such analog noise, and a theoretical limit value of S / N obtained by quantizing 20 [bit], 24 [bit], etc. is obtained. Had a very difficult problem.

The present invention has been made in view of the above points, and is intended to propose an analog digital conversion method capable of reducing the noise of an analog signal by using an existing AD converter when performing analog digital conversion. is there.

[0006]

In order to solve such a problem, in the present invention, the phase of a predetermined clock signal is set to 360
/ N ° (N is a natural number) are sequentially shifted, and each analog signal is converted into N digital data in synchronism with N clock signals obtained, and subsequently one of the N digital data is digital data. After the other remaining (N-1) digital data are interpolated with respect to each other and the phase is adjusted to one reference digital data, the average value of the N digital data after the phases are adjusted. To be calculated.

[0007]

In operation, the analog signals are converted into N digital data in synchronization with N clock signals obtained by sequentially shifting the phase of a predetermined clock signal by 360 / N ° (N is a natural number), Of the N digital data, one digital data is used as a reference and the other (N-
1) Interpolation of 1 digital data is used as the reference 1
After the phase is adjusted to each of the digital data, the average value of the N digital data after the phases are adjusted is calculated, so that the S / N in the average value of the N digital data is calculated as a signal component. Can be improved by subtracting the level of the noise component from the level of. As a result, it is possible to reduce the noise of the analog signal by using the existing AD converter when performing the analog digital conversion.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment (1-1) When Two AD Converters are Used The signal processing circuit 1 is shown in FIG. 1 (A), and the clock signal S1 generated in the clock generator 2 is
The clock signal S1 is sent to the D converter 3A ₁ and the clock signal S2 obtained by inverting the phase of the clock signal S1 via the inverter 4 is sent to the AD converter 3A ₂ . A
The D converters 3A ₁ and 3A ₂ have rising edges of the clock signals S1 and S2 which are 180 ° out of phase with each other (see FIG.
(B)) in synchronization with the analog signal S3 from the outside.
Is to be entered. Incidentally, the AD converters 3A ₁ and 3A ₂ have the same configuration.

Then, the AD converters 3A ₁ and 3A
_After sampling and quantizing the input analog signal S3 and AD-converting the analog signal S3, the signal ₂ is sent to the digital signal processing processor (DSP) 5 as digital data S4A ₁ and S4A ₂ . The digital signal processing processor 5 interpolates the digital data S4A ₂ and then averages it together with the digital data S4A ₁ to output it as an averaged signal S5.

That is, as shown in FIG. 2A, when the analog signal S3 is sampled at the sampling frequency FS, sampling points are taken every sampling period 1 / FS, and sampling data X (n) is obtained at each sampling point. Take Then, when the phase is shifted by 180 ° with respect to the sampling data X (n), FIG.
Sampling data Y (n) as shown in is obtained.

Here, as an experiment, the sampling data X (n) and Y (n) are each quantized to 32 [bit] data (about 1 [kH generated by the computer.
z) sine wave), of which 16th bit, 18th
A signal generated by adding white noise of pseudo random numbers to the [bit] th and the 20 [bit] th is used respectively.

In this case, the S / N ratio of the sampling data X (n) and Y (n) is X (n) = 98.1 [dB] (16 [bi
t]), 110.1 [dB] (18 [bit]), 1
22.2 [dB] (at 20 [bit]), Y (n) = 9
8.1 [dB] (at 16 [bit]), 110.1 [dB] (18 [b
It)) and 122.2 [dB] (20 [bit]), which is almost the theoretical value.

Next, the sampling data Y (n) in FIG. 2 (B) is interpolated using, for example, 7th-order Lagrange interpolation to obtain sampling data X (n) as shown in FIG. 2 (C). Sampling data Y ′ (n) is obtained at each sampling point in FIG. 2 (A). In this case, the sampling data Y ′ (n) is calculated using the 7th-order Lagrangian interpolation as follows:

[Equation 1]

[Equation 2]

(Equation 3) Is required. As a result, S / N is Y '(n) = 98.4
[DB] (when 16 [bit]), 110.4 [dB] (18 [bit
]) And 122.4 [dB] (when 20 [bit]).

Incidentally, as described above, the sampling data Y '
(N) is slightly more S / N than the sampling data Y (n)
The reason for the improvement of is that the Lagrangian interpolation uses the correlation of data of several points before and after (four points before and after in the present invention), so that the component of white noise having no correlation is not weighted. Therefore,
If the interpolation method is changed, the S / N will also rise or fall slightly. Further, in the present invention, since the calculation is performed using a computer rather than real time, the S / N fluctuates depending on the calculation word length of the digital signal processing processor or the like when actually expressed by a digital signal processing processor or the like.

Therefore, in order to finally improve the S / N as much as possible, it is necessary to set the S / N of the sampling data Y '(n) to the same value as the S / N of the Y (n). Since the noise existing in the sampling data Y '(n) and the noise existing in the sampling data Y (n) have no correlation with each other, the sum of these noise components improves the level by 3 [dB]. On the other hand, since the signal components of the sampling data Y '(n) and X (n) are almost the same, the signal component is doubled as it is when these signal components are added, so that the level is 6 [DB]
improves.

The final output is the sampling data Z
(N)

[Equation 4] And the result S / N is measured as follows. Z
(N) = 101.7 [dB] (when 16 [bit]), 113.7
[DB] (at 18 [bit]), 125.8 [dB] (at 20 [bit]
] When) becomes. Comparing this value with the sampling data X (n) and Y (n), which are the original signals, approximately 3
It can be seen that the S / N is improved by about [dB].

(1-2) When N AD Converters are Used The signal processing circuit 10 is shown in FIG. 3 in which parts corresponding to those in FIG. In the signal processing circuit 10,
The clock signal S1 generated in the clock generator 2 is sent to the phase conversion circuit 11. Phase conversion circuit 1
1, the clock signal S1 input 360 / N ° (N is a natural number) clock signal obtained by shifting the sequential phase by S10A ₁ (S1) ~S10A _N respectively A
And it sends it to D converter 3A ₁ to 3 A _N.

[0019] AD converter 3A ₁ to 3 A _N is clock signal S10 sequentially phase shifted by respectively 360 / N °
Each externally in synchronization with the rise of A ₁ ~S10A _N are adapted analog signal S3 is input. AD converter 3A ₁ to 3 A _N is an analog signal S3 are input to sampling and quantization A
After D conversion, these are digital data S11A ₁ ~
It is sent to the digital signal processing processor 5 as S11A _N. Digital signal processing processor 5 outputs this by averaging these together with digital data S11A ₁ after interpolating the digital data S11A ₂ ~S11A _N as the average value of signal S12.

A case where four of the N AD converters are used will be described. That is, as shown in FIG. 4A, when the analog signal S3 is sampled at the sampling frequency FS, sampling points are taken every sampling period 1 / FS, and sampling data X (n) is taken at each sampling point. Subsequently, when the phase is sequentially shifted by 90 ° with respect to the sampling data X (n), the sampling data Y1 (n), Y2 (n) and Y3 (n) are respectively obtained as shown in FIGS. Is obtained.

Next, the sampling data Y1 (n), Y2 (n) and Y3 (n) in FIGS. 4B to 4D are interpolated by using, for example, 7th order Lagrange interpolation, 5 (A) to (C), sampling data Y1 '(n), Y2' at each sampling point of sampling data X (n) (FIG. 4 (A)).
(N) and Y3 '(n) are obtained.

In this case, the sampling data Y1 '
(N), Y2 '(n) and Y3' (n) are obtained as follows using the 7th order Lagrangian interpolation. That is, the sampling data Y1 ′ (n) is calculated by the following equation

(Equation 5)

(Equation 2)

(Equation 6) And the sampling data Y2 ′ (n) is
The following formula

(Equation 7)

(Equation 2)

(Equation 8) Sampling data Y3 ′ (n)
Is the expression

[Equation 9]

(Equation 2)

[Equation 10] Is required. As a result, S / N is Y1 '(n) = 98.9
[DB] (when 16 [bit]), 110.9 [dB] (18 [bit
]), 122.9 [dB] (at 20 [bit]), and Y2 ′ (n) = 98.4 [dB] (at 16 [bit]),
110.4 [dB] (at 18 [bit]), 122.4 [dB] (20
[When bit is]). Furthermore, Y3 '(n) = 98.9
[DB] (when 16 [bit]), 110.9 [dB] (18 [bit
]), And 122.9 [dB] (at 20 [bit]).

Sampling data Y1 '(n), Y2'
Since there is no correlation between the noise existing in (n) and Y3 ′ (n) and the noise existing in the sampling data Y (n), the noise component level is improved by 6 [dB] when these noises are added together, Since the signal component is simply quadrupled, it is improved by 12 [dB]. Therefore, theoretically, the S / N is 6
[DB] improves.

If the final output is Z (n), then

[Equation 11] And the result S / N is measured as follows. Z
(N) = 104.8 [dB] (when 16 [bit]), 116.8
[DB] (at 18 [bit]), 128.9 [dB] (20 [bit
] When) becomes. This value is the sampling data X
Comparing with (n) and Y (n), it is understood that the S / N is improved by about 6 [dB], which is almost the theoretical value.

In this way, the input clock signal S1
When the phase of is sequentially shifted by 360 / N °, the S / N is also set to 3 × k [dB] by setting a large value of N.
And improve. In addition, in this case, the theoretical ideal value of the signal component becomes the maximum, so that as the value of N is increased, the S / N does not become better, but the value approaches the ideal value.

(1-3) Operation of the First Embodiment In the above configuration, the signal processing circuit 10 described above with reference to FIG. 3 executes the processing for reducing the noise of the analog signal according to the processing procedure shown in FIG. To do. That is, the signal processing circuit 10 enters the processing procedure from step SP1.
A predetermined sampling frequency FS in step SP2
After the clock signal is generated, the process proceeds to step SP3. In this step SP3, the signal processing circuit 10
The phase of the input clock signal is sequentially shifted by 360 / N ° (N is a natural number), and N AD converters 3A _1-
After sending to 3A _N respectively, the process proceeds to step SP4.

[0027] Then step SP4 signal processing circuit 10 in, the digital conversion in synchronization of N AD converter 3A ₁ to 3 A _N analog signals respectively inputted to the to the corresponding clock signal. Then, the signal processing circuit 10 interpolates the remaining (N-1) pieces of digital data with one piece of digital data out of the N pieces of digital data obtained as a reference, by interpolating the other piece of digital data. Match the phase with the digital data.

At this time, the noise existing in one reference digital data and the noise existing in the other digital data after the interpolation of the remaining (N-1) digital data are not correlated with each other. When the noise components of are added, the level is improved by 3/2 × N [dB]. On the other hand, when the signal component of one reference digital data and the signal component after interpolation of the other remaining (N-1) digital data are added, the signal component is N times as it is. Therefore, 3 × N
The level is improved by [dB].

After this, the signal processing circuit 10 proceeds to step SP.
Moving to step 5, the average value of N pieces of digital data in which these phases are combined is calculated and output. At this time, the average value of the N digital data has a signal component of 3 × N [dB]
Minute level is improved and noise component is 3/2 × N [d
B] As the level is improved, the S / N is 3/2 × N
Improves by about [dB]. After this, the signal processing circuit 10 moves to step SP6 and ends the processing procedure.

(1-4) Effects of the First Embodiment According to the above configuration, of the N digital data obtained by AD converting the analog signal using the N AD converters 3A _{1 to} 3A _N. , By interpolating and matching the phases of the remaining (N-1) digital data with the phase of one reference digital data, and calculating the average value of these digital data, S / N in the average value of N digital data
Is improved by subtracting the level of the noise component from the level of the signal component, and as a result, the noise of the analog signal at the time of AD conversion can be reduced. Further, by combining a plurality of existing AD converters, it is not necessary to newly provide a device for reducing noise of an analog signal.

(2) Second Embodiment (2-1) Using Two AD Converters In FIG. 7 in which parts corresponding to those in FIG. In addition to the signal processing circuit 1 of the first embodiment, oversampling filters 21A ₁ and 21A ₂ are provided on the output sides of the AD converters 3A ₁ and 3A ₂ , respectively, and the output side of the digital signal processing processor 5 is decimated. A filter 22 is provided.

The oversampling filters 21A ₁ and 21A ₂ oversample each frequency of the digital data S4A ₁ and S4A ₂ by M times (M is a positive number), and then oversample them S20A ₁ and S20A ₂ , respectively. Is sent to the digital signal processing processor 5. Subsequently, the digital signal processing processor 5 outputs the oversampling signal S20A.
After interpolating ₂ , this is oversampled signal S20
A1 and A ₁ are averaged and sent as an averaged signal S21 to the decimation filter 22.

The decimation filter 22 downsamples the sampling frequency M × FS oversampled M times based on the averaged signal S21 to 1 / M times to restore the original sampling frequency FS,
This is output as a filter output signal S22.

(2-2) N AD converters are used
In the case of FIG. 8 in which the same parts as in FIG.
The signal processing circuit 30 is shown. In the signal processing circuit 30,
AD converter in addition to the signal processing circuit 10 of the first embodiment
3A₁~ 3A_NOversampler on each output side
G Filter 21A ₁~ 21A_NIs installed and
Decimation is performed on the output side of the digital signal processing processor 5.
A filter 22 is provided.

Oversampling filter 21A ₁ ~
21A _N is digital data S11A _{1 to} S, respectively.
After oversampling each sampling frequency FS of 11A _N by M times (M is a positive number), these are sent to the digital signal processing processor 5 as oversampling signals S30A _{1 to} S30A _N , respectively. Digital signal processing processor 5 subsequently sends this by averaging it with over-sampling signal S30A ₁ after interpolating the oversampled signals S30A ₂ ~S30A _N as the average value of signal S31 to the decimating Chillon filter 22.

The decimation filter 22 downsamples the sampling frequency M × FS oversampled M times based on the averaged signal S31 to 1 / M times to restore the original sampling frequency FS,
This is output as a filter output signal S22.

(2-3) Operation of the Second Embodiment In the second embodiment, the Lagrangian interpolation is used as the interpolation method in the digital signal processing processor 5 as in the case of the first embodiment. . In this case, the averaged signal S21 output from the digital signal processing processor 5 is, for example, a frequency curve F1 having a sampling frequency FS = 44.1 [kHz] as shown in FIG.
The level decreases when the frequency is about 15 [kHz] at the point P on the frequency curve F1.

At this time, the frequency characteristic of the averaged signal S21 rolls off at a frequency as high as about 15 [kHz], which is a very high frequency range. In many cases, the low-frequency effect has a greater effect, and it is often felt that the sound quality is improved with respect to the source sound. However, when it is used for professional audio equipment, it is necessary to avoid lowering the high-frequency level. Therefore, when Lagrangian interpolation is used, it is inevitable that the high-frequency level lowers. I got it.

That is, in the first embodiment, FIG.
As shown in (A), the frequency band of the signal components of the signal obtained by band-limiting the analog signal S3 at the Nyquist frequency FS / 2 and sampling and quantized at the sampling frequency FS exists up to the Nyquist frequency FS / 2 or less. .
Therefore, if Lagrangian interpolation is used, the high frequency range of the signal component will be reduced.

To solve this problem, the AD converter 3
To the output side of the A ₁ to 3 A _N provided oversampling filters 21A ₁ ~21A _N, respectively each sampling frequency FS of the digital data S11A ₁ ~S11A _N oversampling M times. That is, in the second embodiment, as shown in FIG. 10 (B), digital data obtained by sampling and quantizing at a sampling frequency FS to band-limited analog signal S3 at the Nyquist frequency FS / 2 S11A ₁ ~S11A _By oversampling each _{N so} that each sampling frequency FS becomes M times, the oversampling signals S30A _{1 to} S30A _N
The frequency band of the signal component of is the sampling frequency M × FS
To the low frequency side.

Therefore, even when the Lagrangian interpolation in which the level in the high frequency range is lowered is used, the oversampling signal S
30A ₁ level of the high band of the signal component without affecting the frequency band of the signal component of ～S30A _N can be prevented from being lowered.

(2-4) Effects of the Second Embodiment According to the above configuration, each of N digital data obtained by AD converting an analog signal using N AD converters 3A _{1 to} 3A _N. After oversampling the sampling frequency FS by M times, the phases of the remaining one (N-1) digital data are interpolated and matched with the phase of one reference digital data among these. By doing so, it is possible to prevent the high-frequency level of the signal components of the N digital data after oversampling from decreasing even when Lagrangian interpolation is used.

Further, the average value of the N pieces of digital data after matching the phases is calculated, and the sampling frequency M × FS of the digital data having the average value is downsampled to 1 / M times to obtain the original sampling frequency FS. By returning to, it is possible to reduce the noise of the analog signal at the time of AD conversion as in the case of the first embodiment. Further, by combining a plurality of existing AD converters, it is not necessary to newly provide a device for reducing noise of an analog signal.

(3) Third Embodiment (3-1) Using Two AD Converters In FIG. 11 in which parts corresponding to those in FIG. 7 are designated by the same reference numerals, the signal processing circuit 40 has a second Unlike the signal processing circuit 20 of the embodiment, a clock generator 41 is provided in place of the clock generator 2 and the oversampling filters 21A ₁ and 21A ₂ are removed so that the output side of the AD converters 3A ₁ and 3A ₂ is removed. And the digital signal processing processor 5 are connected to each other.

The clock generator 41 has a clock signal S which is M times (M is a positive number) the sampling frequency FS.
41 is generated and sent to the AD converter 3A ₁ , and a clock signal S42 obtained by inverting the phase of the clock signal S41 via the inverter 4 is sent to the AD converter 3A ₂ .

The analog signals S3 are input to the AD converters 3A ₁ and 3A ₂ from the outside in synchronization with the clock signals S41 and S42 which are 180 ° out of phase with each other. The AD converters 3A ₁ and 3A ₂ respectively AD-convert and sample the analog signal S3, and then send these to the digital signal processing processor 5 as digital data S43A ₁ and S43A ₂ , respectively.

Subsequently, the digital signal processing processor 5
Sends the decimating Chillon filter 22 this was interpolating digital data S43A ₂ this by averaging with digital data S43A ₁ as an average value signal S44. The decimation filter 22 has a sampling frequency M multiplied by M based on the averaged signal S44.
After × FS is down-sampled to 1 / M times to restore the original sampling frequency FS, this is output as a filter output signal S22.

(3-2) When N AD Converters are Used In FIG. 12 in which parts corresponding to those in FIG. 7 are designated by the same reference numerals, the signal processing circuit 50 includes a signal processing circuit 30 of the second embodiment. Unlike the clock generator 2, a clock generator 41 is provided in place of the clock generator 2 and the oversampling filters 21A _{1 to} 21A _N are removed so that the output side of the AD converters 3A _{1 to} 3A _N and the digital signal processing processor 5 are connected. Are connected.

The clock generator 41 has a clock signal S which is M times (M is a positive number) the sampling frequency FS.
41 is generated and sent to the phase conversion circuit 11. The phase conversion circuit 11 receives the input clock signal S41 by 360 / N.
° (N is a natural number) and sends the clock signal S50A obtained by shifting the sequential phase by ₁ (S41) ~S50A _N to AD converter 3A ₁ to 3 A _N, respectively.

The AD converter 3A ₁ to 3 A _N is clock signal S50 which sequentially phase shifted by respectively 360 / N °
Each externally in synchronization with the A ₁ ~S50A _N are adapted analog signal S3 is input. AD converter 3A ₁ to 3 A _N can be obtained by sampling with the analog signal S3 is input to the AD conversion, respectively, and sends the digital signal processing processor 5 them as digital data S51A ₁ ~S51A _N. The digital signal processing processor 5 uses the digital data S51A ₂
After interpolating S51A _N , these are digital data S
51A _{1 is} averaged together with the averaged signal S52
Is sent to the decimation filter 22 as.

The decimation filter 22 down-samples the sampling frequency M × FS multiplied by M based on the averaged signal S52 to 1 / M to restore the original sampling frequency FS. This is output as a filter output signal S53.

(3-3) Operation of the third embodiment In the third embodiment, a clock generator 41 is provided in place of the clock generator 2 in the second embodiment, and the sampling frequency FS is M times. By generating the clock signal S41, the analog signal S3 is band-limited at the Nyquist frequency FS / 2, sampled and quantized at the sampling frequency M × FS, and the signal components of the digital data S43A _{1 to} S43A _N are obtained. The frequency band is on the low frequency side with respect to the sampling frequency M × FS.

Therefore, as in the case of the second embodiment, when Lagrangian interpolation that lowers the level in the high frequency range is used,
It is possible to prevent the level of the high frequency band of the signal component from decreasing without affecting the frequency band of the signal component of the digital data S43A _{1 to} S43A _N.

(3-4) Effects of the third embodiment According to the above configuration, the phase of the clock signal having the sampling frequency M × FS, which is M times the sampling frequency FS, is 360 / N ° (N is a natural number). in synchronization with the N clock signals obtained by sequentially shifting, AD conversion in each of the N AD converter 3A ₁ to 3 a _N respectively corresponding analog signals. By interpolating the remaining (N-1) digital data with respect to the phase of one reference digital data out of the N digital data obtained as a result, the phases are matched with each other. Even when Lagrangian interpolation is used, it is possible to prevent the high-frequency level of the signal components of the N digital data after oversampling from decreasing.

Further, the average value of the N pieces of digital data after matching the phases is calculated, and the sampling frequency M × FS of the digital data having the average value is downsampled to 1 / M times to obtain the original sampling frequency FS. By returning to, it is possible to reduce the noise of the analog signal at the time of AD conversion as in the case of the first embodiment. Further, by combining a plurality of existing AD converters, it is not necessary to newly provide a device for reducing noise of an analog signal.

(4) Other Embodiments In the above-mentioned embodiments, the 7th-order Lagrangian interpolation is used as the signal interpolation method in the digital signal processing processor 5, but the present invention is not limited to this. Lagrangian interpolation of 6 or less or 8 or more other than 7th order may be used, and various interpolation methods such as Newton interpolation and Newton-Raphson interpolation may be used.

[0057]

As described above, according to the present invention, an analog signal is synchronized with N clock signals obtained by sequentially shifting the phase of a predetermined clock signal by 360 / N ° (N is a natural number). Converted to N digital data each,
Subsequently, one of the N pieces of digital data is used as a reference, and the other remaining (N-1) pieces of digital data are interpolated to adjust the phases to the reference digital data. By taking the average value of N digital data whose phases are matched, the S / N in the average value of the N digital data is improved by the amount obtained by subtracting the noise component level from the signal component level. obtain. As a result, it is possible to realize an analog digital conversion method capable of reducing noise in an analog signal by using an existing AD converter when performing analog digital conversion.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal processing circuit according to a first embodiment.

FIG. 2 is a signal waveform diagram provided for explanation when sampling an analog signal.

FIG. 3 is a block diagram showing a configuration of a signal processing circuit according to the first embodiment.

FIG. 4 is a signal waveform diagram provided for explanation when sampling an analog signal.

FIG. 5 is a signal waveform diagram provided for explanation when sampling an analog signal.

FIG. 6 is a flow chart showing a processing procedure by the signal processing circuit in the first embodiment.

FIG. 7 is a block diagram showing a configuration of a signal processing circuit according to a second embodiment.

FIG. 8 is a block diagram showing a configuration of a signal processing circuit according to a second embodiment.

FIG. 9 is a frequency characteristic curve diagram when Lagrangian interpolation is used.

FIG. 10 is a signal waveform diagram showing a signal spectrum by oversampling.

FIG. 11 is a block diagram showing a configuration of a signal processing circuit according to a third embodiment.

FIG. 12 is a block diagram showing a configuration of a signal processing circuit according to a third embodiment.

[Explanation of symbols]

1, 10, 20, 30, 40, 50 ... Signal processing circuit,
2, 41 ...... Kurotsu lottery energy regulator, 3A ₁ ~3A _N ...
AD converter, 4 Inverter, 5 Digital signal processing processor, 11 Phase converter, 21A
_{1 ~21A N} ...... oversampling filter, 22
...... Decimation filter.

Claims (3)

[Claims] 1. The phase of a predetermined clock signal is 360 / N °
(N is a natural number) In synchronization with N clock signals obtained by sequentially shifting them, a first step of converting an analog signal into N digital data and one of the N digital data are performed. After the other remaining (N-1) digital data are interpolated by using the digital data as a reference and the phases are adjusted to the reference digital data, respectively, the N data after the phases are adjusted. And a second step of calculating an average value of the digital data of the analog digital conversion method. 2. In the first step, each sampling frequency of the N digital data is oversampled by a first predetermined multiple, and in the second step, the N frequencies after the oversampling are performed. Among the digital data, one of the digital data is used as a reference to interpolate the remaining (N-1) digital data, and the phase is adjusted to the reference digital data. 2. The average value of the N pieces of data after the summation is calculated, and the sampling frequency of the average value is down-sampled to a multiple of the first predetermined number. Analog digital conversion method. 3. In the first step, after multiplying the sampling frequency of the clock signal by a first predetermined number, the phase of the clock signal is sequentially shifted by 360 / N °, and in the second step, 2. The analog digital conversion method according to claim 1, wherein the sampling frequency of the average value of the N pieces of data after the phases are matched is down-sampled to the first predetermined number.