JPH08265124A - Gate drive circuit for field effect transistor - Google Patents

Abstract

PURPOSE: To delay an on-timing of a FET by minimizing a loss of a buffer circuit itself with simple configuration. CONSTITUTION: An on-timing of a FET 4 is delayed by a rising of an output voltage Vout by a time constant being a product of a resistance of a resistor 32 and a capacitance of a capacitive component 8 in existence in the FET 4. On the other hand, when the output signal Vout reaches an L level, both transistors(TRs) 17, 18 are conductive by a response delay of the TR 17 when it is turned off. However, the resistor 32 limits a collector current of the TR 17 to block the current flowing to the TR 18. Through the use of only one component (resistor 32), the loss of the buffer circuit 19 itself is minimized and the on-timing of the FET 4 can be slowed down.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit of a field effect transistor (hereinafter referred to as FET) having a delay circuit mainly applied to a partial resonance type switching power supply device and the like.

[0002]

2. Description of the Related Art Generally, an FE equipped with a delay circuit of this type.
The gate drive circuit of T is effectively used, for example, in a partial resonance type switching power supply device disclosed in JP-A-5-56638. The partial resonance type switching power supply device has an appropriate dead time from the control IC which is the pulse generating means to the gates of the pair of MOS type FETs which are the main switching elements, that is, both FETs are turned off. As described above, it is necessary to supply the gate driving signal. Specifically, as shown in the waveform diagram of FIG. 3, the output signal Vou from the control IC that generates a rectangular wave is generated.
t is directly applied to the gate drive circuit of the FET having the delay circuit to delay the ON timing of one FET (see the waveform of the drain-source voltage Vds1). On the other hand, after inverting the output signal Vout from the control IC, this inverted signal Vout 'is applied to the gate drive circuit of the FET having the similar delay circuit to delay the ON timing of the other FET. (Drain-source voltage V
See the waveform of ds2). In this way, each FE is
By delaying the on timing of T, the FETs are both turned off, that is, the drain-source voltage Vds1 of the FET,
It is possible to obtain the dead times T1 and T2 in which both Vds2 and the H level are high.

As a gate drive circuit for an FET suitable for such a partial resonance type switching power supply device, those shown in FIGS. 4 and 6 have been conventionally known. First, FIG.
The gate drive circuit 1 is a control I circuit.
A parallel circuit of a resistor 5 and a diode 6 is inserted and connected between the output terminal 3 which is the output terminal of C2 and the gate of the MOS type FET 4. Further, the delay circuit 7 which delays the ON timing of the FET 4 uses the time constant of the resistor 5 and the input capacitance of the capacitor 8 existing between the gate and the source of the FET 4.

The operation of this circuit is as shown in the waveform diagram of FIG. That is, when the output signal Vout of the control IC 2 rises to the H level, the gate-source voltage Vgs of the FET 4 exponentially rises based on the time constant of the resistor 5 and the input capacitance of the capacitor 8. And this FET
The gate-source voltage Vgs of 4 is the threshold level (F
When the drain current of ET4 exceeds the minimum value of the gate-source voltage Vgs at which it flows out, FET4 turns on, and the drain-source voltage Vds of FET4 becomes L.
Turn to a level. On the other hand, the output signal Vout of the control IC 2
Becomes L level, the energy stored in the capacitor 8 is released to the control IC 2 side via the diode 6, and the gate-source voltage Vgs of the FET 4 rapidly decreases. Therefore, the FET 4 is immediately turned off, and the drain-source voltage Vds changes to H level. In this case, after the output signal Vout of the control IC 2 rises,
The delay time T1 until the FET 4 is turned on can be appropriately changed by changing the constant of the resistor 5.

Explaining the circuit shown in FIG. 6, the gate drive circuit 11 includes a parallel circuit of a resistor 15 and a diode 16 between the output terminal 3 and the gate of the FET 4 and N.
A PN-type transistor 17 and a PNP-type transistor 18 are connected in series with a buffer circuit 19 formed by push-pull connection, and a capacitor 20 and a resistor 21 are connected to the output terminal 3.
Is connected to a differentiating circuit, and a MOS type FET 22 different from the FET 4 is connected to the connection point of the capacitor 20 and the resistor 21.
Connect the gate of and connect the drain of this FET22 to resistor 15
And a diode 16 connected in parallel to the buffer circuit 19 and a connection point.

In the operation of this circuit, as shown in the waveform diagram of FIG. 7, the differential output of the output signal Vout is applied between the gate and source of the FET 22 based on the time constant of the capacitor 20 and the resistor 21. At this time, when the output signal Vout rises, F
When the gate-source voltage Vgs' of the ET22 exceeds the threshold level, the FET22 turns on and the FET is turned on during that time.
The drain-source voltage Vds' of 22 becomes L level.
The input of the buffer circuit 19, that is, the transistors 17 and 18
The voltage applied to the base of the FET is at L level during the ON period of the FET 22, but after that, when the gate-source voltage Vgs' of the FET 22 becomes below the threshold level and the FET 22 is switched to the OFF state, the control IC 2 outputs the voltage. Output signal Vou
t is added as it is through the resistor 15 and turns to H level. At the same time, the buffer circuit 19 has one transistor 17
Is turned on, while the other transistor 18 is turned off, and the operating voltage terminal Vcc of the control IC 2
A predetermined operating voltage is applied to the gate of FET 4 via transistor 17. When the gate-source voltage Vgs of the FET4 becomes H level, the FET4 is turned on and the drain-source voltage Vds of the FET4 turns to L level. As described above, the gate-source voltage Vgs of the FET4 rises when a predetermined delay time T1 elapses from the output signal Vout. Therefore, the ON timing of the FET4 is the delay time T1 longer than the rise of the output voltage Vout. I will be late.

On the other hand, the output signal Vout of the control IC 2 is L
When the level is reached, the energy stored in the capacitor 20 is consumed by the resistor 21, one transistor 17 forming the buffer circuit 19 is turned off, the other transistor 18 is turned on, and the FET 4 is immediately turned off. At this time, the current generated from the buffer circuit 19 returns to the control IC 2 side via the diode 16. As a result, the drain-source voltage Vds' of the FET 22 becomes L level.

[0008]

The gate drive circuit 1 shown in FIG. 4 has the FE when the FET 4 is turned off.
The energy stored in the gate of T4 is the diode 6
Is directly returned to the control IC 2 via. Therefore, the loss of the control IC 2 becomes large, and there arises a problem that it cannot be used under a severe operating temperature. Also,
Considering these problems, it is possible to insert and connect the buffer circuit 19 as shown in FIG. 6 between the output terminal 3 and the parallel circuit of the resistor 5 and the diode 16. In this case, the buffer circuit 19 can obtain a sufficient capacity to drive the FET 4 and at the same time reduce the loss of the control IC 2 at the time of turning off the FET 4, but this time, the energy stored in the gate of the FET 4 can be reduced. Directly returns to the buffer circuit 19, and the loss of the buffer circuit 19 increases.

The biggest problem in using such a buffer circuit 19 is that the output signal Vout of the control IC 2 is at the L level, that is, when the FET 4 is turned off, because of the poor response of the transistor 17.
Both 7 and 18 are turned on, and the collector current of the transistor 17 flows to the transistor 18 side as it is, which causes the loss of the buffer circuit 19 itself.

On the other hand, in the circuit shown in FIG. 6, in order to obtain the predetermined delay time T1, a differentiating circuit consisting of the capacitor 20 and the resistor 21 and the FET 22 must be separately provided, which makes the circuit complicated. There is. Moreover, since the buffer circuit 19 is used, there is a problem that the buffer circuit 19 itself causes a loss when the output signal Vout falls as described above.

The present invention has been made in order to eliminate various problems in the existing gate drive circuit of the field effect transistor, and its purpose is to minimize the loss of the buffer circuit itself by a simple structure. Another object of the present invention is to provide a gate drive circuit for a field effect transistor that can suppress the delay and delay the on-timing of the field effect transistor.

[0012]

A gate driving circuit for a field effect transistor according to the present invention is an NPN push-pull connected to an output terminal of a pulse generating means for generating a rectangular wave.
Type transistor and PNP type transistor bases are connected, one end of a resistor is connected to the emitter of the NPN type transistor, and the PNP is connected to the other end of the resistor.
Circuit connecting the emitter of a field effect transistor and the gate of a field effect transistor, and a delay circuit for delaying the on-timing of the field effect transistor by a time constant between the gate-source capacitance of the field effect transistor and the resistance. It consists of and.

[0013]

With the above structure, when the output signal from the pulse generating means becomes L level, there is a period in which both transistors are in the ON state due to the response delay when the NPN transistor is turned off. However, during this period, the collector current of the NPN transistor is limited by the resistor,
Since the current hardly flows into the P-type transistor, the loss of the buffer circuit itself becomes significantly lower than in the conventional case. The resistance that constitutes the delay circuit not only sets the delay time by the time constant with the input capacitance existing in the field effect transistor, but also limits the collector current of the NPN transistor that tries to flow into the PNP transistor. Since it also plays a role of, the loss of the buffer circuit itself can be minimized and the on-timing of the field effect transistor can be delayed only by the resistance of only one component.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. The same parts as those of the circuit shown in the conventional example are designated by the same reference numerals, and detailed description of the common parts will be omitted.

First, the circuit configuration shown in FIG. 1 will be described.
The gate drive circuit 31 of the FET 4 in this embodiment is NP
A buffer circuit 19 in which an N-type transistor 17 and a PNP-type transistor 18 are push-pull connected, a resistor 32 whose one end is connected to the emitter of the transistor 17 and the other end is connected to the emitter of the transistor 18 and the gate of the FET 4, and this resistor 32. And a delay circuit 33 that delays the ON timing of the FET 4 according to the time constant of the input capacitance of the capacitor 8 existing between the gate and the source of the FET 4. The bases of the transistors 17 and 18 that form the buffer circuit 19 are connected to the output terminal 3 provided in the control IC 2, and the collector of the transistor 17 is connected to the operating voltage terminal Vcc of the control IC 2 and the transistor 18 is connected. Is grounded together with the source of FET4. FET4 is
Actually, it constitutes one main switching element of the partial resonance type switching power supply device, and by switching the FET 4 via the gate drive circuit 31, a DC voltage is intermittently applied to the primary winding of an inverter transformer (not shown). Is applied.

Although the control IC 2 is disclosed as one means for generating a rectangular wave in this embodiment, any pulse generating means may be used as long as it generates a rectangular wave of at least a predetermined period. Absent. Specifically, various pulse generation circuits and oscillators can be applied. Also, control IC
2 is provided with an output terminal 3, but this is provided only for the sake of convenience. Actually, the bases of the transistors 17 and 18 may be directly connected to the output terminal of the control IC 2.

Next, the operation of the above structure will be described with reference to the waveform diagram of FIG. Output signal V of control IC 2
When out rises to H level, one transistor 17 forming the buffer circuit 19 is turned on and the other transistor 18 is turned off, and the control IC is turned on.
A predetermined operating voltage is applied to the gate of the FET 4 from the second operating voltage terminal Vcc via the transistor 17. At this time, the gate-source voltage Vgs of the FET 4 exponentially rises based on the time constant between the resistor 32 and the input capacitance of the capacitor 8 as shown in the waveform diagram of FIG. When the inter-electrode voltage Vgs exceeds the threshold level, the FET4 turns on and the drain-source voltage Vds of the FET4 turns to the L level. Therefore, FE
The on-timing of T4 is delayed by the delay time T1 from the rise of the output voltage Vout.

On the other hand, the output signal Vout of the control IC 2 is L
At the level, one transistor 17 turns off, while the other transistor 18 turns on, but in reality, due to the response delay when the transistor 17 is turned off, both transistors 17 and 18 are in the ON state for a period. Occurs. However, during this period, the collector current of the transistor 17 is limited by the resistor 32 and hardly flows into the emitter side of the transistor 18, so that the buffer circuit
The loss of 19 itself is significantly lower than before. Moreover, F
Since the energy stored in the capacitor 8 existing in the ET4 is released to the ground line via the transistor 18 of the buffer circuit 19, it does not directly return to the control IC2, and also in this respect, the loss of the control IC2 can be reduced.

The gate drive circuit 31 of the present embodiment is no different from the prior art in that the provision of the buffer circuit 19 reduces the loss of the control IC 2 when the FET 4 is turned off. However, the resistor 32 forming the delay circuit 33 not only sets the delay time T1 by the time constant of the input capacitance of the capacitor 8 existing in the FET 4, but also the transistor 17 that tries to flow into the transistor 17. Also plays a role of limiting the collector current of the FET, and the loss of the buffer circuit 19 itself can be minimized and the ON timing of the FET 4 can be delayed by using only one resistor 32. In this regard, in each of the gate drive circuits 1 and 11 shown in FIGS. 4 and 6 shown in the conventional example, not only the loss of the buffer circuit 19 itself cannot be suppressed, but also the circuit configuration thereof is higher than that of the present embodiment. It's complicated. For example, the conventional gate drive circuit 1 shown in FIG. 4 seems to have a simpler configuration than the gate drive circuit 31 of the present embodiment, but in reality, if the buffer circuit 19 is provided in consideration of the loss of the control IC 2. , The number of parts is increased by the presence of the diode 6.

As described above, the FET 4 in this embodiment
The gate drive circuit 31 of the above connects one end of the resistor 32 to the emitter of one transistor 17 forming the buffer circuit 19,
The emitter of the other transistor 18 and the gate of the FET 4 are connected to the other end of the resistor 32, and the resistor 32 and the FET are connected.
By configuring the delay circuit 33 that delays the on-timing of the FET 4 by the time constant of the input capacitance of the capacitor 8 existing between the gate and the source of the buffer circuit 4, the loss of the buffer circuit 19 itself is extremely simple. The current limit of the resistor 32 can be suppressed to the minimum, and the ON timing of the field effect transistor can be delayed by the delay circuit 33.

The present invention is not limited to the above embodiments, but various modifications can be made within the scope of the gist of the present invention. For example, the FET 4 in the embodiment is assumed to be the main switching element of the partial resonance type switching power supply device, but the gate drive circuit of the present invention is applied to any field effect transistor which is desired to be operated with a delayed on-timing. Applicable.

[0022]

In the gate drive circuit for the field effect transistor according to the present invention, the output terminal of the pulse generating means for generating a rectangular wave is connected to the push-pull NPN type transistor and the base of the PNP type transistor, and the NPN transistor is connected. Existing between the gate and source of the field effect transistor, and a buffer circuit in which one end of a resistor is connected to the emitter of the field effect transistor, and the other end of the resistor is connected to the emitter of the PNP type transistor and the gate of the field effect transistor. The delay circuit delays the on-timing of the field effect transistor by the time constant of the input capacitance and the resistance, and the loss of the buffer circuit itself is minimized by a simple configuration. It is possible to delay the on-timing.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a waveform diagram of essential parts for explaining the circuit operation of FIG. 1 above.

FIG. 3 is a diagram showing each F in the partial resonance type switching power supply device.
FIG. 6 is a waveform diagram illustrating the operation of ET.

FIG. 4 is a circuit diagram showing a conventional example.

5 is a waveform chart of a main part for explaining the circuit operation of FIG.

FIG. 6 is a circuit diagram showing another conventional example.

7 is a waveform chart of a main part for explaining the circuit operation of FIG.

[Explanation of symbols]

 2 Control IC (pulse generation means) 4 FET (field effect transistor) 8 Capacitor (input capacitance) 17 NPN type transistor 18 PNP type transistor 19 Buffer circuit 32 Resistor 33 Delay circuit

Claims (1)

[Claims] 1. A base of an NPN type transistor and a PNP type transistor which are push-pull connected to an output terminal of a pulse generating means for generating a rectangular wave, and
A buffer circuit in which one end of a resistor is connected to the emitter of the NPN transistor and the other end of the resistor is connected to the emitter of the PNP transistor and the gate of the field effect transistor;
A gate drive circuit for a field effect transistor, comprising: a delay circuit that delays an on-timing of the field effect transistor by a time constant of an input capacitance existing between sources and the resistance.