JPH08263158A - Constant-current source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current source for supplying a current practically fixed for fluctuation in operation parameters and manufacture processing conditions. SOLUTION: This current source 2 is provided with a bias circuit 20 for generating a bias voltage for compensation and a current mirror 15. The bias circuit 20 uses a voltage divider 10 for generating a voltage voltage-divided based on a power supply voltage. The voltage-divided voltage is applied to the gate of a transistor 28 for modulation biased to a saturation state in a first current mirror 15 and the first current mirror controls the current applied to a linear load device 34. The voltage across the load device decides the bias voltage and it is applied to the gate of the transistor 52 at the reference branch of a second current mirror 40. The bias voltage controls the current at the reference branch of the second current mirror and an output branch 56 mirror- operates the current at the reference branch and generates a stable output current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of integrated circuits, and more particularly to a current source circuit useful in integrated circuits.

[0002]

BACKGROUND OF THE INVENTION In modern digital integrated circuits, especially those manufactured according to the well-known complementary metal-oxide-semiconductor (CMOS) technology, many functional circuits within the integrated circuit conduct stable currents. It depends on the current source. Examples of such functional circuits include voltage regulators, differential amplifiers, sense amplifiers, current mirrors, operational amplifiers, level shift circuits, reference voltage circuits, and the like. Such a current source is usually realized by a field effect transistor and a reference voltage is applied to the gate of the field effect transistor.

As is known in the art, integrated circuits using such current sources operate optimally when the current provided by the current source is stable to variations in operating and processing conditions. do. However, as is known in the art, the drive characteristics of MOS transistors can change significantly with respect to such operational and process variations. Conventional MOS transistor current sources typically have low operating temperatures (eg, 0 ° C.), high V _cc supply voltages (eg, 5.3 for a nominal 5V supply).
V), and more current at process conditions that maximize drive (eg, dimensions shorter than the nominal channel length), and conversely, these current sources have higher operating temperatures (eg, 100 ° C.), lower V _cc power supply voltage (for example, nominally 5V
It supplies less current to the power supply (4.7V), and at processing conditions that minimize drive current (eg, dimensions longer than the nominal channel length). It has been observed that the ratio between maximum current drive and minimum current drive for such conventional current sources is on the order of 2.5 to 6.0.
The operation of circuits dependent on these current sources tends to change significantly with respect to these operating and processing conditions,
It requires the circuit designer to design with greater operational margin, thus reducing the maximum performance of the integrated circuit.

Fluctuations in the current supplied by the current source are problematic, especially when the current to be supplied is relatively large. For example, output driver circuits for conventional integrated circuits may require up to 20 mA of current to be sourced by the current source. In such applications it is not possible to tolerate more than double this current fluctuation.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, solves the drawbacks of the prior art as described above, and substantially eliminates fluctuations in operating parameters and manufacturing process conditions. It is to provide a current source that supplies a constant current. Another object of the present invention is to
It is an object of the present invention to provide a current source that can be used in an output driver circuit that requires a substantially large current.

[0006]

The present invention can be realized in an integrated circuit as a current source,
It has a current mirror output stage controlled by a bias voltage from a bias circuit that tracks variations in processing parameters and supply voltage. The bias circuit is based on a resistive voltage divider that sets the current in the input branch of the current mirror in the bias circuit, where the modulating transistor, which is maintained in saturation, is the output branch of the bias circuit current mirror. Control the current through the linear load device at and generate the bias voltage applied to the current mirror output stage. The current mirror output stage comprises a reference branch having a P-channel transistor, the gate of which receives the bias voltage from the bias circuit and is in series with an N-channel transistor having its gate connected to the drain. The relative dimensions of the P-channel transistor and the N-channel transistor in this reference branch are selected to keep the P-channel transistor saturated. The output branch of the current mirror output stage is an N-channel transistor whose gate is connected to the gate and drain of the N-channel transistor in the reference branch. Therefore, the current supplied in the output branch of the current mirror is
Extremely stable against variations in power supply voltage, temperature, and manufacturing process conditions.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a current source 2 constructed according to a preferred embodiment of the present invention will be described with reference to FIG. The current source 2 according to this embodiment of the invention comprises a bias circuit 20 for generating a bias voltage on the line BIAS. As shown in FIG. 1, the bias circuit 20 includes a resistive voltage divider 10, which produces a voltage that is the desired portion of the voltage on the V _cc power supply. This divided voltage is applied to the current mirror 15. As will be described in more detail below, current mirror 15 produces a current that is applied to the load, so the output of current mirror 15 is the bias voltage on line BIAS. Line BI
The voltage on AS is applied to the current mirror 40, and the current mirror 40 outputs a fixed output current i at the terminal OUT.
_It absorbs _OUT and operates as a current source.

The construction and operation of the bias circuit 20 and the current mirror 40 in the current source 2 according to the preferred embodiment of the present invention will now be described in detail with reference to FIG. Generally, the bias circuit 20 is a current mirror bias circuit, in which case the reference branch of the current mirror 15 is controlled by the voltage divider 10. As will be apparent from the following description, the bias circuit 20 has the power supply voltage _Vcc
A bias voltage is provided on line BIAS that varies in a consistent manner with respect to variations in the value of V and certain manufacturing process parameters.

In this embodiment, the bias circuit 20
Supplies the voltage on line BIAS to the gate of P-channel transistor 52 in current mirror 40.
In this embodiment, P-channel transistor 52
It is desired that the gate-to-source voltage of the V _CC remain substantially constant with respect to variations in the voltage of the V _cc power supply, and thus the current therethrough. In other words, it is desired that the voltage on line BIAS follow the variations in _Vcc . Thus, the current i _OUT generated by the current mirror 40 at terminal OUT remains substantially constant with such variations.

In this embodiment of the invention, the bias circuit 20 comprises a resistive voltage divider 10 having resistors 21, 23 connected in series between the _Vcc power supply and ground. The output of the resistor divider 10 at the node between the resistors 21 and 23 is provided to the gate of the N-channel transistor 28 in the current mirror 15. Resistors 21 and 23 are preferably implemented in the usual manner as polysilicon resistors. As shown in FIG. 2, an additional resistor 2
5,27 can be provided in each branch of the voltage divider,
The fuses 24, 26 can be provided in parallel with it. Thus, the integrated circuit that implements bias circuit 20 is fuse programmable, allowing the voltage applied to the gate of transistor 28 to be adjusted, if desired. Of course, it is of course possible to provide a plurality of additional resistors 25, 27 and their associated fuses in the voltage divider in order to make the voltage output of the voltage divider adjustable.

As mentioned above, the gate of transistor 28 receives the output of the voltage divider formed by resistors 21 and 23. The source of transistor 28 is biased to ground, the drain of transistor 28 is connected to the drain and gate of P-channel transistor 30, and the source of P-channel transistor 30 is connected to _Vcc . The coupling of the transistors 28 and 30 constitutes the reference branch of the current mirror, the current conducted through it being substantially controlled by the voltage output of the resistive voltage divider 10 consisting of the resistors 21,23. To be done. Therefore, the voltage applied to the gate of transistor 28, and thus transistor 28 in the reference branch of the current mirror,
Current conducted by 30 varies with respect to variations in voltage of V _cc power supply, to maintain approximately the same percentage of the voltage of the V _cc power supply.

The output branch of the current mirror 15 in the bias circuit 20 is a P-channel mirror transistor 32.
And a linear load device 34. The source of P-channel transistor 32 is connected to _Vcc and its gate is connected to the gate and drain of transistor 30 in a current mirror fashion. The drain of the transistor 32 is a linear load device 3 in the line BIAS.
Connected to 4. The load device 34 can be realized as an N-channel transistor 34 whose source is grounded and whose gate is V _cc , in which case the common drain node of the transistors 32, 34 is on the line BIAS. Drive the bias voltage output of.
On the other hand, the linear load device 34 can be realized as a precision resistor or a two-terminal diode.

In either case, the linear loading device 34 is important in compensating for variations in processing parameters such as channel length. Transistor 30,
Fluctuations in the channel length of 32
Causes a variation in the current conducted by the line BIA, due to the linear characteristics of the load device 34.
Generate a corresponding variation in voltage on S. Therefore,
Bias circuit 20 provides an output voltage on line BIAS that tracks variations in processing parameters that affect the conduction of current by transistors in the integrated circuit.

As noted above, the current conducted by transistor 32 is controlled to match or be a specified multiple of the current conducted through transistor 30. Since the current conducted through transistors 28 and 30 is controlled according to the divided voltage of the _Vcc power supply, the current conducted by transistor 32 (and thus the voltage on line BIAS) is controlled by the _Vcc power supply. It The voltage on line BIAS follows the modulation in the _Vcc supply voltage, as will be explained in more detail below, by the modulation in the voltage drop across the linear load 34.

It is believed that certain dimensional relationships between the transistors in bias circuit 20 are very important in ensuring proper compensation. First, transistor 2
8 is preferably close to the minimum channel length and channel width for the manufacturing process used. With transistor 28 having a channel length close to the processing minimum, the current conducted by transistor 28 varies with variations in channel length for the highest performance transistors in an integrated circuit, and by using a longer channel length, The sensitivity of transistor 28 to such variations is reduced. However, the channel length of transistor 28 should be slightly greater than the minimum value to avoid hot electron effects and short channel effects. Transistor 28 is also preferably, and in particular bias circuit 20, transistors 28, 30 (and Miller branch transistor 32).
And considering that the DC current is always conducted through the linear load 34), in order to minimize the current conducted through it, one having a relatively small channel width but not a minimum value. is there. An example of the size of the transistor 28 based on a recent manufacturing process is a channel length of 0.8 μm and a channel width of 4.0 μm.
m, while the minimum processing values are 0.6 μm and 1.0 μm, respectively.

The P-channel transistors 30, 32 must also be appropriately sized in order to properly bias the bias transistor 28 and the linear load device 34 (if configured as transistors), respectively. To properly compensate for the bias voltage on line BIAS, transistor 28 is preferably biased into the saturation region (square law), while transistor 34 is biased into the linear (or triode) region. This is
Transistor 34 effectively acts as a linear resistive load device, while allowing transistor 28 to accumulate in saturation. As is apparent from the configuration of the bias circuit 20 in FIG. 2, such biasing action is due to the relative size of the transistors 28 and 30 and the transistor 3.
It depends on the relative dimensions of 2 and 34.

While maintaining the transistor 28 in saturation, the voltage at the gate of transistor 28 is as high as V
It is desirable for transistor 30 to be as large as practical in order to be close to _cc . Because the variation in _Vcc is applied to the gate of transistor 28 at a ratio defined by the voltage divider of resistors 21,23, so that this ratio is as close to 1 as possible,
Furthermore, it is desirable to maintain the transistor 28 in a saturated state. Large W for transistor 30
The / L ratio allows its drain-to-source voltage to be relatively small, thus pulling the drain voltage of transistor 28 higher, which causes the voltage at the gate of transistor 28 to be higher. Moreover, it is possible to maintain the transistor 28 in a saturated state. Therefore, the tracking capability of the bias circuit 20 is improved by the transistor 30 being very large.

In the embodiment described above, the V _cc power supply voltage is nominally 5.0 V and the table below shows the transistors 28, 30, in the configuration of FIG. 2 for each channel length of 0.8 μm. 32 and 34 show preferable channel widths (μm).

Transistor Channel Width (μm) 28 4.0 30 32.0 32 76.0 34 4.0 This bias circuit 20 embodiment has a relatively wide range of V _cc.
It has been found to be effective in maintaining good tracking behavior of the voltage on line BIAS over the supply voltage (via simulation). FIG. 3 shows line BA as a function of simulated V _cc for maximum and minimum transistor channel lengths in a 0.8 μm manufacturing process.
1 is a plot of voltage on IS showing the operation of bias circuit 20 according to the present invention. Curve 4 in Figure 3
4, 46 correspond to low current processing corners (ie maximum channel length) at 0 ° C. and 100 ° C. junction temperature, respectively, and curves 47, 49 in FIG. 3 indicate 0 ° C., respectively.
And 100 ° C. junction temperature at high current handling corners (ie minimum channel length). As can be seen from FIG. 3, the tracking of V _cc , which is increased by the voltage on line BIAS, is very accurate over a wide range of temperature and process parameters. As will be described in more detail below, this tracking effect causes the output current i _OUT from the output of the current mirror 40 to be substantially constant.

The configuration of the current mirror output circuit 40 will be described in detail with reference to FIG. 2 again. The current mirror 40 in this embodiment is constituted by a P-channel transistor 52, the source of which is biased to V _cc and the gate of which is the bias circuit 2 described above.
Biased by the bias voltage BIAS from the zero output. N-channel transistor 54 is connected in the form of a diode, the gate and drain of which are connected to the drain of transistor 64. Transistor 5
The dimensions of 2 and 54 are selected to ensure that P-channel transistor 52 remains saturated for the desired level of bias voltage BIAS. For example, for a bias voltage BIAS of about 2V, transistors 52 and 54 with a W / L ratio of about 15 keep transistor 52 in saturation, while _Vcc is nominally 5V.

The common node at the drains of transistors 52 and 54 provides a reference voltage ISVR, which is applied to the gate of N-channel transistor 56 which forms the output branch of current mirror 40. The source of N-channel transistor 56 is biased to ground and its drain is connected to terminal OUT. Therefore, the current conducted by the transistor 56, ie the output current i _OUT, is the current mirrored with respect to the current conducted by the transistor 54 in the reference branch of the current mirror 40.

The relative dimensions of transistors 54 and 56 are selected so that the current provided by transistor 56 is the desired multiple of the current conducted by transistors 52 and 54. For example, the ratio is 1: 1
, The width / length ratios of the transistors 54, 56 are equal to each other, while the current to be supplied by the transistor 56 is a multiple of the current to be conducted by the transistors 52, 54. 5
A W / L ratio of 6 is a desired multiple of the W / L ratio of transistor 54.

In operation, the current source 2 according to an embodiment of the present invention provides a relatively constant output as a result of the bias circuit 20 following variations in the supply voltage and process parameters in the generation of the vice voltage on the line BIAS. Supply current i _OUT . Because line BI
This is because the condition for causing the shift in the voltage on AS has the same influence on the drive characteristics of the transistor in the current mirror 40. In particular, both variations in processing conditions that shift the voltage on line BIAS (eg, shift between lines 46 and 49 in FIG. 3) and variations in power supply voltage V _cc affect the drive characteristics of transistor 52 in current mirror 40. And the net effect is that the current conducted by transistor 52 will be substantially constant with respect to these variations. For example, the processing conditions shown by the straight lines 47 and 49 in FIG. 3 cause the transistor 52 to conduct more current for a given set of bias conditions. However, the increased voltage generated by bias circuit 20 on line BIAS under these conditions causes the additional current drive of P-channel transistor 52 by reducing the gate-to-source voltage applied to transistor 52. To compensate. Similarly, when the power supply voltage V _cc is increased, the voltage on line BIAS is also increased, thus the gate-to-source voltage at the P-channel transistor 52 is maintained substantially constant over variations in supply voltage. Since the current through transistor 52 remains constant, the mirrored output current i _OUT tends to remain substantially constant with these variations.

In some circuit applications it may be necessary to control a relatively large current by a field effect current source. Particularly in these applications, and when there is a possibility of large variations in processing parameters and power supply voltage with respect to temperature, it is desirable that the output current i _OUT be as stable as possible. The current source configuration of FIGS. 1 and 2 according to this embodiment of the invention provides such stability. In the embodiment described above, the simulation results show that the ratio between the maximum current and the minimum current conducted by the transistor 56 in the current mirror 40 when the bias circuit 20 sets the voltage on the line BIAS applied to it. About 1.1
7 means that it is 0 ° C to 100 ° C.
Fluctuations over a temperature range of ° C, fluctuations in process parameters (ie transistor channel length, gate oxide thickness, and other known driving state changing parameters) resulting in about 50% driving current fluctuations, and 4.7V. Taken for variations in the _Vcc supply voltage in the range of to 5.3V. In this particular embodiment, the minimum current required to be driven by transistor 56 in current mirror 40 is 20 mA,
The maximum current supplied by transistor 56 is about 2
It is 3.4 mA.

The current source of this embodiment of the invention is believed to be useful in other circuit designs. For example, all circuits such as a voltage regulator, a differential amplifier, a sense amplifier, a current mirror, an operational amplifier, a level shift circuit, and a reference voltage circuit can be configured by using a current source transistor (that is, transistor 56). is there. By controlling the current source transistor in the manner described above, it is possible to ensure that the current supplied by transistor 56 is relatively stable,
This is considered to be beneficial in these application situations as well.

It is needless to say that the bias circuit 20 can be changed or modified without departing from the technical scope of the present invention. One such modification is shown in FIG. 4 as bias circuit 20 '. Circuit 20 '
Components similar to those in circuit 20 are labeled with similar reference numerals.

The bias circuit 20 'is constructed similarly to the bias circuit 20 described above. However, in this alternative embodiment, the voltage at the gate of the linear additional transistor 34 is set by the voltage divider 38 and its gate voltage is set to be a specified percentage of the V _cc power supply voltage. Transistor 34 operates as a substantially linear load, but is actually a voltage controlled resistor whose on-resistance is a function of gate to source voltage.
As shown in FIG. 4, only a part of _Vcc is applied to the transistor 34.
_Can be applied to the gate of the transistor to reduce the undesired decrease in the resistance of transistor 34 when V _cc makes a positive transition.

It is also possible to provide a circuit for selectively enabling and disabling the generation of the bias voltage BIAS, and providing such selectivity enhances its utility in certain applications. It is possible.

Thus, the present invention provides the significant advantage of a current source capable of providing a stable output voltage over a wide range of temperatures, power supply voltages and manufacturing process parameters. According to the above-described embodiments of the present invention, this stable output current is obtained by generating a bias voltage that tracks variations in processing conditions and power supply voltage in a manner that compensates for variations in the transistors of the output current mirror. To be The current source of the present invention is particularly useful in applications where a relatively large current is required, such as in an output driver circuit, without the risk of the maximum current of the current source becoming excessive.

Although the specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. It goes without saying that the above can be modified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a current source constructed in accordance with a preferred embodiment of the present invention.

FIG. 2 is a schematic circuit diagram showing a current source constructed according to a preferred embodiment of the present invention.

FIG. 3 is a graph showing bias voltage BIAS against V _cc power supply voltage generated by the bias circuit shown in FIG. 2 for various processing conditions and temperatures.

FIG. 4 is a schematic circuit diagram showing a current source configured according to another embodiment of the present invention.

[Explanation of symbols]

 2 current source 10 resistance voltage divider 15, 40 current mirror 20 bias circuit

Claims (16)

[Claims] 1. A current source comprising a resistive voltage divider coupled between a power supply voltage and a reference voltage for generating a divided voltage, a first current mirror having a reference branch and an output branch. A mirror transistor in which a first reference current conducted by the reference branch is controlled by the divided voltage and the output branch conducts a first mirror current corresponding to the first reference current; A first current mirror having a load for conducting a current and generating a bias voltage in response to the first mirror current; comprising a reference branch for conducting a second mirror current controlled by the bias voltage; And a second current mirror having an output branch for generating an output current for mirroring the second reference current. 2. The reference branch of the first current mirror according to claim 1, comprising a drain connected to the mirror node, a source connected to the power supply voltage, and connected to the drain thereof. A first reference transistor having a gate, a modulation transistor having a conduction path connected between the mirror node and a reference voltage, and having a control terminal for receiving the divided voltage, A current source characterized by having. 3. The mirror transistor according to claim 2, further comprising a source / drain path connected between the power supply voltage and the bias output node, and a control terminal connected to the mirror node. A current source characterized by comprising. 4. The load according to claim 3, wherein the load has a conductive path connected between the bias output and a reference voltage, and a control terminal for receiving a voltage for biasing in a linear region. A current source having a transistor. 5. The second reference transistor according to claim 4, wherein the reference branch of the second current mirror includes a source / drain path and a gate for receiving the bias voltage, the power supply voltage and the reference voltage. And a third reference transistor having a source / drain path connected in series with the source / drain path of the second reference transistor and having a gate to which the drain is connected, The output branch of the second current mirror comprises a source / drain path, comprises a gate connected to the gate of the third reference transistor, and is identical to the source of the third reference transistor. A current source having an output transistor having a source biased to a voltage. 6. The current according to claim 4, wherein the first reference transistor and the mirror transistor are P-channel field effect transistors, and the modulation transistor and the load transistor are N-channel field effect transistors. source. 7. The current source of claim 6, wherein the size of the first reference transistor is selected such that the modulating transistor is biased in the saturation region. 8. The current source of claim 7, wherein the mirror transistor size is selected such that the load transistor is biased in a linear region. 9. The current source of claim 4, wherein the voltage received at the control terminal of the load transistor is a portion of the power supply voltage. 10. The current source according to claim 1, wherein the load is a resistor. 11. The current source according to claim 1, wherein the load is a diode. 12. The second reference transistor according to claim 1, wherein the reference branch of the second current mirror comprises a source / drain path and a gate for receiving the bias voltage, the power supply voltage and the reference voltage. A third reference transistor having a source / drain path connected in series with the source / drain path of the second reference transistor and having a gate having its drain connected between The output branch of the mirror comprises a source / drain path, a gate connected to the gate of the third reference transistor, and a source biased to the same voltage as the source of the third reference transistor. A current source comprising an output transistor comprising: 13. A method of generating a stable current, wherein a power supply voltage is applied to a voltage divider to generate a divided voltage, and the divided voltage is a control terminal of a modulation transistor biased in a saturation region. Is applied to control a first reference current in a reference branch of the first current mirror, the first reference current is mirrored to generate a first mirror current in an output branch of the first current mirror, Applying the mirror current to a load in the output branch of the mirror to generate a bias voltage, applying the bias voltage to a control terminal of a transistor in the reference branch of the second current mirror to control the second reference current, A method comprising the steps of: mirroring a second reference current to generate a second mirror current. 14. The field effect transistor of claim 13, wherein the modulating transistor comprises a conducting path in a reference branch of the first current mirror and a control terminal coupled to the voltage divider. , A method of biasing the modulation transistor to a saturation region. 15. The output branch of the first current mirror according to claim 14, comprising a mirror transistor,
And the load includes a load transistor, each of the mirror transistor and the load transistor having a conductive path connected in series with each other, the mirror transistor being coupled to a reference branch of the first current mirror. A method comprising a control terminal, such that the current conducted by the mirror transistor mirrors the current conducted by the modulating transistor, biasing the load transistor in a linear region. 16. The method of claim 13, wherein the reference branch of the second current mirror comprises first and second reference transistors having source / drain paths connected in series, the drain of the second reference transistor And the gates are commonly connected and the first reference transistor is biased in the saturation region.