JPH08255912A - Semiconductor device, fabrication thereof and target - Google Patents

Abstract

PURPOSE: To form a shallow junction of a source-drain region while reducing the parasitic resistance in the source-drain region and the interconnection resistance of the gate electrode simultaneously. CONSTITUTION: Boron doped titanium 6 is deposited on the entire surface of a device. First heat treatment is then carried out to cause reaction among the titanium 6, a silicon substrate 1 and a polysilicon gate electrode 4 thus depositing titanium silicide 7. The boron doped titanium 6 not subjected to silification is then removed by wet etching using a mixture solution of hydrogen peroxide water, ammonia and water heat at about 60 deg.C thus leaving only the titanium silicide 7. Subsequently, second heat treatment is carried out in order to decrease the resistance of the substrate 1 deposited with the titanium silicide 7 and the gate electrode 4. At the same time, boron is diffused from the titanium silicide 7 into the substrate 1 thus forming a heavily doped shallow junction region 8 about 40nm deep.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and a target.

[0002]

2. Description of the Related Art In recent years, further reduction of design rules has been studied in order to realize high integration and high speed of semiconductor devices. Today, a prototype of 256M DRAM and a prototype of a CMOS transistor having a gate length of 0.1 μm have been announced. With the progress of miniaturization of such transistors, the device size is reduced according to the scaling rule, and
It is expected that the operation speed will increase accordingly.

However, although the channel resistance can be reduced by simply miniaturizing the transistor, the parasitic resistance of the diffusion layer of the source / drain (source / drain regions) and the resistance of the contact portion (contact resistance) may cause the channel resistance. It becomes equal to or larger than the resistance, which is an obstacle to speeding up the operation. In addition, in order to speed up the operation, it is necessary to reduce the resistance of the gate wiring (electrode).

Hitherto, refractory metals such as titanium (Ti), titanium tungsten (TiW) and titanium nitride (TiN), or compounds thereof have been used as means for lowering these resistances in semiconductor devices. Below, about the specific method of lowering the resistance using this high melting point metal,
Let me explain some.

1) Salicide method As a method for simultaneously reducing the parasitic resistance of the source / drain region and the wiring resistance of the gate electrode, salicide (Salici)
de; Self-aligned silicide) method has been proposed (T.Yo
shida., et.al.: J.Electrochemi.Soc., Vol.137, No.6, (19
90) pp1914-1917. reference).

General salicide method (salicide structure)
10 and 1 show a method of manufacturing a p-channel MOS transistor having an LDD (Lightly Doped Drain) structure using
A description will be given according to the schematic sectional view of the device shown in FIG. Step 1 (see FIG. 10A): LOCOS (Localized
Oxidation of Silicon method is used to form the element isolation region 72 on the n-type single crystal silicon substrate 71. Next, a silicon oxide film is formed on the substrate 71 by using a thermal oxidation method.
Then, a doped polysilicon film doped with boron is formed on the silicon oxide film by using a CVD (Chemical Vapor Deposition) method. Then, the doped polysilicon film and the silicon oxide film are patterned into a desired shape to form a gate insulating film 73 and a gate electrode 74.

Step 2 (see FIG. 10B): Boron ions (B ⁺ ) are implanted into the surface of the substrate 71 by using the gate electrode 74 as a mask for ion implantation, and self-aligned (self-aligned) low level. The concentration region 75 is formed. Step 3 (see FIG. 10C): Using a CVD method, a silicon oxide film is formed on the entire surface of the device formed in the above step. Next, the silicon oxide film is etched back by using the entire surface etch back method to form a sidewall spacer 76 on the sidewall of the gate electrode 74. Then, using the gate electrode 74 and the sidewall spacers 76 as a mask for ion implantation, boron fluoride ions (BF ₂ ⁺ ) are implanted into the surface of the substrate 71 to form the high concentration region 77 in a self-aligned manner.

Step 4 (see FIG. 11A): Using isotropic etching, the natural oxide film formed on the surface of the substrate 71 is removed. Next, a titanium film 78 (thickness: 30 nm) is formed on the entire surface of the device formed in the above step by using a magnetron sputtering method. Step 5 (see FIG. 11B): A first heat treatment is performed at a treatment temperature of 600 to 700 ° C. using a heat treatment method in an electric furnace or an RTA (Rapid Thermal Annealing) method. As a result, a titanium silicide (TiSi ₂ ) film 79 is formed in a self-aligned manner at the positions where the titanium film 78 and the substrate 71 are in contact with each other and the titanium film 78 and the gate electrode 74 are in contact with each other. At the same time, boron in the low concentration region 75 and the high concentration region 77 is activated. The treatment time when the heat treatment method in the electric furnace is used is about 30 minutes, and the treatment time when the RTA method is used is about 30 seconds. At this time, the titanium silicide film 79 is not formed at the position where the titanium film 78 and the sidewall spacer 76 are in contact with each other.

Next, a mixed solution of hydrogen peroxide solution, ammonia and water heated to about 60 ° C. (mixing ratio is H ₂ O ₂ : NH
_The unsilicided titanium film 78 is removed by a wet etching method using ₄ OH: H ₂ O = 1: 1: 5) to leave only the titanium silicide film 79. Then, using a heat treatment method or an RTA method in an electric furnace, the treatment temperature:
A second heat treatment is performed at 750 to 900 ° C. The second heat treatment time is the same as that of the first heat treatment. By this second heat treatment, the gate electrode 74 having the titanium silicide film 79 formed on the surface and the titanium silicide film 7 are formed.
The sheet resistance of each of the high-concentration regions 77 having 9 formed on the surface is reduced to about 5Ω / □.

Step 6 (see FIG. 11C): An interlayer insulating film 80 is formed on the entire surface of the device formed in the above step. Next, anisotropic etching is used to form a contact hole 81 in the interlayer insulating film 80, which is in contact with the titanium silicide film 79. Then, a metal material is filled in the contact hole 81 by using a sputtering method to form a metal wiring 82.
To form. As a result, the low concentration region 75 and the high concentration region 7
LDD with source / drain region 83
The manufacturing process of the p-channel MOS transistor 84 having the structure is completed.

Since the titanium silicide film 79 is formed in the MOS transistor 83, the parasitic resistance of the source / drain region 83 and the wiring resistance of the gate electrode 74 are simultaneously reduced. An n-channel MOS of LDD structure
When forming a transistor, n is formed in each of the regions 75 and 77.
Forming impurities (phosphorus, arsenic, etc.) may be ion-implanted.

Further, by replacing the titanium film 78 with a nickel film, a platinum film, a cobalt film, or the like, the titanium silicide film 79 can be replaced with a nickel silicide film, a platinum silicide film, a cobalt silicide film, or the like (the 41st part). Proceedings of the 29th Joint Lecture on Applied Physics (19
1994), 29p-ZG-13, 29p-ZG-14). 2) Method using Ti / TiN laminated barrier metal As a method of reducing the contact resistance between the source / drain regions and the metal wiring, there is a Ti / TiN laminated barrier metal method. At the same time, this is the Al that constitutes the metal wiring.
It is also a structure for preventing the reaction of the above with the Si substrate.

A process of connecting a metal wiring to a p-channel MOS transistor having a general structure will be described with reference to the schematic sectional view of the device shown in FIG. In this manufacturing method, the same components as those of the salicide method described above have the same reference numerals. Step 1 (see FIG. 12 (a)): p
A channel MOS transistor is formed.

Step 2 (see FIG. 12B): Normal C
Using the VD method, an interlayer insulating film 101 such as an HTO film or a BPSG film is formed on the entire surface of the device formed in the above process. Step 3 (see FIG. 12C): The interlayer insulating film 1 is formed by using a photolithography technique and a dry etching technique.
At 01, contact holes 102 to 104 communicating with the source / drain region 83 and the gate electrode 74 are formed, respectively.

Step 4 (see FIG. 12D): A Ti film 105 (thickness: 30 to 50 nm) is formed on the interlayer insulating film 101 and in the contact holes 102 to 104 by using a magnetron sputtering method. Step 5 (see FIG. 12E): A TiN film 106 (film thickness 70 to 100 nm) is formed on the Ti film 105 by magnetron sputtering. Further thereon, an aluminum alloy film (Al-Si (1%)-Cu (0.5%)) 10
7 is formed, and these metal films are processed into a predetermined shape by the photolithography technique and the dry etching technique.

Thus, the connection between the p-channel MOS transistor and the Al wiring is completed. The Ti film 105 is provided in the contact portion between the transistor and the wiring, and serves to reduce the contact resistance in this portion. The TiN film 106 functions as a so-called barrier metal that prevents Al and Si from reacting with each other. However, according to this method, the boron (B) doped in the source / drain regions 83 diffuses into the Ti film 105, and the impurity concentration of the source / drain regions 83 decreases, so that a large reduction in contact resistance can be expected. There is no problem.

Therefore, in consideration of the diffusion of B into the Ti film 105, a method of additionally doping B into the source / drain region 83 before forming the Ti film 105 in advance has been proposed (Proceedings VMIC). Conference June
12-13, 1989, p. 105). This will be described with reference to FIG. Since the steps of FIGS. 13a to 13c are common to the steps of FIGS. 12a to 12c, the description thereof will be omitted and the subsequent steps will be described.

Step 6 (see FIG. 13D): The source / drain regions 83 are formed using the interlayer insulating film 101 as a mask.
B is ion-implanted into the gate electrode 74 and the gate electrode 74, and further heat-treated to activate the source / drain region 83.
A new p ⁺ layer 108 is formed on the surface of the. After that, as in FIGS. 12d and 12e, the Ti film 105 / TiN film 106 / A is formed.
A metal wiring made of the 1-alloy film 107 is formed.

By doing so, the contact resistance is
It can be lowered to about 30 to 50Ω in a contact hole having a diameter of 1 μm. 3) Method of using doped oxide as a solid-phase diffusion source to a silicon substrate By the way, in order to miniaturize a transistor, it is necessary to prevent punch-through between a source and a drain.
Drain region (n ⁺ for n-channel MOS transistors
In layers, p-channel MOS transistors, the shallow junction of the p ⁺ layer must be formed.

As a method of forming a shallow junction between the source / drain regions, a method of using a doped oxide as a solid phase diffusion source to a silicon substrate has been proposed (M.
Saito, et.al .: IEEE, IEDM, (1992) pp897-900. reference). As a doped oxide, BSG (Boro-Silicate Glass)
) A method for manufacturing a p-channel MOS transistor having an LDD structure using a film will be described with reference to schematic sectional views of devices shown in FIGS. 14 and 15. In this manufacturing method, the same components as those of the salicide method described above have the same reference numerals.

Step 1 (see FIG. 14A): This is the same as step 1 (see FIG. 10A) in the salicide method described above. Step 2 (see FIG. 14B): Boron concentration: 4 × 1 over the entire surface of the device formed in the above step by using the CVD method.
A BSG film (film thickness: 100 nm) of 0 ²¹ cm ⁻³ is formed. To form a BSG film, during CVD growth,
Silane (SiH ₄ ) gas, which is the source gas, is added to diborane (B ₂
H ₆ ) gas may be added. Next, the BSG film is etched back by using the entire surface etch back method to form the gate electrode 74.
Side wall spacers 91 are formed on the side walls of the.

Step 3 (see FIG. 14C): Using RTA method, processing time: about 3 seconds, processing temperature: 1000 ° C. 1
A second heat treatment is performed to diffuse boron in the sidewall spacers 91 into the substrate 71 to form a low-concentration shallow junction region 92. Step 4 (see FIG. 15A): Using the gate electrode 74 and the sidewall spacers 91 as a mask for ion implantation, boron fluoride ions are implanted into the surface of the substrate 71,
The high concentration region 93 is formed in a self-aligned manner. Next, a second heat treatment is performed by using a heat treatment method in an electric furnace or an RTA method to form a low concentration shallow junction region 92 and a high concentration region 9
Activates the boron in 3.

Step 5 (see FIG. 15B): This is the same as step 6 (see FIG. 11C) in the salicide method described above. As a result, the manufacturing process of the p-channel MOS transistor 95 of the LDD structure including the source / drain region 94 including the low-concentration shallow junction region 92 and the high-concentration region 93 is completed. In the MOS transistor 95, since the low-concentration shallow junction region 92 is formed by using the sidewall spacer 91 (BSG film) as a solid-phase diffusion source, the low-concentration shallow junction region 92 has a shallow junction depth of about 40 nm. can do.

When forming an LDD structure n-channel MOS transistor, a sidewall spacer 91 is used.
BSG film for forming PSG (Phospho-Silicate)
Glass) film or AsSG (Arsenic Silicate Glass)
It may be replaced with a film, and n-type impurities (phosphorus, arsenic, etc.) may be ion-implanted into the high concentration region 93. To form the PSG film or AsSG film, phosphine (PH ₃ ) gas or arsine (AsH ₃ ) gas may be added to the silane gas during the CVD growth.

[0025]

The salicide method shown in FIGS. 10 and 11 has the following problems. That is, in the second heat treatment in the step 5 of the salicide method, the low concentration region 75 and the high concentration region 7 are exposed.
Boron in 7 diffuses deeply into the substrate 71. for that reason,
It is difficult to set the junction depth of the source / drain regions 83 to 100 nm or less. In other words, this method
While the parasitic resistance of the drain region 83 and the wiring resistance of the gate electrode 74 can be reduced at the same time, there is a problem that a shallow junction between the source / drain regions 83 cannot be formed.

Therefore, a method has been proposed in which boron fluoride ions are implanted after the titanium silicide film 79 is formed to form the high concentration region 77, thereby forming a shallow junction between the source / drain regions 83. However, according to this method, it is difficult to implant the impurity ions in a uniform dose amount into the substrate 71 through the titanium silicide film 79 due to the unevenness formed on the surface of the titanium silicide film 79. Therefore, there is a problem that the impurity concentration of the high concentration region 77 becomes non-uniform.

A method of forming a shallow junction of the source / drain regions 83 by lowering the second heat treatment temperature has been proposed. However, according to this method, the impurity concentration at the interface between the titanium silicide film 79 and the junction between the source / drain regions 83 is reduced, so that the parasitic resistance at the junction interface is increased. Therefore, increase in junction leakage in reverse bias and drain voltage-drain current (Vds
There is a problem that the rising of the −Ids characteristic is defective. Therefore, a method of thinning the titanium silicide film 79 (fourth
Proceedings of the 1st Joint Lecture on Applied Physics (1994), 29p-
ZG-10) and a method using double source / drain ion implantation (see 29p-ZG-11) have been proposed, but either method complicates the manufacturing process and lowers the throughput. There's a problem.

Even when the titanium silicide film 79 is replaced with another silicide film (a nickel silicide film, a platinum silicide film, a cobalt silicide film, etc.), the same problem as described above occurs. Moreover, the method shown in FIG. 13 has the following problems. That is, if high temperature annealing is performed to activate the p ⁺ region 108 formed by the additional ion implantation, it affects the initial operation design of the MOS transistor, so that a temperature of 800 ° C. or lower must be used. However, there is a problem that the crystal defects formed by the ion implantation cannot be sufficiently repaired.

Further, the method of utilizing doped oxide as a solid phase diffusion source to the silicon substrate shown in FIGS. 14 and 15 has the following problems. That is, the sheet resistance of the low-concentration shallow junction region 92 is extremely high at about 10 kΩ / □. That is, this method can form a shallow junction of the source / drain regions 83, but has a problem that the parasitic resistance of the source / drain regions 83 increases.

Therefore, in order to reduce the parasitic resistance of the source / drain region 94 as a whole, the junction depth of the high-concentration region 93 is increased to lower the parasitic resistance, and the parasitic resistance of the low-concentration shallow junction region 92 is reduced. A method of compensating for the height of is proposed. However, in this method, in order to suppress punch-through between the source / drain regions 94, the width of the low-concentration shallow junction region 92 (= width of the sidewall spacer 91) needs to be 0.15 μm or more. Therefore, M
There is a problem that miniaturization of the OS transistor 95 becomes difficult.

Even when the BSG film for forming the sidewall spacers 91 is replaced with another doped oxide (PSG film or AsSG film), the same problem as described above occurs. The present invention has been made to solve the above problems, and has the following objects.

1] A semiconductor device having a low resistance and a shallow junction and a method for manufacturing the same are provided. 2) A semiconductor device including a high-performance transistor and a method for manufacturing the same are provided. 3] A semiconductor device including a metal film doped with impurities and a method for manufacturing the same are provided.

4] A target used in the method of manufacturing a semiconductor device according to 1) or 2) above is provided.

[0034]

The gist of the present invention is to provide a metal film doped with impurities. The invention according to claim 2 has an LDD structure in which the source region or the drain region is formed by a shallow junction, and the drain region has a low concentration region and a high concentration region, and the low concentration region is formed on the sidewall of the gate electrode. The salicide structure is formed below the formed side wall spacer made of doped oxide, and the silicide film is formed on the source region or the drain region in a self-aligned manner.
The gist is that the silicide film is doped with impurities.

The invention according to claim 3 comprises a step of forming an impurity-doped metal film by adding an impurity to a raw material of the metal film at the time of forming the metal film by the PVD method or the CVD method. That is the summary. The gist of the invention according to claim 4 is that it comprises a step of forming a metal film doped with impurities by using an alloy target to which impurities have been added in advance when forming a metal film by a sputtering method. To do.

According to a fifth aspect of the invention, a step of forming a metal film doped with impurities by using a target made of a raw material of the metal film and a target made of impurities when forming the metal film by the sputtering method. The point is to have The invention according to claim 6 has a step of forming a metal film doped with impurities by adding impurities to a source gas of the metal film when forming the metal film by the CVD method. And

According to a seventh aspect of the present invention, the method of manufacturing a semiconductor device according to any one of the third to sixth aspects is used.
By performing a step of forming a metal film doped with impurities on the silicon layer and a heat treatment, a silicide film is formed at a position where the metal film and the silicon layer are in contact with each other, and impurities in the metal film are removed from the silicon film. The gist of the present invention is to have a step of diffusing into a layer.

The invention described in claim 8 uses the method for manufacturing a semiconductor device according to any one of claims 3 to 6,
A step of forming a metal film doped with an impurity having a conductivity different from that of the silicon layer on the silicon layer doped with the impurity and a heat treatment are performed so that a silicide is formed at a position where the metal film and the silicon layer are in contact with each other. The gist of the method is to form a film and diffuse the impurities in the metal film into the silicon layer to form a pn junction in the silicon layer.

According to a ninth aspect of the present invention, the method for manufacturing a semiconductor device according to any one of the third to sixth aspects is used.
A step of forming a metal film doped with an impurity having the same conductivity as that of the silicon layer on the impurity-doped silicon layer, and a heat treatment are performed to form a silicide at a position where the metal film and the silicon layer are in contact with each other. The gist of the invention is to form a film and diffuse the impurities in the metal film into the silicon layer.

According to a tenth aspect of the present invention, the step of forming a gate insulating film and a gate electrode on the silicon layer, the step of forming a sidewall spacer on the side wall of the gate electrode, and any one of the third to sixth aspects. Using the method for manufacturing a semiconductor device according to Item 1, a step of forming a metal film doped with impurities on the entire surface of the device formed in the above step, and a heat treatment to form a metal film and a silicon layer. Forming a source region or a drain region by diffusing impurities in the metal film into the silicon layer and forming a salicide structure at a position where the metal film is in contact with the silicide film. And

According to an eleventh aspect of the present invention, a step of forming a gate insulating film and a gate electrode on a silicon layer, a step of forming a sidewall spacer made of a doped oxide on a side wall of the gate electrode, 7. The method for manufacturing a semiconductor device according to any one of 1 to 6 above, a step of forming a metal film doped with impurities on the entire surface of the device formed in the above step and a heat treatment, A salicide structure is formed by forming a silicide film at a position where the film and the silicon layer are in contact with each other, and an impurity in the metal film and an impurity in the sidewall spacer are diffused into the silicon layer to form a source region or a drain. The gist of the present invention is to include a step of forming a region to form an LDD structure.

The invention according to claim 12 is the invention according to claims 3 to 6.
Using the method for manufacturing a semiconductor device according to any one of 1, a step of forming a metal film doped with impurities at least at a bottom of a contact hole communicating with the impurity region, and connecting the metal film to the impurity region. And a step of processing the metal wiring as at least a part thereof.

According to a thirteenth aspect of the present invention, the step of forming an impurity region on the surface of a silicon substrate and the method for manufacturing a semiconductor device according to any one of the third to sixth aspects are used.
At least the bottom of the contact hole leading to the impurity region, a step of forming a metal film doped with the same conductive impurities as the impurity region, and by performing a heat treatment, at a position where the metal film and the silicon substrate are in contact with each other. The gist of the invention is to form a silicide film and diffuse the impurities in the metal film to the surface of the silicon substrate.

According to a fourteenth aspect of the present invention, there is provided a step of forming a first conductivity type impurity region and a second conductivity type impurity region on a silicon substrate, and any one of the third to sixth aspects. Using the method of manufacturing a semiconductor device, at least a bottom portion of a contact hole communicating with an impurity region of the first conductivity type is doped with an impurity having the same conductivity as that of the impurity region.
7. The step of forming a metal film, the step of forming a silicide film at a portion where the first metal film and the silicon substrate are in contact by performing heat treatment, and the step of forming a silicide film according to claim 3. By using the method for manufacturing a semiconductor device, at least the bottom portion of the contact hole communicating with the impurity region of the second conductivity type,
The step of forming a second metal film doped with the same conductive impurities as the impurity region, and processing at least one of the silicide film and the second metal film as at least a part of the metal wiring connected to each impurity region. The point is that the process is provided.

The invention described in claim 15 is based on claims 12 to
In the method of manufacturing a semiconductor device according to any one of Items 14 to 14, the gist is that the impurity region functions as a source or a drain of the transistor. According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the seventh to eleventh and fourteenth aspects, the method includes a step of removing a metal film which is not silicided after the formation of the silicide film. That is the summary.

The gist of the seventeenth aspect of the present invention is that the target used in the sputtering method comprises an alloy in which impurities are added to a metal material. That is, according to the first aspect of the present invention, the silicide film is formed using the metal film in which the impurity serving as the dopant is doped into silicon, and the metal film in which the impurity serving as the dopant is doped into the silicon is formed. By using the film as a solid phase diffusion source, it is possible to form a shallow junction with low resistance.

According to the second aspect of the invention, a high-performance MOS transistor can be obtained by providing the source region or the drain region of the salicide structure formed by the shallow junction. Further, by providing the LDD structure, it is possible to obtain a MOS transistor having improved hot carrier resistance. Then, a low-concentration drain region is formed using the sidewall spacer as a solid phase diffusion source. Further, since the silicide film is doped with impurities serving as a dopant with respect to silicon, its resistance value becomes low, so that the parasitic resistance of the source region or the drain region can be reduced and the source region or the drain region can be reduced. Shallow junctions can be formed.

Further, according to the invention described in any one of claims 3 to 6, a metal film doped with impurities serving as dopants or impurities for suppressing diffusion of impurities from an impurity region with respect to silicon. Can be formed.
In addition, according to the invention described in any one of claims 7 to 9, the formation of the silicide film and the formation of the diffusion layer can be performed at the same time. Moreover, a shallow junction of the diffusion layer can be formed.

According to the invention described in claim 10,
When the sidewall spacer is formed of a material that does not react with the metal film, the salicide structure and the source or drain region can be formed at the same time. Further, by using the metal film as the solid phase diffusion source, a shallow junction of the source region or the drain region can be formed. The salicide structure can reduce the parasitic resistance of the source region or the drain region.

According to the invention described in claim 11,
The salicide structure and the source or drain region can be formed at the same time. Further, by using the metal film and the sidewall spacer as the solid phase diffusion source, a shallow junction of the source region or the drain region can be formed. The salicide structure can reduce the parasitic resistance of the source region or the drain region. Moreover, by providing the LDD structure, a MOS transistor having improved hot carrier resistance can be obtained.

Further, according to the invention of any one of claims 12 to 15, since the metal film is already doped with the impurity, it is difficult for the impurity to diffuse from the impurity region to the metal film, and the impurity region Since the impurity concentration does not easily decrease, the contact resistance can be reduced. In particular, claim 1
According to the invention described in 3, when the alignment margin between the element isolation edge and the contact hole is reduced due to the miniaturization of the element, the element isolation edge is also etched when the contact hole is formed, and the impurity region is formed. Even if the surface of the silicon substrate that is not formed is exposed, an increase in contact resistance is prevented by diffusing impurities from the metal film to this portion.

According to the invention described in claim 16,
By using the wet etching method, it is possible to easily and surely remove the metal film which is not silicided. According to the invention of claim 17, claim 4
The alloy target used in the invention described in 1. can be obtained.

[0053]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment Hereinafter, the present invention will be described with reference to SD (Single Drain).
A first embodiment embodied in a method for manufacturing a p-channel MOS transistor having a structure will be described with reference to schematic sectional views of devices shown in FIGS. 1 and 2.

Step 1 (see FIG. 1A): The element isolation region 2 is formed on the n-type single crystal silicon substrate 1 by using the LOCOS method.
To form. Next, a silicon oxide film is formed on the substrate 1 by using a thermal oxidation method. Subsequently, a doped polysilicon film doped with boron is formed on the silicon oxide film by using the CVD method. Then, the doped polysilicon film and the silicon oxide film are patterned into a desired shape to form the gate insulating film 3 (thickness: 3.5 nm) and the gate electrode 4 (thickness: 70 nm).

Step 2 (see FIG. 1 (b)): LPCVD (Low Low) using monosilane and nitric oxide (N ₂ O) as source gases.
A silicon oxide film (film thickness: 50 nm) is formed on the entire surface of the device formed in the above step by the Pressure Chemical Vapor Deposition) method. Next, the silicon oxide film is etched back by using the entire surface etch back method to form the sidewall spacer 5 on the sidewall of the gate electrode 4.

Step 3 (see FIG. 1C): The natural oxide film formed on the surface of the substrate 1 is removed by using isotropic etching. Next, using a magnetron sputtering method, a boron-doped titanium film 6 (thickness: 30 nm) is formed on the entire surface of the device formed in the above step. Here, in order to form a boron-doped titanium film (hereinafter referred to as a boron-doped titanium film) 6, an alloy target manufactured by a sintering method in which 5 wt% of boron is added to titanium is used as a target. The sputtering conditions are: substrate heating temperature: 300 ° C., sputtering power: 3.6 W, vacuum degree: 665 mpa (5 mTorr).

Step 4 (see FIG. 2A): The first heat treatment is performed at a treatment temperature of 625 ° C. by using the heat treatment method in the electric furnace or the RTA method. As a result, the titanium silicide film 7 is formed in a self-aligned manner at the positions where the boron-doped titanium film 6 and the substrate 1 are in contact with each other and the boron-doped titanium film 6 and the gate electrode 4 are in contact with each other. The treatment time when the heat treatment method in the electric furnace is used is about 30 minutes, and the treatment time when the RTA method is used is about 30 seconds. At this time, the titanium silicide film 7 is formed at a position where the boron-doped titanium film 6 and the sidewall spacer 5 are in contact with each other.
Is not formed.

By the way, the first heat treatment temperature is 600 to
700 ° C. is suitable, and if the processing temperature is higher than this temperature range, the silicidation proceeds too much to generate a residue, which may cause a bridge between the titanium silicide films 7. If the processing temperature is low, the titanium silicide film may be bridged. 7 may not be formed. Further, when the first heat treatment time is longer or shorter than the above, there is a tendency similar to the case where the treatment temperature is high or low, respectively.

Next, a mixed solution of hydrogen peroxide solution, ammonia and water heated to about 60 ° C. (mixing ratio is H ₂ O ₂ : NH
_The unsilicided boron-doped titanium film 6 is removed by a wet etching method using ₄ OH: H ₂ O = 1: 1: 5) to leave only the titanium silicide film 7.
Then, using a heat treatment method or RTA method in an electric furnace,
A second heat treatment is performed at a treatment temperature of 850 ° C. The second heat treatment time is the same as that of the first heat treatment.
By this second heat treatment, the sheet resistance of the substrate 1 and the gate electrode 4 on which the titanium silicide film 7 is formed is reduced to about 5Ω / □. At the same time, boron in the titanium silicide film 7 diffuses into the substrate 1 to form a high-concentration shallow junction region (diffusion layer) 8 having a junction depth of about 40 nm. To measure the junction depth, SIMS
(Secondary Ion Mass Spectrometry) method may be used.

By the way, the temperature of the second heat treatment is 750 to 750.
900 ° C. is suitable, and if the processing temperature is higher than this temperature range, there is a tendency that the diffusion of boron from the titanium silicide film 7 becomes too much and the junction becomes deeper. The diffusion of boron from inside 7 becomes less and the junction becomes too shallow.
There is a tendency that the n-junction is not formed. Also, 2
When the heat treatment time of the second time is longer or shorter than the above, there is the same tendency as when the treatment temperature is high or low.

Step 5 (see FIG. 2B): An interlayer insulating film 9 is formed on the entire surface of the device formed in the above step.
Next, by using anisotropic etching, a contact hole 10 for contacting the titanium silicide film 7 with the interlayer insulating film 9 is formed.
To form. Subsequently, the wiring layer 11 is formed by filling the contact hole 10 with a metal material by using a sputtering method. As a result, the manufacturing process of the p-channel MOS transistor 12 having the SD structure having the source / drain regions formed of the high-concentration shallow junction region 8 is completed.

In the MOS transistor 12, since the titanium silicide film 7 is formed on the source / drain regions (high-concentration shallow junction region 8) and the gate electrode 4 in a self-aligned manner, the parasitic resistance of the source / drain regions is increased. And the wiring resistance of the gate electrode 4 are simultaneously reduced. Also, MOS
In the transistor 12, since the source / drain region is composed of the high-concentration shallow junction region 8 having a junction depth of about 40 nm, the shallow junction of the source / drain region can be formed.

In the conventional salicide method described above, the silicidation reaction between the titanium film 78 and the substrate 71 and the diffusion of boron in the high concentration region 77 proceed independently. Therefore, it is difficult to keep the distance between the junction interface of the high concentration region 77 (hereinafter referred to as the junction interface A) and the junction interface between the titanium silicide film 79 and the substrate 71 (hereinafter referred to as the junction interface B) constant. Therefore, when a reverse bias is applied to the MOS transistor 84, titanium atoms are taken into the depletion layer at the portion where the distance between the junction interfaces A and B is short. As a result, problems such as an increase in junction leakage current and a defective rising of the drain voltage-drain current (Vds-Ids) characteristic occur.

On the other hand, in this embodiment, since boron atoms are present in the boron-doped titanium film 6, boron is diffused into the substrate 1 using the boron-doped titanium film 6 as a solid-phase diffusion source. . Therefore, the distance between the junction interface of the high-concentration shallow junction region 8 (source / drain region) and the junction interface of the titanium silicide film 7 and the substrate 1 can be kept constant. Therefore, even if a reverse bias is applied to the MOS transistor 12, titanium atoms are hard to be taken into the depletion layer. As a result, the junction leak current is suppressed and the rise of the drain voltage-drain current characteristic becomes good.

Incidentally, when the junction leak current in the reverse bias of the MOS transistor 12 was actually measured, it was found to be in the extremely low order of 1 × 10 ⁻⁹ A / cm ² . As described above, in the present embodiment, the salicide method (salicide structure) in which the titanium silicide film 7 is formed in a self-aligned manner on the surface of the source / drain region (the high-concentration shallow junction region 8) and the substrate 1 The method using the boron-doped titanium film 6 as the solid-phase diffusion source is also used.

Therefore, according to the present embodiment, the parasitic resistance of the source / drain region (shallow junction region 8 with high concentration) and the wiring resistance of the gate electrode 4 are simultaneously reduced, and the shallow junction of the source / drain region is reduced. Can be formed. Further, the manufacturing method of this embodiment is simple and easy, and high throughput can be obtained. By the way, according to the present embodiment, in the contact hole 10, the wiring layer 11 is formed via the titanium silicide film 7 doped with boron.
And the high-concentration shallow junction region 8 are contacted. Therefore, good contact between the wiring layer 11 and the high-concentration shallow junction region 8 can be obtained. In other words, the titanium silicide film 7 whose resistance has been reduced by being doped with boron functions as an excellent barrier metal in the multilayer wiring.

(Second Embodiment) A second embodiment in which the present invention is embodied in a method of manufacturing a p-channel MOS transistor having an LDD structure will be described below with reference to schematic sectional views of devices shown in FIGS. 3 and 4. In the present embodiment,
The same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

Step 1 (see FIG. 3A): The same as Step 1 of the first embodiment. Step 2 (see FIG. 3B): monosilane and nitric oxide (N
The ₂ O) and LPCVD method using TMB to (Trimethylboron) in the raw material gas, the entire surface boron concentration of the devices formed in the steps described above: a 4 × 10 ²¹ cm ^-3 BSG film (thickness: 100 nm) formed To do. Next, the BSG film is etched back by using the entire surface etch back method to form the sidewall spacer 21 on the sidewall of the gate electrode 4.

Then, using the RTA method, processing time: 3
Second, heat treatment is performed at 1000 ° C. for the first time. As a result, boron in the sidewall spacers 21 diffuses into the substrate 71, and a low-concentration shallow junction region (diffusion layer) 22 having a junction depth of about 40 nm is formed. By the way, 1
900-1100 ° C is suitable for the heat treatment temperature for the second time,
When the processing temperature is higher than this temperature range, there is a tendency that the diffusion amount of boron from the inside of the sidewall spacer 21 becomes too large and the junction becomes deep, and when the processing temperature becomes lower, the diffusion of boron from the inside of the sidewall spacer 21. Tends to be too shallow and the pn junction is not formed. If the first heat treatment time is longer or shorter than the above,
The tendency tends to be the same as when the processing temperature is high or low.

Step 3 (see FIG. 3C): The same as Step 3 in the first embodiment. Step 4 (see FIG. 4A): The same as Step 4 in the first embodiment. In the third heat treatment (second time in the process 4 of the first embodiment), the high-concentration shallow junction region 8 is formed.
Simultaneously with the formation of boron, boron in the low-concentration shallow junction region 22 is activated.

Step 5 (see FIG. 4B): The same as Step 5 in the first embodiment. As a result, a p-channel MOS of LDD structure having a source / drain region 23 composed of a low concentration shallow junction region 22 and a high concentration shallow junction region 8 is formed.
The manufacturing process of the transistor 24 is completed. In the MOS transistor 24, since the titanium silicide film 7 is formed on the source / drain region 23 and the gate electrode 4, the parasitic resistance of the source / drain region 22 and the wiring resistance of the gate electrode 4 are simultaneously reduced.

Further, in the MOS transistor 24, since the junction depths of the junction regions 8 and 22 are both as shallow as about 40 nm, the shallow junction of the source / drain regions 23 can be formed. Incidentally, when the junction leak current in the reverse bias was actually measured in the MOS transistor 24, it was 1 × 10 ⁻⁹ A / m as in the MOS transistor 12.
It turned out that it was in an extremely low order of cm ² .

As described above, in this embodiment, the salicide method (salicide structure) in which the titanium silicide film 7 is formed in a self-aligned manner on the surface of the source / drain region 23 (specifically, the high-concentration shallow junction region 8). ) And the method of using the boron-doped titanium film 6 as the solid phase diffusion source to the substrate 1 and the method of using the doped oxide (BSG film, the sidewall spacer 21) as the solid phase diffusion source to the substrate 1 are used together. Has been done.

Therefore, according to this embodiment, the same operation and effect as those of the first embodiment can be obtained. In addition, according to this embodiment, an LDD structure can be realized. That is, the BSG film (sidewall spacer 2
By adjusting the boron concentration in 1) and the width of the sidewall spacer 21, the characteristics of the low-concentration shallow junction region 22 can be adjusted, and the hot carrier resistance of the MOS transistor 24 can be improved and the parasitic capacitance can be reduced. Can be made smaller.

(Third Embodiment) Hereinafter, a third embodiment in which the present invention is embodied in a method of manufacturing a CMOS transistor having an SD structure will be described with reference to schematic sectional views of devices shown in FIGS. In this embodiment, the same components as those in the first and second embodiments are designated by the same reference numerals, and detailed description thereof will be omitted.

The CMOS transistor is a p-channel MOS transistor 1 of SD structure formed on the same substrate 1.
2 and an n-channel MOS transistor 31 of SD structure. Step 1 (see FIG. 5A): The element isolation region 2 is formed on the p-type single crystal silicon substrate 1 by using the LOCOS method.
Next, the n well 40 is formed in the region α where the n channel MOS transistor 12 is formed on the substrate 1. Then, a silicon oxide film is formed on the substrate 1 by using a thermal oxidation method.

Next, a region β where the p-channel MOS transistor 12 is formed on the substrate 1 is formed by using the CVD method.
A doped polysilicon film doped with boron is formed on the silicon oxide film. Further, a doped polysilicon film doped with phosphorus is formed on the silicon oxide film in the region β by using the CVD method. Then, the doped polysilicon film and the silicon oxide film are patterned into a desired shape to form the gate insulating film 3, the gate electrode 32 of the n-channel MOS transistor 31, and the gate electrode 4 of the p-channel MOS transistor 12.

Step 2 (see FIG. 5B): The silicon oxide film 3 is formed on the entire surface of the device formed in the above step by the LPCVD method using monosilane and nitric oxide as source gases.
3 (film thickness: 50 nm) is formed. Next, the silicon oxide film 33 on the region α is covered with a resist mask (not shown).
Then, the silicon oxide film 33 is etched back only on the region β by using the entire surface etch back method, and the sidewall spacer 34 is formed on the sidewall of the gate electrode 32.
At this time, since the silicon oxide film 33 on the region α is covered with the resist mask, it remains as it is.

Step 3 (see FIG. 5C): Using isotropic etching, the natural oxide film formed on the surface of the substrate 1 corresponding to the region β is removed. Next, using a magnetron sputtering method, a phosphorus-doped titanium film 35 (thickness: 30 nm) (hereinafter,
A phosphorus-doped titanium film 35) is formed. Here, the method for forming the phosphorus-doped titanium film 35 is the same as the method for forming the boron-doped titanium film 6 except that boron is replaced by phosphorus.

Step 4 (see FIG. 6A): The first heat treatment is performed at a treatment temperature of 625 ° C. by using the heat treatment method in the electric furnace or the RTA method. As a result, the titanium silicide film 36 is formed in a self-aligned manner at the portions where the phosphorus-doped titanium film 35 and the substrate 1 are in contact with each other and the phosphorus-doped titanium film 35 and the gate electrode 32 are in contact with each other. When the heat treatment method in the electric furnace is used, the treatment time is about 30 minutes and RT
The processing time when the method A is used is about 30 seconds. At this time, the titanium silicide film 36 is not formed at the position where the phosphorus-doped titanium film 35 and the sidewall spacer 34 are in contact with each other. Further, since the silicon oxide film 33 is formed on the region α, the titanium silicide film 3
6 is not formed.

Next, a mixed solution of hydrogen peroxide solution, ammonia and water heated to about 60 ° C. (mixing ratio is H ₂ O ₂ : NH
By wet etching using ₄ OH: H ₂ O = 1: 1: 5), the non-silicided phosphorus-doped titanium film 35 is removed to leave only the titanium silicide film 36. Subsequently, a second heat treatment is performed at a treatment temperature of 850 ° C. using a heat treatment method in an electric furnace or an RTA method. still,
The second heat treatment time is the same as that of the first heat treatment. By this second heat treatment, the titanium silicide film 3
The sheet resistance of the substrate 1 and the gate electrode 32 having the surface 6 formed thereon is reduced to about 5Ω / □. At the same time,
Phosphorus in the titanium silicide film 36 diffuses into the substrate 1,
A high-concentration shallow junction region (diffusion layer) 37 having a junction depth of about 30 nm is formed.

Next, a silicon oxide film 38 is formed on the entire surface of the device formed in the above process. Step 5 (see FIG. 6B): The silicon oxide film 38 on the region β is covered with a resist mask (not shown). Then, the silicon oxide film 33 is etched back only on the region α by using the entire surface etch-back method to form the sidewall spacer 5 on the sidewall of the gate electrode 4. Then, similarly to the first embodiment, the titanium silicide film 7 doped with boron and the shallow junction region 8 of high concentration are formed.

Step 6 (see FIG. 6C): An interlayer insulating film 9 is formed on the entire surface of the device formed in the above step.
Next, anisotropic etching is used to form contact holes in the interlayer insulating film 9 that are in contact with the titanium silicide films 7 and 36. Then, the wiring layer 11 is formed by filling the contact hole with a metal material by using a sputtering method.
As a result, a p-channel MOS transistor 12 of SD structure having a source / drain region formed of a high-concentration shallow junction region 8 and an n-channel SD structure of a source / drain region formed of a high-concentration shallow junction region 37 are formed. MO
The manufacturing process of the S transistor 31 is completed.

In the MOS transistor 31, since the titanium silicide film 36 is formed on the source / drain region (shallow junction region 37 of high concentration) and the gate electrode 32, the parasitic resistance of the source / drain region and the gate electrode 3 are not formed.
The wiring resistance of 2 is reduced at the same time. Further, in the MOS transistor 31, since the source / drain region is composed of the high-concentration shallow junction region 37 having a junction depth of about 30 nm, the shallow junction of the source / drain region can be formed.

In this embodiment, the phosphorus-doped titanium film 3 is used.
Since phosphorus atoms are present in 5, phosphorus is diffused into the substrate 1 using the phosphorus-doped titanium film 35 as a solid-phase diffusion source. Therefore, the high-concentration shallow junction region 37 (source / source
The junction interface of the drain region) and the titanium silicide film 36
It is possible to keep a constant distance from the bonding interface between the substrate and the substrate 1. Therefore, even if a reverse bias is applied to the MOS transistor 31, it is difficult for titanium atoms to be taken into the depletion layer. As a result, the junction leak current is suppressed and the rise of the drain voltage-drain current characteristic becomes good.

By the way, when the junction leak current in the reverse bias was actually measured in the MOS transistor 31, it was 1 × 10 ⁻⁹ A / c as in the MOS transistor 12.
It was found that the order was extremely low at m ² . As described above, in the present embodiment, the salicide method (salicide structure) in which the titanium silicide films 7 and 36 are formed on the surfaces of the source / drain regions (the high-concentration shallow junction regions 8 and 37) in a self-aligning manner, The method of using the boron-doped titanium film 6 as the solid phase diffusion source to the substrate 1 and the method of using the phosphorus-doped titanium film 35 as the solid phase diffusion source to the substrate 1 are used in combination.

By the way, according to this embodiment, the wiring layer 11 is formed through the titanium silicide film 36 doped with phosphorus.
And the high-concentration shallow junction region 37 are contacted. Therefore, the wiring layer 11 and the high-concentration shallow junction region 37 are formed.
You can get good contact with. That is, the titanium silicide film 36 whose resistance has been reduced by being doped with phosphorus functions as an excellent barrier metal in the multilayer wiring.

(Fourth Embodiment) The fourth embodiment of the present invention, which embodies the process of connecting metal wiring to a p-channel MOS transistor having an LDD structure, will be described below with reference to a schematic sectional view of a device shown in FIG. . In this embodiment, the same components as those of the conventional technique shown in FIG. 12 are designated by the same reference numerals, and detailed description thereof will be omitted.

Step 1 (see FIG. 7A): A p-channel MOS transistor is formed by the same method as in FIG. The film thickness of the gate oxide film 73 is 15 nm, and the film thickness of the gate electrode 74 is 100 nm. Step 2 (see FIG. 7B): An HTO film or B is formed on the entire surface of the device formed in the above step by using a normal CVD method.
An interlayer insulating film 101 such as a PSG film is formed.

Step 3 (see FIG. 7C): Contact holes 102 to 104 communicating with the source / drain region 83 and the gate electrode 74 are formed in the interlayer insulating film 74 by using a photolithography technique and a dry etching technique.
Are formed respectively. Step 4 (see FIG. 7D): dilute hydrofluoric acid (HF: H ₂ O =
Wet etching method (time: 30)
To 60 seconds) or the contact holes 102 to 1 by the sputter etching method using argon ions (Ar ⁺ ).
04 After removing the natural oxide film at the bottom, a titanium film (hereinafter referred to as a boron-doped titanium film) 50 (thickness: 30 nm) in which boron is doped on the entire surface of the device formed by the above process by using a magnetron sputtering method ) Is formed.

Here, in order to form the boron-doped titanium film 50, an alloy target manufactured by a sintering method in which 5 wt% of boron is added to titanium is used as a target. The sputtering conditions are as follows: substrate heating temperature: 300 ° C.
Sputtering power: 3.6W, vacuum degree: 665mp
a (5 mTorr). The thickness of the boron-doped titanium film 50 is preferably in the range of 10 to 150 nm. Among them, the range of 20 to 60 nm is preferable in order to reduce the manufacturing cost and obtain a stable contact resistance. Most desirable.

Step 5 (see FIG. 7E): A TiN film 106 is formed on the boron-doped titanium film 50 by the magnetron sputtering method. Further, an aluminum alloy film 107 is formed thereon, and these metal films are processed into a predetermined shape by photolithography technique and dry etching technique. In this way, the connection between the p-channel MOS transistor and the Al wiring is completed.

In the fourth embodiment, intentional heat treatment is not performed after the boron-doped titanium film 50 is formed, but in the subsequent process, a thermal history of a maximum temperature of about 450 ° C. is received. In the conventional example shown in FIG. 12, due to this thermal history, B atoms existing on the surface of the Si substrate at the bottom of the contact diffuse into the Ti or TiSi _x film, so the B concentration at the bottom of the contact decreases and the diameter of 0. The contact resistance value for p ⁺ in a contact hole of 5 μm is about 1
It becomes 00Ω.

On the other hand, in the fourth embodiment, the boron-doped titanium film 50 itself originally contains B atoms, and diffusion of B atoms from the Si substrate to the boron-doped titanium film 50 is suppressed. Therefore, B at the bottom of the contact
The concentration is less likely to decrease, and the contact resistance value for p ⁺ in a contact hole with a diameter of 0.5 μm is about 5 to 5.
It becomes as low as 10Ω. The contact resistance for n ⁺ in a contact hole having a diameter of 0.5 μm is about 20 to
A value of 50Ω was obtained.

(Fifth Embodiment) The fifth embodiment of the present invention, which embodies the process of connecting metal wiring to a p-channel MOS transistor having an LDD structure, will be described below with reference to a schematic sectional view of a device shown in FIG. . In the present embodiment, the same components as those in the fourth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

Step 1 (see FIG. 8A): Same as step 1 of the fourth embodiment. Step 2 (see FIG. 8B): The same as Step 2 of the fourth embodiment. Step 3 (see FIG. 8C): The interlayer insulating film 10 is formed by using a photolithography technique and a dry etching technique.
1, the source / drain region 83 and the gate electrode 7
Contact holes 102 to 104 which communicate with No. 4 are formed respectively.

At this time, if the alignment margin between the element isolation edge and the contact hole is reduced due to the miniaturization of the element, the element isolation edge is also etched and the source / drain regions 83 are not formed. The surface S of the Si substrate 71 is exposed. Step 4 (see FIG. 8D): The same as Step 4 in the fourth embodiment. Step 5 (see FIG. 8E): Using the RTA method, nitrogen (N
₂ ) In the atmosphere, heat treatment is performed at a treatment temperature of 900 ° C. for 30 seconds. As a result, the portion where the boron-doped titanium film 50 and the substrate 1 are in contact with each other is silicidized, and at the same time,
Boron in the boron-doped titanium film 50 diffuses into the substrate 1 to form a high-concentration shallow junction region (diffusion layer) 51 having a junction depth of about 40 nm. The SIMS method may be used to measure the junction depth.

By the way, the heat treatment temperature by RTA is 80
0 to 1000 ° C is suitable, and within this range, 85
By setting the temperature to 0 to 950 ° C., particularly good bonding control can be obtained, and the depth of the bonding region 51 does not become too deep, which is an optimum value. In addition, as heat treatment, RT
In addition to A, thermal annealing using an electric furnace may be used, and for example, heat treatment may be performed at a processing temperature of 850 ° C. for 30 minutes in a nitrogen atmosphere.

Step 5 (see FIG. 8E): A TiN film 106 is formed on the boron-doped titanium film 50 by the magnetron sputtering method. Further, an aluminum alloy film 107 is formed thereon, and these metal films are processed into a predetermined shape by photolithography technique and dry etching technique. In this way, the connection between the p-channel MOS transistor and the Al wiring is completed.

In the fifth embodiment, as in the fourth embodiment, p in a contact hole with a diameter of 0.5 μm is used.
^The contact resistance value for ⁺ is as low as about 5 to 10Ω. The contact resistance for n ⁺ in the contact hole having a diameter of 0.5 μm was about 20 to 50Ω. Further, when the junction leak current in the reverse direction was measured, it was on the order of 1 × 10 ⁻⁹ A / cm ² , and it was not a value causing any particular problem.

(Sixth Embodiment) The fourth embodiment of the present invention will now be described with reference to a method of manufacturing a CMOS transistor having an SD structure as an example.
A sixth embodiment, which embodies a method for further lowering the contact resistance with respect to n ⁺ , as compared with the embodiments and the fifth embodiment, will be described according to a schematic sectional view of a device shown in FIG. 9. In the present embodiment, the same components as those in the fourth and fifth embodiments have the same reference numerals, and detailed description thereof will be omitted.

The CMOS transistor is composed of an SD structure p-channel MOS transistor 52 and an SD structure n-channel MOS transistor 53 formed on the same substrate 71. Step 1 (see FIG. 9A): Using the LOCOS method, after forming the element isolation region 72 on the p-type single crystal silicon substrate 71, the p-channel MOS transistor 52 and the n-channel MOS transistor 53 are formed. Although not shown, the n-channel MOS transistor 53 is formed in an n-well or the like. A sidewall 76 is formed on the gate electrode 74 of each transistor.

Step 2 (see FIG. 9B): SiH ₄ and N ₂
A silicon oxide film 54 is formed on the entire surface of the device formed in the above process by the LPCVD method using a mixed gas with O.
(Film thickness; 50 nm) is formed. Next, contact holes 55, 55 communicating with the source / drain regions (not shown) of the p-channel MOS transistor 52 are formed by using the lithography technique.

Step 3 (see FIG. 9C): Isotropic etching is used to remove the natural oxide film formed at the bottoms of the contact holes 55, 55. Next, a magnetron sputtering method is used to form a boron-doped titanium film 50 (thickness: 30 nm) on the entire surface of the device formed in the above step. Here, the method for forming the boron-doped titanium film 50 is the same as that already described.

Furthermore, a heat treatment method or RTA in an electric furnace is performed.
Method, heat treatment is performed at a treatment temperature of 900 ° C. As a result, the titanium silicide film 56 is formed in a self-aligned manner at the position where the boron-doped titanium film 50 and the substrate 1 are in contact with each other. The treatment time when the heat treatment method in the electric furnace is used is about 30 minutes, and the treatment time when the RTA method is used is about 30 seconds. At this time, the titanium silicide film 56 is not formed on the silicon oxide film 54.

Step 4 (see FIG. 9D): A mixed solution of hydrogen peroxide solution, ammonia and water heated to about 60 ° C. (mixing ratio is H ₂ O ₂ : NH ₄ OH: H ₂ O = 1). The boron-doped titanium film 50 which has not been silicidized is removed by a wet etching method using 1: 5) to leave only the titanium silicide film 56. Step 5 (see FIG. 9E): A contact hole communicating with the source / drain region (not shown) of the n-channel MOS transistor 53 is formed by using the lithography technique.

Then, using the magnetron sputtering method,
A phosphorus-doped titanium film (hereinafter referred to as a phosphorus-doped titanium film) on the entire surface of the device formed in the above process 5
7 (film thickness: 30 nm) is formed. Here, to form the phosphorus-doped titanium film 57, the same method as that for forming the boron-doped titanium film may be used, and phosphorus may be used instead of boron.

Then, a TiN film 106 is formed on the phosphorus-doped titanium film 57 by magnetron sputtering.
To form. Further, an aluminum alloy film 107 is formed thereon. Step 6 (see FIG. 9F): Finally, these metal films are processed into a predetermined shape by the photolithography technique and the dry etching technique. In the sixth embodiment,
The contact resistance value for p ⁺ in a contact hole having a diameter of 0.5 μm is about 10 to 30 Ω, and the diameter is 0.5.
The contact resistance value with respect to n ⁺ in the μm contact hole is as low as about 5 to 10Ω, and CMO
This value has no problem in the S process. As for the junction leak characteristic, a value without any problem can be obtained as in the fifth embodiment.

The above embodiments may be modified as follows, and in that case, the same operation and effect can be obtained. (1) Replace the titanium films 6, 35, 50, 57 with other metal films (platinum film, cobalt film, etc.). As a result, the titanium silicide films 7, 36 and 56 are replaced with other silicide films (platinum silicide film, cobalt silicide film,
Etc.). In that case, in order to form each of the metal silicide films described above, a first heat treatment is performed under the following conditions using a heat treatment method in an electric furnace or an RTA method after forming the metal film. Platinum silicide film (processing temperature: 550-650 ° C, processing time in electric furnace: 3
About 0 minutes, RTA method processing time: about 60 seconds), cobalt silicide film (processing temperature: 600 to 700 ° C., processing time in electric furnace: about 30 minutes, RTA method processing time: about 60 seconds).

In the first heat treatment, if the treatment temperature is higher than the above temperature range, silicidation proceeds too much to generate a residue, which may cause a bridge, and if the treatment temperature is lowered, the resistance value of the metal silicide film is decreased. There is a risk of becoming higher. Further, when the first heat treatment time is longer or shorter than the above, there is a tendency similar to the case where the treatment temperature is high or low, respectively.

Further, there are the following etching solutions for wet etching the above metal silicide films. Platinum silicide film (mixed solution of nitric acid, hydrochloric acid, and water heated to about 80 ° C. (mixing ratio is HNO ₃ :
HCl: H ₂ O = 1: 1: 5), cobalt silicide film (mixed solution of hydrochloric acid, hydrogen peroxide solution and water heated to about 60 ° C. (mixing ratio is HCl: H ₂ O ₂ : H ₂ O = 1: 1:
5)).

Then, in order to reduce the resistance of each metal silicide film, a second heat treatment is performed at the following processing temperature. Platinum silicide film (Processing temperature: 800-900
C.), cobalt silicide film (processing temperature: 800 to 90)
0 ° C). The heat treatment time is the same as that of the first heat treatment. In the second heat treatment, if the treatment temperature is higher than the above temperature range, there is a tendency that the diffusion of impurities becomes excessive and the junction depth increases.
When the processing temperature is low, the diffusion of impurities is reduced, the junction becomes too shallow, and the pn junction is not formed. Further, when the second heat treatment time is longer or shorter than the above, there is a tendency similar to the case where the treatment temperature is high or low, respectively.

If the resistance of the metal silicide film is sufficiently reduced by the first heat treatment, the second heat treatment may be omitted. (2) In the third and sixth embodiments, the phosphorus-doped titanium films 35 and 57 are replaced with arsenic-doped titanium films. The method for forming the titanium film doped with arsenic is the same as the method for forming the boron-doped titanium film 6,
Other conditions are the same except that boron is replaced by arsenic.

(3) Impurity-doped metal film (titanium film 6, 35, 50,
In the case of forming 57), an alloy target is not used, and a target of a simple metal and a target of a simple impurity are arranged side by side in the magnetron sputtering apparatus. (4) Metal film doped with impurities (titanium films 6, 3
5, 50, 57) is formed by the CVD method.

In this case, the raw material is used to form the titanium film.
As gas, titanium chloride (TiCl _Four), TDMAT (T
etrakis-Dimethylamido-Titanium), TDEAT (Tet
rakis-Diethylamino-Titanium) is used. Platy
Cyclopentadien is used as the source gas to form the Na film.
Use yl allyl Platinum or the like. Form cobalt film
The raw material gas is Bis-methylcyclopentadienyl.
 Use Cobalt etc.

Then, the source gas of the metal film is added with T
A gas containing impurities such as MB, TMP (Trimethylphosphine), diborane, phosphine, arsine, and boron trifluoride (BF ₃ ) is added to form a metal film doped with impurities. (5) In the second embodiment, the BSG film for forming the sidewall spacers 21 is a PSG film or AsS film.
Replace with G membrane. Then, the boron-doped titanium film 6, the titanium silicide film 7, and the high-concentration shallow junction region 8 are replaced with the phosphorus-doped titanium film 35, the titanium silicide film 36, and the high-concentration shallow junction region 37, respectively.
An n-channel MOS transistor having a D structure is formed.

(6) Second Embodiment and Above (5) and Third
A CMOS transistor having an LDD structure is manufactured in combination with the embodiment. (7) Metal film doped with impurities (titanium films 6, 3
5, 50, 57), a sputtering method (simultaneous sputtering, bias sputtering, etc.) other than the magnetron sputtering method, a vacuum deposition method, an ion plating method,
PVD (Physical Vapor Deposition) in a broad sense including ion beam deposition method and cluster ion beam method
Use the method.

(8) The single crystal silicon substrates 1 and 71 are replaced with single crystal silicon films, polysilicon films and amorphous silicon films to form thin film transistors. (9) The gate insulating film 3 is formed of an appropriate insulating film (silicon nitride film or the like) other than the silicon oxide film or a laminated film thereof. (10) The side wall spacers 5, 34, 76 are formed of an appropriate material (silicon nitride film, etc.) that does not react with the titanium films 6, 35. Titanium film 6,35,50,
When 57 is replaced with another metal film, the sidewall spacers 5, 34, 7 are made of a material that does not react with the metal film.
6 is formed.

(11) The above (1) to (10) are combined and implemented. Although the respective embodiments have been described above, technical ideas other than the claims that can be understood from the respective embodiments will be described below together with their effects. (A) The method of manufacturing a semiconductor device according to any one of claims 7 to 11, wherein after the heat treatment, the heat treatment is performed again at a higher temperature than the heat treatment.

By doing so, it is possible to further reduce the resistance of the silicide film. (B) In the method of manufacturing a semiconductor device according to any one of claims 7 to 11, a step of forming an interlayer insulating film on the entire surface of the device formed in the step, and the silicide in the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: a step of forming a contact hole for contacting a film; and a step of filling the contact hole with a conductive material to form a wiring layer.

By doing so, it is possible to realize contact between the silicide film having a low contact resistance and the wiring layer. By the way, in this specification, a member according to the constitution of the invention is defined as follows. (A) The silicon layer includes not only a single crystal silicon substrate but also a well, a single crystal silicon film, a polysilicon film, and an amorphous silicon film.

(B) The PVD method is not only a sputtering method such as a co-sputtering method, a bias sputtering method and a magnetron sputtering method, but also a vacuum deposition method, an ion plating method, an ion beam deposition method, a cluster ion beam method and the like. Shall also be included.

[0123]

【The invention's effect】

1] It is possible to provide a semiconductor device having a low resistance and a shallow junction and a method for manufacturing the semiconductor device. 2) It is possible to provide a semiconductor device including a high performance transistor and a method for manufacturing the same.

3] It is possible to provide a semiconductor device having a metal film doped with impurities and a method for manufacturing the same. 4] It is possible to provide a target used in the method of manufacturing a semiconductor device described in 1) or 2) above.

[Brief description of drawings]

FIG. 1 is a schematic sectional view for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining the manufacturing method according to the second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining the manufacturing method according to the second embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view for explaining the manufacturing method according to the third embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view for explaining the manufacturing method according to the third embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view for explaining the manufacturing method according to the fourth embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view for explaining the manufacturing method according to the fifth embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view for explaining the manufacturing method according to the sixth embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 11 is a schematic cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 12 is a schematic cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 13 is a schematic cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 14 is a schematic cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 15 is a schematic cross-sectional view for explaining the manufacturing method of the conventional example.

[Explanation of symbols]

 1,71 n-type single crystal silicon substrate 3,73 gate insulating film 4,32,74 gate electrode 5,34 sidewall spacer 6,, 35 50,57 titanium film 7,36,56 titanium silicide film 8,37 high concentration Shallow junction region 9 Interlayer insulating film 10, 102, 104 Contact hole 11 Wiring layer 22 Low concentration shallow junction region 23 Source / drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/285

Claims (17)

[Claims] 1. A semiconductor device comprising a metal film doped with impurities. 2. The source or drain region is formed by a shallow junction, and the drain region has an LDD structure having a low concentration region and a high concentration region, the low concentration region being formed on a sidewall of a gate electrode. The salicide structure is formed below the sidewall spacer made of doxide, and the silicide film is formed in a self-aligned manner on the source region or the drain region, and the silicide film is doped with impurities. Semiconductor device. 3. A semiconductor comprising a step of forming a metal film doped with impurities by adding impurities to a raw material of the metal film at the time of forming the metal film by the PVD method or the CVD method. Device manufacturing method. 4. By using an alloy target to which impurities are added in advance when forming a metal film by a sputtering method,
A method of manufacturing a semiconductor device, comprising a step of forming a metal film doped with impurities. 5. A step of forming a metal film doped with impurities by using a target made of a raw material of the metal film and a target made of impurities when forming the metal film by the sputtering method. Of manufacturing a semiconductor device. 6. A semiconductor device comprising a step of forming a metal film doped with impurities by adding impurities to a source gas of the metal film when forming the metal film by a CVD method. Production method. 7. A method of forming a metal film doped with impurities on a silicon layer by using the method for manufacturing a semiconductor device according to claim 3 and performing heat treatment, And a step of diffusing impurities in the metal film into the silicon layer while forming a silicide film at a position where the metal film and the silicon layer are in contact with each other. 8. A metal doped with an impurity having a conductivity different from that of the silicon layer on the silicon layer doped with the impurity, using the method for manufacturing a semiconductor device according to claim 3. By the step of forming the film and the heat treatment, a silicide film is formed at a position where the metal film and the silicon layer are in contact with each other, and impurities in the metal film are diffused into the silicon layer to form a pn layer in the silicon layer. And a step of forming a junction. 9. A metal in which the same conductive impurity as that of the silicon layer is doped on the impurity-doped silicon layer by using the method for manufacturing a semiconductor device according to claim 3. The method includes a step of forming a film and a step of performing a heat treatment to form a silicide film at a position where the metal film and the silicon layer are in contact with each other and diffusing impurities in the metal film into the silicon layer. A method of manufacturing a semiconductor device, comprising: 10. The step of forming a gate insulating film and a gate electrode on a silicon layer, the step of forming a sidewall spacer on the side wall of the gate electrode, and the semiconductor device according to claim 3. By using the manufacturing method of 1., a step of forming a metal film doped with impurities on the entire surface of the device formed in the above step, and performing a heat treatment, a portion where the metal film and the silicon layer are in contact with each other is formed. Forming a salicide structure by forming a silicide film and diffusing impurities in the metal film into a silicon layer to form a source region or a drain region. 11. A process of forming a gate insulating film and a gate electrode on a silicon layer, a process of forming a sidewall spacer made of a doped oxide on a side wall of the gate electrode, and a process of claim 3. By using the method for manufacturing a semiconductor device described in 1 above, a step of forming a metal film doped with impurities on the entire surface of the device formed in the above step, and performing heat treatment to bring the metal film and the silicon layer into contact with each other. A salicide structure is formed by forming a silicide film in a portion where the LDD structure is formed by diffusing impurities in the metal film and impurities in the sidewall spacer into the silicon layer to form a source region or a drain region. And a step of forming a semiconductor device. 12. A method of forming a metal film doped with an impurity at least on a bottom portion of a contact hole communicating with an impurity region by using the method for manufacturing a semiconductor device according to claim 3. And a step of processing the metal film as at least a part of a metal wiring connected to the impurity region, the method for manufacturing a semiconductor device. 13. A step of forming an impurity region on a surface of a silicon substrate, and the method of manufacturing a semiconductor device according to claim 3, wherein at least a bottom portion of a contact hole communicating with the impurity region is formed. , A step of forming a metal film doped with the same conductive impurities as the impurity region and a heat treatment to form a silicide film at a position where the metal film and the silicon substrate are in contact with each other, and And a step of diffusing the impurities of 1. into the surface of the silicon substrate. 14. A step of forming a first conductivity type impurity region and a second conductivity type impurity region on a silicon substrate, and the method of manufacturing a semiconductor device according to claim 3. Forming a first metal film doped with an impurity having the same conductivity as that of the impurity region at least on the bottom of the contact hole leading to the impurity region of the first conductivity type; A step of forming a silicide film at a position where the film and the silicon substrate are in contact with each other, and a method of manufacturing a semiconductor device according to claim 3, wherein a second conductivity type impurity region is formed. Forming a second metal film doped with the same conductive impurity as the impurity region on at least the bottom of the contact hole, and forming at least one of the silicide film and the second metal film on each impurity region. The method of manufacturing a semiconductor device characterized by comprising a step of processing the at least a portion of the connection is the metal wiring. 15. The method of manufacturing a semiconductor device according to claim 12, wherein the impurity region functions as a source or a drain of a transistor. 16. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of removing a non-silicided metal film after forming the silicide film. And a method for manufacturing a semiconductor device. 17. A target used in a sputtering method, which is made of an alloy in which impurities are added to a metal material.