JPH08250046A - Image forming device and manufacture thereof - Google Patents

Image forming device and manufacture thereof

Info

Publication number
JPH08250046A
JPH08250046A JP4892695A JP4892695A JPH08250046A JP H08250046 A JPH08250046 A JP H08250046A JP 4892695 A JP4892695 A JP 4892695A JP 4892695 A JP4892695 A JP 4892695A JP H08250046 A JPH08250046 A JP H08250046A
Authority
JP
Japan
Prior art keywords
electron
insulating film
length
pair
electron source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4892695A
Other languages
Japanese (ja)
Other versions
JP3135813B2 (en
Inventor
Osamu Takamatsu
修 高松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP4892695A priority Critical patent/JP3135813B2/en
Publication of JPH08250046A publication Critical patent/JPH08250046A/en
Application granted granted Critical
Publication of JP3135813B2 publication Critical patent/JP3135813B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Electrodes For Cathode-Ray Tubes (AREA)

Abstract

PURPOSE: To make the length of an electron emitting part constant to prevent decrease of brightness and its nonuniformity of an image, by forming both end parts in a row direction of a pair of element electrodes arranged on an electron source substrate so as to be covered with an insulating film. CONSTITUTION: On the surface of an insulating substrate 1, a surface conduction electron emitting element formed of an element electrode 2 provided with an electron emitting part is arranged, to obtain an electron source of an image forming device. Here is formed an insulating film 6 so as to cover both end parts in a row direction Y of a pair of element electrodes. A length in the row direction of a pair of these element electrodes is formed preferably longer than a length in a row direction of a pair of the element electrodes not covered with the insulating film by 60μm or more. Row direction wiring 6 connected to an element electrode 2, line direction wiring 8 and the insulating film 6 are preferably formed by a screen method, thus to enable a pattern position deviation to reduce to a minium limit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は画像形成装置、特に表面
伝導型電子放出素子を用いた画像形成装置及びその製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus using a surface conduction electron-emitting device and a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来、平面型画像形成装置としては、単
純マトリックス液晶表示装置(LCD)、薄膜トランジ
スタ液晶表示装置(TFT/LCD)、プラズマディス
プレイ(PDP)、低速電子線蛍光表示管(VFD)等
がある。
2. Description of the Related Art Conventional flat panel image forming apparatuses include simple matrix liquid crystal display (LCD), thin film transistor liquid crystal display (TFT / LCD), plasma display (PDP), low-speed electron beam fluorescent display (VFD) and the like. There is.

【0003】これらの画像形成装置における発光方法の
一つとして、電子放出素子を用いて蛍光体を発光させる
方法がある。この電子放出素子としては表面伝導型電子
放出素子が一般的に知られている(M.I.Elins
on,Radio Eng.Electron Phy
s.,10,(1965))。この電子放出素子は、基
板上に形成された小面積の薄膜に、膜面に対して平行方
向に電流を流すと電子が放出する現象を利用するもので
ある。
As one of the light emitting methods in these image forming apparatuses, there is a method of causing a phosphor to emit light by using an electron emitting element. A surface conduction electron-emitting device is generally known as this electron-emitting device (MI Elins).
on, Radio Eng. Electron Phy
s. , 10, (1965)). This electron-emitting device utilizes a phenomenon in which electrons are emitted when a current is applied to a small-area thin film formed on a substrate in a direction parallel to the film surface.

【0004】表面伝導型電子放出素子の薄膜としては、
SnO2薄膜(M.I.Elinson,Radio
Eng.Electron Phys.,10,(19
65))、Au薄膜(G.Dittmer,Thin
Solid Films,9,317(1972)),
In23/SnO2薄膜(M.Hartwell an
d C.G.Fonstad,IEEE Trans.
ED Conf.,519(1975))、カーボン薄
膜(荒木 久ほか,真空,26,1,22(198
3))等が報告されている。
As the thin film of the surface conduction electron-emitting device,
SnO 2 thin film (MI Elinson, Radio)
Eng. Electron Phys. , 10, (19
65)), Au thin film (G. Dittmer, Thin.
Solid Films, 9, 317 (1972)),
In 2 O 3 / SnO 2 thin film (M. Hartwell an
d C. G. Fonstad, IEEE Trans.
ED Conf. , 519 (1975)), carbon thin film (Hiroshi Araki et al., Vacuum, 26, 1, 22 (198).
3)) etc. have been reported.

【0005】表面伝導型電子放出素子の典型的な例を図
5に示す。この電子放出素子の構成は上記のM.Har
twellによるもので、1は絶縁性の基板、12は電
子放出部形成用薄膜、3は電子放出部である。電子放出
部形成用薄膜(12)の形成は、基板(1)上にH型形
状の金属酸化物の薄膜をスパッタで形成することによっ
て行われる。次いで、フォーミングと呼ばれる通電処理
によって電子放出部(3)が形成される。フォーミング
とは、電子放出部形成用薄膜(12)の両端に電圧を印
加通電し、この電子放出部形成用薄膜(12)を局所的
に破壊・変形・変質させ、電気的に高抵抗な電子放出部
(3)を形成することである。また電子の放出は、電子
放出部形成用薄膜(12)の亀裂付近から行われる場合
もある。
A typical example of the surface conduction electron-emitting device is shown in FIG. The structure of this electron-emitting device is as described in M. Har
According to Twell, 1 is an insulating substrate, 12 is an electron emitting portion forming thin film, and 3 is an electron emitting portion. The electron emission portion forming thin film (12) is formed by forming an H-shaped metal oxide thin film on the substrate (1) by sputtering. Next, the electron emission portion (3) is formed by an energization process called forming. The forming means that a voltage is applied to both ends of the thin film (12) for forming an electron emitting portion to locally destroy, deform, and change the thin film (12) for forming an electron emitting portion, and an electron having a high electrical resistance is formed. Forming the emitting portion (3). In addition, the electrons may be emitted from the vicinity of the cracks in the thin film (12) for forming the electron emitting portion.

【0006】一方、本出願人は、微粒子が分散配置され
た電子放出材からなる電子放出部形成用薄膜(12)
を、一対の素子電極間に配置することによって、新規な
表面伝導型電子放出素子を開発し、これを技術開示した
(USP5,066,883)。この電子放出素子は、
上記従来のものより電子放出位置を精密に制御できるた
め、より高い精度で電子放出素子を配列することができ
る。この電子放出素子の典型的な例を図6に示す。図6
において、1は絶縁性の基板、2は電気的接続のための
素子電極、12は微粒子が分散配置された電子放出材か
らなる電子放出部形成用薄膜、3は電子放出部である。
On the other hand, the applicant of the present invention has found that a thin film (12) for forming an electron emitting portion, which is made of an electron emitting material in which fine particles are dispersed and arranged.
By arranging between a pair of device electrodes, a new surface conduction electron-emitting device was developed, and this was technically disclosed (USP 5,066,883). This electron-emitting device is
Since the electron emission position can be controlled more precisely than the conventional one, the electron emitting devices can be arranged with higher accuracy. A typical example of this electron-emitting device is shown in FIG. Figure 6
In the above, 1 is an insulating substrate, 2 is an element electrode for electrical connection, 12 is an electron emitting portion forming thin film made of an electron emitting material in which fine particles are dispersed and arranged, and 3 is an electron emitting portion.

【0007】上記の表面伝導型電子放出素子は、基板上
に多数形成され電子源基板が作製される。この電子源基
板は蛍光体を有するプレートと組み合わされ、次いで真
空外囲器内に設置され画像形成装置を形成する。真空外
囲器内では、電子源基板から電子が放出し、その電子が
プレートの蛍光体へ照射される。
A large number of the surface conduction electron-emitting devices described above are formed on a substrate to produce an electron source substrate. The electron source substrate is combined with a plate having a phosphor and then placed in a vacuum envelope to form an image forming device. In the vacuum envelope, electrons are emitted from the electron source substrate and the electrons irradiate the phosphor of the plate.

【0008】本出願人は、上記の表面伝導型電子放出素
子を用いて、電子源基板の作製を検討している。この電
子源基板の1例を図7に示す。この図7は、行列方向に
多数形成された電子放出素子のうち、行方向に2個、列
方向に2個(行列合計3個)の電子放出素子を含む電子
源基板の一部を表わすものである。
The present applicant is studying the production of an electron source substrate using the above surface conduction electron-emitting device. An example of this electron source substrate is shown in FIG. FIG. 7 shows a part of an electron source substrate including two electron-emitting devices in the row direction and two in the column direction (a total of three matrixes) out of a large number of electron-emitting devices formed in the matrix direction. Is.

【0009】このような電子源基板の作製方法として
は、フォトリソグラフ法や印刷法等がある。フォトリソ
グラフ法はパターニング精度が良好である。しかし、4
0インチ以上の大面積の画像表示装置を作製する場合
は、大型の成膜装置や露光装置が必要になり、さらに用
いるプロセス材料も大量に必要となりコストが高くな
る。そのため、大面積の画像形成装置を作製する場合
は、印刷法で行うことがコスト的に望ましい。
As a method of manufacturing such an electron source substrate, there are a photolithography method, a printing method and the like. The photolithographic method has good patterning accuracy. But 4
In the case of manufacturing an image display device having a large area of 0 inch or more, a large-sized film forming device and an exposure device are required, and a large amount of process materials to be used are also required, resulting in an increase in cost. Therefore, when manufacturing an image forming apparatus having a large area, it is preferable to use a printing method in terms of cost.

【0010】[0010]

【発明が解決しようとする課題】しかし印刷法では、電
子放出素子を基板上に形成して電子源基板を作製する
際、パターン寸法精度および位置合わせ精度が低いとい
う問題がある。特に図7および図8において、素子電極
(2)と絶縁膜(6)とのパターン寸法精度および位置
合わせ精度に問題が発生する。すなわち、図8(a)に
示すように、2つの絶縁膜(6)は、その中央に素子電
極(2)を位置するように形成されるべきでものである
が(このときP1=Q)、図8(b)に示すように2つ
の絶縁膜(6)が位置ズレを起こす。その結果、絶縁膜
に覆われていない一対の素子電極の列方向の長さが短く
なり、その素子電極間に形成される電子放出部の列方向
の長さが短くなる(P1>P2=P1−R1)。これが原因
で輝度が低下したり輝度ムラが発生する。なお図8にお
いて、Qは素子電極(2)の列方向の長さ、P1及びP2
は絶縁膜に覆われていない素子電極の列方向の長さ、R
1は絶縁膜(6)の位置ズレによって覆われた素子電極
の列方向の長さを示す。
However, the printing method has a problem that the pattern dimensional accuracy and the alignment accuracy are low when the electron-emitting device is formed on the substrate to manufacture the electron source substrate. Particularly, in FIGS. 7 and 8, problems occur in the pattern dimensional accuracy and the alignment accuracy of the device electrode (2) and the insulating film (6). That is, as shown in FIG. 8A, the two insulating films (6) should be formed so that the element electrode (2) is located at the center thereof (at this time, P 1 = Q). , The two insulating films (6) are displaced as shown in FIG. 8 (b). As a result, the length in the column direction of the pair of device electrodes not covered with the insulating film becomes shorter, and the length in the column direction of the electron emitting portion formed between the device electrodes becomes shorter (P 1 > P 2). = P 1 -R 1). Due to this, the brightness is lowered or the brightness becomes uneven. In FIG. 8, Q is the length of the element electrode (2) in the column direction, P 1 and P 2
Is the length in the column direction of the device electrode not covered by the insulating film, R
Reference numeral 1 denotes the length in the column direction of the device electrode covered by the positional deviation of the insulating film (6).

【0011】そこで本発明の目的は、電子源基板の絶縁
膜形成時に位置ズレが生じても一対の素子電極間の電子
放出部の長さが一定になるようにし、画像の輝度が低下
せず且つ輝度ムラが少ない画像形成装置を提供すること
である。さらに印刷法によって電子源基板を作製し、大
画面の画像形成装置を低コストで提供することである。
Therefore, an object of the present invention is to make the length of the electron emitting portion between the pair of device electrodes constant even if the position shift occurs during the formation of the insulating film of the electron source substrate, so that the brightness of the image does not decrease. Moreover, it is an object of the present invention to provide an image forming apparatus with less uneven brightness. Another object is to provide an electron source substrate by a printing method and provide a large-screen image forming apparatus at low cost.

【0012】[0012]

【課題を解決するための手段】本発明者は、上記の目的
を達成するために種々の検討を重ねた結果、本発明を完
成した。すなわち本発明は、表面伝導型電子放出素子が
配列された電子源基板を備えた画像形成装置において、
絶縁膜が、一対の素子電極の列方向の両端部を覆うよう
に形成されていることを特徴とする画像形成装置に関す
る。また、電子源基板上の配線および絶縁膜をスクリー
ン印刷法によって形成する上記画像形成装置の製造方法
に関する。
The present inventor has completed the present invention as a result of various studies in order to achieve the above object. That is, the present invention provides an image forming apparatus including an electron source substrate on which surface conduction electron-emitting devices are arranged,
The present invention relates to an image forming apparatus, wherein an insulating film is formed so as to cover both ends of a pair of element electrodes in the column direction. The present invention also relates to a method for manufacturing the image forming apparatus, in which the wiring and the insulating film on the electron source substrate are formed by screen printing.

【0013】以下本発明を詳細に説明する。The present invention will be described in detail below.

【0014】図1に本発明の電子源基板の平面図を示す
(同図において、X軸方向を行方向、Y軸方向を列方向
とする)。この図1は、絶縁性の基板(1)上で行列方
向に多数形成された電子放出素子のうち、行方向に2
個、列方向に2個(行列合計3個)の素子電極を含む電
子源基板の一部を表わしたものである。また図2に、図
1のA−A線断面図を示す。
FIG. 1 is a plan view of the electron source substrate of the present invention (in the figure, the X-axis direction is the row direction and the Y-axis direction is the column direction). This FIG. 1 shows that two of the electron-emitting devices formed in the matrix direction on the insulating substrate (1) are arranged in the row direction.
3 shows a part of an electron source substrate including two element electrodes in the column direction (three in matrix). Further, FIG. 2 shows a sectional view taken along the line AA of FIG.

【0015】本発明はこのような電子源基板上におい
て、絶縁膜が、一対の素子電極の列方向の両端部を覆う
ように形成されていることを特徴とする。すなわち図2
(a)において、素子電極(2)の長さ(Q)が、絶縁
膜に覆われていない素子電極の列方向の長さ、すなわち
一対の絶縁膜(6)間の距離(P1)より長いことが特
徴である。印刷法でのパターンの位置ズレは多くとも±
30μm程度であるので、60μm以上長いことが望ま
しい。素子電極の長さをこのように設定することによっ
て、図2(b)に示すように、絶縁膜形成時の位置ズレ
(R2)が生じても絶縁膜に覆われていない素子電極の
列方向の長さ(P2)は一定である(P2=P1)。した
がって、絶縁膜に覆われていない一対の素子電極間の全
体に電子放出部形成用薄膜(12)を形成すると(図1
参照)、この薄膜(12)に形成される電子放出部
(3)の長さも絶縁膜の位置ズレにかかわらず一定にな
るため、輝度の低下が抑えられ、輝度ムラも減少する。
The present invention is characterized in that an insulating film is formed on such an electron source substrate so as to cover both ends in the column direction of the pair of device electrodes. That is, FIG.
In (a), the length (Q) of the device electrode (2) is determined by the length in the column direction of the device electrode not covered with the insulating film, that is, the distance (P 1 ) between the pair of insulating films (6). The feature is that it is long. The positional deviation of the pattern in the printing method is at most ±
Since it is about 30 μm, it is desirable that it is longer than 60 μm. By setting the lengths of the element electrodes in this way, as shown in FIG. 2B, a row of element electrodes that is not covered with the insulating film even if a positional deviation (R 2 ) occurs when the insulating film is formed. The length in the direction (P 2 ) is constant (P 2 = P 1 ). Therefore, when the thin film (12) for forming the electron emission portion is formed between the pair of device electrodes not covered with the insulating film (see FIG. 1).
Since the length of the electron emitting portion (3) formed in this thin film (12) is constant regardless of the positional deviation of the insulating film, the decrease in brightness is suppressed and the uneven brightness is also reduced.

【0016】なお、素子電極の上記の長さの上限は、画
素ピッチ(図4参照)の長さ未満であり、実際には、印
刷の分解能によるため画素ピッチより50μm程度短く
なる。
The upper limit of the above-mentioned length of the element electrode is less than the length of the pixel pitch (see FIG. 4), and in actuality, it is shorter than the pixel pitch by about 50 μm because of the printing resolution.

【0017】図1において、一対の素子電極(2)の電
極間隔は数μm〜数百μmが適当であり、素子電極
(2)の厚さは数百〜数千オングストロームが適当であ
る。素子電極の行方向および列方向の長さは、それぞれ
ともに数百〜1000μmが適当である。
In FIG. 1, the electrode interval between the pair of device electrodes (2) is preferably several μm to several hundred μm, and the thickness of the device electrodes (2) is several hundred to several thousand angstroms. The lengths in the row direction and the column direction of the device electrodes are each preferably several hundreds to 1000 μm.

【0018】この一対の素子電極間に形成される電子放
出部形成用薄膜(12)の厚さは、数十〜数千オングス
トロームが適当である。
The electron emitting portion forming thin film (12) formed between the pair of device electrodes preferably has a thickness of several tens to several thousands angstroms.

【0019】接続電極(4)および列方向配線(5)は
それぞれ素子電極(2)と接続している。これら接続電
極および列方向配線の厚さは数μm〜数十μmが適当で
ある。接続電極の行方向の長さは数十〜数百μmが適当
であり、接続電極の列方向の長さは数百μmが適当であ
る。列方向配線の行方向の長さは100〜300μmが
適当であり、列方向配線の列方向の長さは設計に基ず
き、基板の列方向の長さに従って形成される。
The connection electrode (4) and the column-direction wiring (5) are connected to the device electrode (2), respectively. The thickness of these connection electrodes and the wiring in the column direction is suitably several μm to several tens of μm. The length of the connection electrodes in the row direction is suitably several tens to several hundreds of μm, and the length of the connection electrodes in the column direction is suitably several hundreds μm. The length of the column-direction wiring in the row direction is preferably 100 to 300 μm, and the length of the column-direction wiring in the column direction is based on the design and is formed according to the length of the substrate in the column direction.

【0020】絶縁膜(6)は帯状に形成され、列方向配
線(5)と交差するように設置される。この絶縁膜の厚
さは30〜50μmが適当である。絶縁膜の行方向の長
さは設計に基ずき、基板の行方向の長さに従って形成さ
れ、絶縁膜の列方向の長さは200〜600μmが適当
である。
The insulating film (6) is formed in a strip shape and is installed so as to intersect the column-direction wiring (5). A suitable thickness of this insulating film is 30 to 50 μm. The length of the insulating film in the row direction is based on the design, and is formed according to the length of the substrate in the row direction. The length of the insulating film in the column direction is preferably 200 to 600 μm.

【0021】この帯状の絶縁膜(6)の上部に重ねて行
方向配線(8)が設けられる。この行方向配線(8)は
コンタクトホール(7)を通じて接続電極(4)と接続
している。行方向配線の厚さは40〜60μmが適当で
ある。行方向配線の行方向の長さは設計に基ずいて基板
の行方向の長さに従って形成され、行方向配線の列方向
の長さは100〜500μmが適当である。
A row-direction wiring (8) is provided over the strip-shaped insulating film (6). The row-direction wiring (8) is connected to the connection electrode (4) through the contact hole (7). A suitable thickness of the wiring in the row direction is 40 to 60 μm. The length in the row direction of the row-direction wiring is formed according to the length in the row direction of the substrate based on the design, and the length in the column direction of the row-direction wiring is preferably 100 to 500 μm.

【0022】基板の材料としては、絶縁性材料が用いら
れ、例えば、石英ガラス、Na等の不純物の含有量を低
減したガラス、青板ガラス、スパッタ法等によりSiO
2を積層した青板ガラス、アルミナ等のセラミック類な
どが挙げられる。
An insulating material is used as the material of the substrate. For example, quartz glass, glass with a reduced content of impurities such as Na, soda-lime glass, and SiO by a sputtering method or the like.
Examples include soda-lime glass laminated with 2 , ceramics such as alumina.

【0023】絶縁膜の材料としては、一般的なガラスペ
ーストを用いることができる。
As a material for the insulating film, a general glass paste can be used.

【0024】素子電極、接続電極、行方向配線および列
方向配線の材料は、導電性を有するものであれば制限は
ないが、例えば、Ni・Cr・Au・Mo・W・Pt・
Ti・Al・Cu・Pd等の金属またはこれらの合金、
Pd・Ag・Au・RuO2・Pd−Ag等の金属や金
属酸化物とガラス類とから構成される印刷導体、ポリシ
リコン等の半導体材料、In23−SnO2等の透明導
電体などが挙げられる。
The material of the device electrodes, connection electrodes, row-direction wirings and column-direction wirings is not limited as long as it has conductivity. For example, Ni, Cr, Au, Mo, W, Pt.
Metals such as Ti / Al / Cu / Pd or their alloys,
Pd · Ag · Au · RuO 2 · Pd-Ag or the like of the metal or metal oxide and printed conductor composed of a glasses, semiconductor materials such as polysilicon, a transparent conductive material such as In 2 O 3 -SnO 2, etc. Is mentioned.

【0025】電子放出部形成用薄膜の材料としては、例
えば、Pt・Ru・Ag・Au・Ti・In・Cu・C
r・Fe・Zn・Sn・Ta・W・Pb・Ag−Mg・
Ni−Cu等の金属、PdO・SnO2・In23・P
bO・Sb23等の酸化物、HfB2・ZrB2・LaB
6・CeB6・YB4・GdB4等のホウ化物、TiC・Z
rC・HfC・TaC・SiC・WC等の炭化物、Ti
N・ZrN・HfN等の窒化物、Si・Ge等の半導
体、カーボンなどが挙げられる。
Examples of the material of the thin film for forming the electron emitting portion include Pt, Ru, Ag, Au, Ti, In, Cu, and C.
r ・ Fe ・ Zn ・ Sn ・ Ta ・ W ・ Pb ・ Ag-Mg ・
Ni-Cu or the like metal, PdO · SnO 2 · In 2 O 3 · P
oxides such as bO · Sb 2 O 3, HfB 2 · ZrB 2 · LaB
Borides of 6・ CeB 6・ YB 4・ GdB 4, etc., TiC ・ Z
Carbide such as rC / HfC / TaC / SiC / WC, Ti
Examples thereof include nitrides such as N / ZrN / HfN, semiconductors such as Si / Ge, and carbon.

【0026】電子放出部形成用薄膜は上記材料の微粒子
膜からなる。微粒子膜とは、複数の微粒子が膜状に集合
したものであり、その微細構造は、微粒子が個々に分散
配置した状態に加えて、微粒子が互いに隣接または重な
りあった状態(島状も含む)の構造を有する。
The thin film for forming the electron emitting portion is a fine particle film of the above material. A fine particle film is an aggregate of a plurality of fine particles in a film form, and its fine structure has a state in which the fine particles are individually dispersed and arranged, and the fine particles are adjacent to each other or overlap each other (including island shape). It has the structure of.

【0027】以上の構成が1個の表面伝導型電子放出素
子単位(1個の表面伝導型電子放出素子を含む配線単
位)となり、この単位が基板(1)上に行列状に多数設
けられ、電子源基板が形成される。
The above structure constitutes one surface conduction electron-emitting device unit (wiring unit including one surface conduction electron-emitting device), and a large number of these units are provided in a matrix on the substrate (1). An electron source substrate is formed.

【0028】次に、本発明の電子源基板の製造方法を、
図4の(I)〜(V)を参照しながら説明する。この図
4は、3行3列で合計9個の表面伝導型電子放出素子単
位を配置した場合を表わす。
Next, a method of manufacturing the electron source substrate of the present invention will be described.
This will be described with reference to (I) to (V) of FIG. FIG. 4 shows a case where a total of 9 surface conduction electron-emitting device units are arranged in 3 rows and 3 columns.

【0029】工程(I):よく洗浄した基板(1)の表
面上に素子電極に使用する前記導電性材料からなる導電
性薄膜を形成する。この基板をフォトリソグラフ法によ
って微細加工し、図4(I)に示すように素子電極
(2)のパターンを形成する。このとき、絶縁膜(6)
の形成時(工程(III))の位置ズレを考慮してパタ
ーン寸法を設計する。すなわち、絶縁膜が、一対の素子
電極の列方向の両端部を覆うようにパターン寸法を設計
する。このとき、一対の素子電極の列方向の長さが、絶
縁膜に覆われていない一対の素子電極の列方向の長さよ
り60μm以上長くなるように設計することが望まし
い。
Step (I): A conductive thin film made of the above-mentioned conductive material used for the device electrode is formed on the surface of the substrate (1) which has been thoroughly washed. This substrate is finely processed by photolithography to form a pattern of device electrodes (2) as shown in FIG. 4 (I). At this time, the insulating film (6)
The pattern dimension is designed in consideration of the positional deviation at the time of forming (step (III)). That is, the pattern dimension is designed such that the insulating film covers both ends of the pair of device electrodes in the column direction. At this time, it is desirable that the length of the pair of device electrodes in the column direction is designed to be 60 μm or more longer than the length of the pair of device electrodes not covered with the insulating film in the column direction.

【0030】工程(II):接続電極および列方向配線
に用いられる前記導電性材料からなる導電性ペースト
を、スクリーン印刷法によって上記工程(I)の基板上
に塗布し、次いで焼成して図4(II)に示すように接
続電極(4)及び列方向配線(5)のパターンを形成す
る。
Step (II): A conductive paste made of the above-mentioned conductive material used for the connection electrodes and the column-direction wiring is applied on the substrate of the above step (I) by a screen printing method, and then fired to form the conductive paste shown in FIG. As shown in (II), a pattern of connection electrodes (4) and column-direction wirings (5) is formed.

【0031】工程(III):絶縁性ペースト(例え
ば、ガラスペースト)を工程(I)で設計したパターン
寸法にしたがってスクリーン印刷法によって塗布し、次
いで焼成を行い、帯状の絶縁膜(6)のパターン(図4
(III))を形成する。この絶縁膜(6)に、コンタ
クトホール(7)を接続電極(4)上に通じるように開
ける。
Step (III): An insulating paste (for example, glass paste) is applied by a screen printing method according to the pattern size designed in the step (I), and then baked to form a pattern of a band-shaped insulating film (6). (Fig. 4
(III)) is formed. A contact hole (7) is opened in this insulating film (6) so as to communicate with the connection electrode (4).

【0032】工程(IV):上記の絶縁膜上に、行方向
配線に用いられる前記導電性材料からなる導電性ペース
トを、スクリーン印刷法によって印刷し、次いで焼成を
行い、図4(IV)に示すように行方向配線(8)を形
成する。この行方向配線(8)はコンタクトホール
(7)を通して接続電極(4)へ通電可能となるように
形成する。
Step (IV): On the above-mentioned insulating film, a conductive paste made of the above-mentioned conductive material used for the row wiring is printed by a screen printing method, followed by firing, and as shown in FIG. 4 (IV). The row wiring (8) is formed as shown. The row-direction wiring (8) is formed so that the connection electrode (4) can be energized through the contact hole (7).

【0033】工程(V):前記材料からなる電子放出部
形成用薄膜を、工程(IV)で形成された基板の表面上
の全面に形成する。次いで、フォトリソグラフ法によっ
て図4(V)に示すように電子放出部形成用薄膜のパタ
ーニングを行い、これに電子放出部(3)を形成する。
このとき、電子放出部形成用薄膜は、一対の素子電極間
の全体に形成されることが望ましい。以上のようにして
本発明の電子源基板が作製される。
Step (V): An electron emitting portion forming thin film made of the above material is formed on the entire surface of the substrate formed in the step (IV). Next, as shown in FIG. 4 (V), the thin film for forming the electron emitting portion is patterned by the photolithography method, and the electron emitting portion (3) is formed thereon.
At this time, it is desirable that the electron emission part forming thin film is formed over the entire space between the pair of device electrodes. The electron source substrate of the present invention is manufactured as described above.

【0034】さらに、このようにして作製された電子源
基板は、その上部にフェースプレーとが配置され、真空
外囲器内に設置される。図3に、図1の電子源基板のB
−B線断面図およびこの電子源基板の上部に組み合わさ
れたフェースプレートの断面図を示す。フェースプレー
トは、ガラス基板(9)の表面上に蛍光体層(10)お
よびメタルバック層(11)が積層されている。
Further, the electron source substrate manufactured in this manner has a face plate arranged on the top thereof and is installed in a vacuum envelope. FIG. 3 shows B of the electron source substrate of FIG.
The -B line sectional view and the sectional view of the face plate combined with the upper part of this electron source substrate are shown. The face plate has a phosphor layer (10) and a metal back layer (11) laminated on the surface of a glass substrate (9).

【0035】この真空外囲器内において、接続電極に通
電可能な行方向配線(8)、及び列方向配線(5)を通
じて素子電極(2)間に電圧を印加し、上方のメタルバ
ック層(11)へはこれを正の電位として電圧を加え
る。この操作によって一対の素子電極(2)間の電子放
出部(3)から電子が放出される。放出された電子はメ
タルバック層(11)を通って蛍光層(10)に照射さ
れ、蛍光が発生し、画像が形成される。このように本発
明の電子源基板は、画像形成装置において発光素子や平
面型表示装置として適用される。
In this vacuum envelope, a voltage is applied between the element electrodes (2) through the row-direction wirings (8) and the column-direction wirings (5) capable of energizing the connection electrodes, and the upper metal back layer ( A voltage is applied to 11) with this as a positive potential. By this operation, electrons are emitted from the electron emitting portion (3) between the pair of device electrodes (2). The emitted electrons pass through the metal back layer (11) and are applied to the fluorescent layer (10) to generate fluorescence, and an image is formed. As described above, the electron source substrate of the present invention is applied as a light emitting element or a flat panel display in an image forming apparatus.

【0036】[0036]

【実施例】以下、本発明を図3および図4を参照しなが
ら、実施例によりさらに説明するが、本発明はこれらに
限定するものではない。
EXAMPLES The present invention will now be further described by way of examples with reference to FIGS. 3 and 4, but the present invention is not limited thereto.

【0037】実施例1 工程(I):青板ガラスからなる基板(1)を準備し、
よく洗浄した。この基板(1)の表面上にスパッタ蒸着
法によって金属薄膜を形成した。次いで、フォトリソエ
ッチング法によって図4(I)に示すように素子電極
(2)を形成した。素子電極(2)は、厚さ50オング
ストロームのTiを下引層とし、厚さ1000オングス
トロームのNi薄膜から成っている。また、一対の素子
電極間の間隔を2μm、素子電極の列方向の長さを26
0μm、行方向の長さを300μmとした。このときパ
ターン寸法として、完成した電子源基板上で、絶縁膜に
覆われていない一対の素子電極の列方向の長さが200
μmとなるように、一対の素子電極(2)の列方向の両
端からそれぞれ30μmの領域が絶縁膜(6)と重なる
パターンを設計した。すなわちこのパターンでは、完成
した電子源基板状で、一対の素子電極の列方向の長さ
が、絶縁膜に覆われていない一対の素子電極の列方向の
長さより60μm長い。
Example 1 Step (I): A substrate (1) made of soda lime glass was prepared,
Washed well. A metal thin film was formed on the surface of this substrate (1) by a sputter deposition method. Then, a device electrode (2) was formed by a photolithographic etching method as shown in FIG. The device electrode (2) is composed of a Ti thin film having a thickness of 50 nm and a Ni thin film having a thickness of 1000 nm. The distance between the pair of device electrodes is 2 μm, and the length of the device electrodes in the column direction is 26 μm.
The length was 0 μm and the length in the row direction was 300 μm. At this time, as a pattern dimension, on the completed electron source substrate, the length in the column direction of the pair of device electrodes not covered with the insulating film is 200.
A pattern was designed such that regions of 30 μm from both ends of the pair of device electrodes (2) in the column direction overlap with the insulating film (6) so as to be μm. That is, in this pattern, the length in the column direction of the pair of device electrodes in the completed electron source substrate shape is 60 μm longer than the length in the column direction of the pair of device electrodes not covered with the insulating film.

【0038】工程(II):Agペーストインキをスク
リーン印刷法によって上記工程(I)の基板上に塗布
し、図4(II)に示すように接続電極(4)および列
方向配線(5)のパターンを形成した。次いでこれを焼
成した。
Step (II): Ag paste ink is applied on the substrate of the step (I) by screen printing, and as shown in FIG. 4 (II), the connection electrodes (4) and the column-direction wirings (5) are formed. A pattern was formed. It was then fired.

【0039】工程(III):ガラスを主成分としたペ
ーストを、工程(I)で設計したパターン寸法にしたが
ってスクリーン印刷法によって塗布し、次いで焼成を行
い、帯状の絶縁膜(6)のパターン(図4(III))
を形成した。この絶縁膜(6)に、コンタクトホール
(7)を接続電極(4)へ通じるように開けた。絶縁膜
(6)の厚さは15μm、列方向の長さは400μmで
あった。また、設計したパターン寸法に対する絶縁膜
(6)の列方向の位置ズレは20μmであった。
Step (III): A paste containing glass as a main component is applied by a screen printing method according to the pattern dimension designed in the step (I), and then baked to form a pattern () of a strip-shaped insulating film (6). (Fig. 4 (III))
Was formed. A contact hole (7) was opened in this insulating film (6) so as to reach the connection electrode (4). The insulating film (6) had a thickness of 15 μm and a length in the column direction of 400 μm. The positional deviation of the insulating film (6) in the column direction from the designed pattern dimension was 20 μm.

【0040】工程(IV):上記絶縁膜(6)の表面上
に、Agペーストをスクリーン印刷法によって印刷し、
次いで焼成を行い、図4(IV)に示すように行方向配
線(8)を形成した。この行方向配線(8)はコンタク
トホール(7)を通して接続電極(4)へ通電が可能と
なるようにした。行方向配線(8)の厚さは20μm、
列方向の長さは300μmであった。
Step (IV): Ag paste is printed on the surface of the insulating film (6) by a screen printing method,
Then, firing was performed to form row wirings (8) as shown in FIG. The row-direction wiring (8) was made to be able to conduct electricity to the connection electrode (4) through the contact hole (7). The row-direction wiring (8) has a thickness of 20 μm,
The length in the column direction was 300 μm.

【0041】工程(V):有機金属溶液の塗布・焼成に
よって、厚さ約200オングストロームのPd微粒子か
らなる電子放出部形成用薄膜を、工程(IV)で形成し
た基板の表面上の全面に形成した。次いで、フォトリソ
グラフ法によって図4(V)に示すように上記薄膜のパ
ターニングを行い、これに電子放出部(3)を形成し
た。このとき、電子放出部形成用薄膜は一対の素子電極
間の全体に形成した。
Step (V): An electron emitting portion forming thin film made of Pd particles having a thickness of about 200 angstroms is formed on the entire surface of the substrate formed in step (IV) by applying and baking an organometallic solution. did. Next, the thin film was patterned by photolithography as shown in FIG. 4 (V), and an electron emitting portion (3) was formed on the thin film. At this time, the electron emission portion forming thin film was formed over the entire area between the pair of device electrodes.

【0042】以上の工程によって、列方向配線(5)お
よび行方向配線(8)をそれぞれ10本ずつ形成し、1
00個の表面伝導型電子放出素子単位が行列状に配列し
た本発明の電子源基板を作製した。このとき、素子配列
のピッチを行列ともに600μmとなるように作製し
た。この電子源基板は、工程(III)において絶縁膜
(6)の位置ズレが生じたが、電子放出部(3)の長さ
に変化はなかった(設計通り200μmであった。)。
By the above process, 10 column-direction wirings (5) and 10 row-direction wirings (8) are formed, respectively.
An electron source substrate of the present invention was prepared in which 00 surface conduction electron-emitting device units were arranged in a matrix. At this time, the pitch of the element array was made to be 600 μm for both the matrix. In this electron source substrate, the position of the insulating film (6) was displaced in the step (III), but the length of the electron emitting portion (3) was not changed (200 μm as designed).

【0043】次に上記の電子源基板を、図3に示すよう
に5mmの間隔でフェースプレートと対面させて組み合
せ、真空外囲器の中に設置した。フェースプレートのガ
ラス基板(9)は青板ガラスからなるものを用いた。蛍
光体層(10)形成は、感光性樹脂に蛍光体を混合して
スラリー状とし、これをガラス基板(9)へ塗布、乾燥
した後、フォトリソグラフ法によってパターニング形成
した。メタルバック層(11)の形成は、蛍光体層(1
0)の表面上にフィルミング処理を行った後、真空蒸着
によって厚さ約300オングストロームのAl薄膜を成
膜し、次いでこれを焼成することによりフィルム層を焼
失させて形成した。
Next, as shown in FIG. 3, the above-mentioned electron source substrate was assembled so as to face the face plate at intervals of 5 mm, and was installed in a vacuum envelope. The glass substrate (9) of the face plate was made of soda lime glass. The phosphor layer (10) was formed by mixing a photosensitive resin with a phosphor to form a slurry, coating the slurry on the glass substrate (9), drying the slurry, and then patterning the slurry by photolithography. The metal back layer (11) is formed by using the phosphor layer (1
After the filming treatment was performed on the surface of (0), an Al thin film having a thickness of about 300 angstrom was formed by vacuum vapor deposition, and then the film was burned to burn off the film layer.

【0044】実施例2 基板(1)を40cm角の大きさ(1辺の長さが40c
mの正方形)とし、表面伝導型電子放出素子単位を行列
方向にそれぞれ350個ずつ(行列合計122500
個)配置した以外は、実施例1と同様な電子源基板を作
製した。この電子源基板を実施例1と同様にしてフェー
スプレートと組み合せ、真空外囲器中に設置した。
Example 2 The substrate (1) was 40 cm square (the length of one side was 40 c).
m squares), and 350 surface conduction electron-emitting device units are arranged in the matrix direction (a total of 122500 matrixes).
An electron source substrate similar to that of Example 1 was prepared except that the number of the above was set. This electron source substrate was combined with a face plate in the same manner as in Example 1 and placed in a vacuum envelope.

【0045】フェースプレートついては、蛍光体(2
2)をR、G、Bの各色によって塗り分けした以外は実
施例1と同様なものを使用した。
For the face plate, the phosphor (2
The same one as in Example 1 was used except that 2) was separately painted in each color of R, G and B.

【0046】実施例3 以下の記載以外は実施例1と同様にして電子源基板を作
製した。素子電極(2)の列方向の長さを500μm、
行方向の長さを250μmとした。このときのパターン
寸法として、完成した電子源基板上で、絶縁膜に覆われ
ていない一対の素子電極の列方向の長さが440μmと
なるように、一対の素子電極(2)の列方向の両端から
それぞれ30μmの領域が絶縁膜(6)と重なるパター
ンを設計した。すなわちこのパターンでは、完成した電
子源基板状で、一対の素子電極の列方向の長さが、絶縁
膜に覆われていない一対の素子電極の列方向の長さより
60μm長い。
Example 3 An electron source substrate was manufactured in the same manner as in Example 1 except for the following description. The length in the column direction of the device electrode (2) is 500 μm,
The length in the row direction was 250 μm. As a pattern dimension at this time, on the completed electron source substrate, the pair of device electrodes (2) are arranged in the column direction such that the length of the pair of device electrodes not covered with the insulating film in the column direction is 440 μm. A pattern was designed in which regions of 30 μm from both ends overlap the insulating film (6). That is, in this pattern, the length in the column direction of the pair of device electrodes in the completed electron source substrate shape is 60 μm longer than the length in the column direction of the pair of device electrodes not covered with the insulating film.

【0047】また、基板(1)を40cm角の大きさと
し、電子放出素子の素子配列のピッチを840μmに設
定し、表面伝導型電子放出素子単位を行列方向にそれぞ
れ350個ずつ(行列合計122500個)配置した。
Further, the substrate (1) was set to a size of 40 cm square, the element array pitch of the electron-emitting devices was set to 840 μm, and 350 surface-conduction electron-emitting device units were arranged in the matrix direction (a total of 122500 matrix) ) I placed it.

【0048】上記の電子源基板を実施例1と同様にして
フェースプレートと組み合せ、真空外囲器中に設置し
た。
The above electron source substrate was combined with a face plate in the same manner as in Example 1 and placed in a vacuum envelope.

【0049】フェースプレートついては、蛍光体(2
2)をR、G、Bの各色によって塗り分けした以外は実
施例1と同様なものを使用した。
Regarding the face plate, the phosphor (2
The same one as in Example 1 was used except that 2) was separately painted in each color of R, G and B.

【0050】(評価方法および評価結果)上記各実施例
の電子源基板の列方向配線(5)および行方向配線
(8)に所定の電圧を印加した。その後、フェースプレ
ートのメタルバック層(11)をアノード電極として、
これに電子の引き出し電圧3kVを印加した。列方向配
線(5)および行方向配線(8)の印加電圧を14Vへ
上げたところ、電子が電子放出部(3)から放出され
た。この放出電子量を印加電圧によって調整して、蛍光
体層(10)を任意に発光させ画像を形成した。実施例
1〜3のいずれの電子源基板においても画像は均一であ
り、画像の輝度の低下および輝度ムラは生じていなかっ
た。
(Evaluation Method and Evaluation Results) A predetermined voltage was applied to the column-direction wiring (5) and the row-direction wiring (8) of the electron source substrate of each of the above-mentioned examples. Then, using the metal back layer (11) of the face plate as an anode electrode,
An electron extraction voltage of 3 kV was applied to this. When the voltage applied to the column-direction wiring (5) and the row-direction wiring (8) was raised to 14 V, electrons were emitted from the electron emitting portion (3). The amount of emitted electrons was adjusted by the applied voltage, and the phosphor layer (10) was arbitrarily made to emit light to form an image. The image was uniform on any of the electron source substrates of Examples 1 to 3, and there was no decrease in image brightness or uneven brightness.

【0051】[0051]

【発明の効果】以上の説明から明らかなように本発明に
よれば、電子源基板の絶縁膜形成時において位置ズレが
生じても、絶縁膜に覆われていない一対の素子電極の列
方向の長さが一定であり、この素子電極間に形成される
電子放出部の長さも一定であるため、輝度の低下および
輝度ムラを抑えることができる。さらに、印刷法によっ
て電子源基板を作製するため、大画面の画像形成装置を
低コストで製造できる。
As is apparent from the above description, according to the present invention, even if a positional deviation occurs during the formation of the insulating film on the electron source substrate, the pair of device electrodes not covered with the insulating film are arranged in the column direction. Since the length is constant and the length of the electron emitting portion formed between the device electrodes is also constant, it is possible to suppress a decrease in brightness and uneven brightness. Furthermore, since the electron source substrate is manufactured by the printing method, a large-screen image forming apparatus can be manufactured at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の電子源基板の平面図である。FIG. 1 is a plan view of an electron source substrate of the present invention.

【図2】図(a)は図1におけるA−A線断面図であ
り、図(b)は絶縁膜形成時に位置ズレが生じた場合の
図1におけるA−A線断面図である。
2A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line AA in FIG. 1 in the case where misalignment occurs during the formation of an insulating film.

【図3】図(a)は電子源基板の上部に組み合わされた
フェースプレートの断面図であり、図(b)は図1にお
けるB−B線断面図である。
3A is a cross-sectional view of a face plate combined with an upper portion of an electron source substrate, and FIG. 3B is a cross-sectional view taken along line BB in FIG.

【図4】本発明の電子源基板の製造工程を示した平面図
である。
FIG. 4 is a plan view showing a manufacturing process of the electron source substrate of the present invention.

【図5】図(a)は従来の表面伝導型電子放出素子の平
面図であり、図(b)は図(a)におけるC−C線断面
図である。
5A is a plan view of a conventional surface conduction electron-emitting device, and FIG. 5B is a cross-sectional view taken along the line CC in FIG. 5A.

【図6】図(a)は従来の表面伝導型電子放出素子の平
面図であり、図(b)は図(a)におけるD−D線断面
図である。
FIG. 6A is a plan view of a conventional surface conduction electron-emitting device, and FIG. 6B is a sectional view taken along line DD in FIG.

【図7】図6の表面伝導型電子放出素子を備えた従来の
電子源基板の平面図である。
FIG. 7 is a plan view of a conventional electron source substrate including the surface conduction electron-emitting device of FIG.

【図8】図(a)は図7におけるF−F線断面図であ
り、図(b)は絶縁膜形成時に位置ズレが生じた場合の
図7におけるF−F線断面図である。
8A is a cross-sectional view taken along the line FF in FIG. 7, and FIG. 8B is a cross-sectional view taken along the line FF in FIG. 7 in the case where misalignment occurs during formation of an insulating film.

【符号の説明】[Explanation of symbols]

1 基板 2 素子電極 3 電子放出部 4 接続電極 5 列方向配線 6 絶縁膜 7 コンタクトホール 8 行方向配線 9 ガラス基板 10 蛍光体層 11 メタルバック層 12 電子放出部形成用薄膜 1 Substrate 2 Element Electrode 3 Electron Emission Section 4 Connection Electrode 5 Column Direction Wiring 6 Insulation Film 7 Contact Hole 8 Row Direction Wiring 9 Glass Substrate 10 Phosphor Layer 11 Metal Back Layer 12 Thin Film for Electron Emission Section Formation

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 表面伝導型電子放出素子が配列された電
子源基板を備えた画像形成装置において、絶縁膜が、一
対の素子電極の列方向の両端部を覆うように形成されて
いることを特徴とする画像形成装置。
1. In an image forming apparatus including an electron source substrate on which surface conduction electron-emitting devices are arranged, an insulating film is formed so as to cover both ends of a pair of device electrodes in the column direction. A characteristic image forming apparatus.
【請求項2】 一対の素子電極の列方向の長さが、絶縁
膜に覆われていない一対の素子電極の列方向の長さより
60μm以上長い請求項1記載の画像形成装置。
2. The image forming apparatus according to claim 1, wherein the length in the column direction of the pair of element electrodes is 60 μm or more longer than the length in the column direction of the pair of element electrodes not covered with the insulating film.
【請求項3】 電子源基板上の配線および絶縁膜をスク
リーン印刷法によって形成する請求項1または2記載の
画像形成装置の製造方法。
3. The method of manufacturing an image forming apparatus according to claim 1, wherein the wiring and the insulating film on the electron source substrate are formed by a screen printing method.
JP4892695A 1995-03-09 1995-03-09 Image forming apparatus and method of manufacturing the same Expired - Fee Related JP3135813B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4892695A JP3135813B2 (en) 1995-03-09 1995-03-09 Image forming apparatus and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4892695A JP3135813B2 (en) 1995-03-09 1995-03-09 Image forming apparatus and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH08250046A true JPH08250046A (en) 1996-09-27
JP3135813B2 JP3135813B2 (en) 2001-02-19

Family

ID=12816873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4892695A Expired - Fee Related JP3135813B2 (en) 1995-03-09 1995-03-09 Image forming apparatus and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3135813B2 (en)

Also Published As

Publication number Publication date
JP3135813B2 (en) 2001-02-19

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