JPH08242434A - Data encoder, recording and reproducing device provided with the encoder, television receiver and muse-ntsc converter - Google Patents

Abstract

PURPOSE: To allow an encoder for VBID or the like to encode data of a composite video signal without any modification without causing waveform distortion of a color burst signal and a DC step difference level. CONSTITUTION: A SYNC tip clamp circuit 1 clamps an input video signal and the clamped signal is fed to a VBID encode circuit 4. A sample-and-hold circuit 11 detects a pedestal level of the video signal subject to SYNC tip clamping. The VBID encode circuit 4 encodes VBID data by making a pedestal level detected by the sample-and-hold circuit 11 corresponding to a low level and making a voltage outputted by a reference voltage generating circuit 3 corresponding to a high level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for encoding various kinds of data superimposed in a vertical blanking period of a video signal, a recording / reproducing apparatus having the same, a television receiver, and a MUSE-NTSC converting apparatus.

[0002]

2. Description of the Related Art By utilizing a vertical blanking period of a video signal, a VBID (Vertical Blank) such as a teletext signal or a closed caption signal is used.
ing Interval Data) is transmitted.

Conventionally, a device shown in FIG. 10 has been proposed as a device for encoding such a VBID. As shown in this figure, the conventional encoding device has a pedestal clamp circuit 1 for clamping a pedestal of a video signal.
0 and VBI connected to the pedestal clamp circuit 10
For the D encode circuit 4 and the VBID encode circuit 4, a low level of encoded data (hereinafter referred to as “L level”)
High level of encoded data (hereinafter referred to as "H
A reference voltage generating circuit 3 for supplying a voltage corresponding to the "level").

The data encoding apparatus shown in FIG. 10 includes a low-pass filter 5, a sync-chip clamp circuit 1 connected to the low-pass filter 5 for clamping a sync chip of a horizontal synchronizing signal of a video signal to a predetermined level, A sync signal separation circuit 6 for separating a horizontal sync signal (hereinafter referred to as "HS") and a vertical sync signal (hereinafter referred to as "VS") from the output of the sync tip clamp circuit 1;
Based on the HS and VS, the clamp pulse supplied to the pedestal clamp circuit 10 and the VBID encoding circuit 4
The timing control circuit 7 generates a timing pulse to be supplied to the parallel / serial converter 9 described later. Here, the sync tip clamp circuit 1 is supplied with a clamp level from the reference voltage generation circuit 3.

Further, the data encoding device shown in FIG. 10 has a register 8 for holding the encoded data and a parallel data held in the register 8 as means for supplying the encoded data to the VBID encoding circuit 4. And a parallel / serial converter (hereinafter referred to as “P / S converter”) 9 for converting the data into serial data.

FIG. 11 shows an example of a circuit in the case where the data encoding device having the above-mentioned configuration is constructed by using a C-MOS circuit. Here, the portion surrounded by the alternate long and short dash line shows the C-MOS circuit. The correspondence between FIG. 11 and FIG. 10 will be described. The pedestal clamp circuit 10 of FIG. 10 has the coupling capacitor Cc1, the resistor Rped and the switch SW of FIG.
1 and a buffer amplifier connected to the switch SW1. Similarly, the VBID encoding circuit 4 is used for the switches SW2 to SW4, the reference voltage generation circuit 3 is used for the resistor ladders R1 to R5, the low pass filter 5 is used for the resistor Rf and the capacitor Cf, and the sync tip clamp circuit 1 is used for Com.
p1 and the sync signal separation circuit 6 correspond to Comp2, respectively. The timing control signal for the VBID encoding circuit 4, the register 8 and the P / S converter 9 are omitted.

Next, the operation of the data encoding apparatus configured as above will be described. The input video signal is
In the pedestal clamp circuit 10, the pedestal has a level equal to the L level of data (resistors R3 and R4 in FIG. 11).
The voltage is clamped to the potential of the connection point (1) and is sent to the VBID encoding circuit 4. In the VBID encoding circuit 4, the timing control signal from the timing control circuit 7 and the P / S
Based on the serial data from the converter 9, the switch SW2
By turning on / off the SW4 to switch between the L level and the H level from the reference voltage generation circuit 3, the level corresponding to the encoded data held in the register 8 is superimposed on the video signal and output.

Further, the input video signal has a noise component and the like removed by the low-pass filter 5, and the sync tip clamp circuit 1 clamps the sync tip at a predetermined level (potential at the connection point between the resistors R1 and R2 in FIG. 11). To be done. The output of the sync tip clamp circuit 1 is sliced into HS and VS in the sync signal separation circuit 6 and extracted, and sent to the timing control circuit 7. From the HS and VS, the timing control circuit 7 outputs the clamp pulse, VBID, which turns on SW1 of the pedestal clamp circuit 10.
A timing pulse that turns on / off the switches SW2 to SW4 of the encoding circuit 4 and a pulse that controls the timing of parallel / serial conversion of the P / S converter 9 are generated.

[0009]

FIG. 12 shows the relationship between the input video signal, the HS and the clamp pulse. As shown in this figure, since the color burst signal (CB in the figure) is inserted in the back porch of the HS, the color burst signal is clamped by the clamp pulse. As a result,
There is a problem that the color burst signal is damaged. The cause will be described with reference to FIG.

In FIG. 13, assuming that the output potential of the emitter follower for driving the video signal is Va and the clamp potential of the pedestal clamp circuit is Vb, the coupling capacitor Cc1 has a charging / discharging current ΔI expressed by the following equation.
Flows.

ΔI = ΔV / (jωCc1 + Rped) =
(Va-Vb) / (jωCc1 + Rped) [C is the capacitance of the coupling capacitor Cc1, Rped is the resistance value of the resistor Rped]

Therefore, the color burst signal is distorted in waveform according to the current. By inserting the resistor Rped, the charge / discharge current can be reduced, but the damage of the color burst signal cannot be eliminated.

Although it is conceivable to superimpose VBID on a sync tip clamped video signal instead of the pedestal clamp, if the sync length is not uniform, it is between the L level of data and the pedestal of the video signal. There is a problem that a DC step is generated.

Therefore, in order to solve such a problem, the composite signal is separated into Y / C and V is added to the Y signal.
Although it is conceivable to perform Y / C synthesis after superimposing BID, there arises a problem that a signal is deteriorated at the time of Y / C separation.

The present invention has been made in view of the above problems, and it is possible to encode data with the composite video signal as it is, and further, to encode the data without causing waveform distortion or DC step of the color burst signal. The purpose is to provide a device. In this specification, the composite video signal and the Y signal are referred to as video signals.

[0016]

In order to solve the above-mentioned problems, the present invention is an apparatus for encoding data to be superimposed on a video signal, comprising first means for clamping a sync chip of the video signal, and video. A second means for detecting the pedestal level of the signal; and a third means for superimposing the detection level of the second means on the output video signal of the first means as a predetermined level of the encoded data. It is a feature.

Further, the present invention is a recording / reproducing apparatus, a television receiver, and a MUSE-NTSC converting apparatus equipped with this data encoding apparatus.

[0018]

According to the present invention, the sync tip of the video signal is clamped by the first means, and the pedestal level of the video signal is detected by the second means. And the third
In the above means, the detection level of the second means is superimposed on the output video signal of the first means as a predetermined level of encoded data.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will now be described with reference to the drawings. [1] Data encoding device according to the embodiments of the present invention [2] Application example of the present invention device (1) Application to video cassette recorder (2) Application to television receiver (3) Application to MUSE-NTSC converter will be described in detail in this order.

[1] Data Encoding Device According to an Embodiment of the Present Invention FIG. 1 is a block diagram showing a configuration of a data encoding device according to an embodiment of the present invention. Here, the same numbers are given to the same or corresponding parts as in FIG.

As shown in the figure, the data encoding apparatus according to the embodiment of the present invention includes a sync chip clamp circuit 1 for clamping a sync chip of a video signal, and a VBID encode circuit 4 connected to the sync chip clamp circuit 1. , VBID encoding circuit 4 is provided with a reference voltage generating circuit 3 for supplying a voltage corresponding to the H level of encoded data. These circuits are also provided in the conventional example shown in FIG. 10, although there are differences in the mutual connection relationship. However, this embodiment is provided with a low-pass filter 10 and a sample hold circuit 11, which are circuits that are not present in the conventional example, and by this, the pedestal level of the video signal is detected, and the VBID encoder circuit 4 receives the data L I tried to supply it as a level.

Further, the data encoding apparatus shown in FIG. 1 has a low-pass filter 5 and a sync signal separation circuit 6 for separating HS and VS from the output of the low-pass filter 5.
And a timing for generating a sampling pulse to be supplied to the pedestal level detection circuit 2, a timing pulse to be supplied to the VBID encoding circuit 4, and a timing pulse to be supplied to a parallel / serial converter 9 which will be described later, based on these HS and VS. A control circuit 7 is provided.

Other than the circuit described above, the circuit has the same configuration and connection as the circuit described with reference to FIG. 10, and will not be described here.

FIG. 2 shows an example of a circuit in the case where the data encoding device having the above-mentioned configuration is constructed by using a C-MOS circuit.
Here, the portion surrounded by the alternate long and short dash line shows the C-MOS circuit. The correspondence between FIG. 2 and FIG. 1 will be described. The low-pass filter 10 of FIG. 1 has the capacitor Cs and the resistor Rs of FIG.
The sample and hold circuit 11 corresponds to
s, the switch SW1, and the buffer amplifier connected to the switch SW1. Similarly, the sync tip clamp circuit 1 of FIG. 1 is Comp1 of FIG. 2, the VBID encoding circuit 4 is the switches SW2 to SW4, the reference voltage generating circuit 3 is the resistor ladders R1 to R4, and the low pass filter 5 is the resistor Rf and the capacitor. The sync signal separation circuit 6 corresponds to Cf, and the sync signal separation circuit 6 corresponds to Comp2. In addition, VBI
The timing control signal for the D encode circuit 4, the register 8 and the P / S converter 9 are omitted.

Here, a supplementary description will be given of the connection relationship between the sync tip clamp circuit 1, the low pass filter 10 and the low pass filter 5. In FIG. 2, Comp1
Since the input impedance is sufficiently higher than that of the resistor Rf, the potential at the connection point between the resistor Rf and the coupling capacitor Cc is substantially equal to the potential of the terminal T1. That is, the terminal T2
It can be considered that the video signal input from the pedestal detection circuit to the pedestal detection circuit is equivalently sync tip clamped. Further, in FIG. 2, since the video signal input to Comp2 passes through the low-pass filter including the resistor Rf and the capacitor Cf and the sync-tip clamp circuit including Comp1, it is functionally equivalent to the sync-tip clamp circuit 1 of FIG. It corresponds to the low-pass filter 5.

Next, the operation of the data encoding apparatus configured as described above will be described. The input video signal is
In the sync chip clamp circuit 1, the sync chip is clamped to a predetermined level (potential at the connection point between the resistors R1 and R2 in FIG. 2) and sent to the VBID encoder circuit 4.
In the VBID encoding circuit 4, the timing control circuit 7
ON / OFF control of the switches SW2 to SW4 based on the timing control signal from the P / S converter 9 and the serial data from the P / S converter 9 so that the H level from the reference voltage generation circuit 3 and the L level from the pedestal detection circuit 2 are controlled. By switching between, the level corresponding to the encoded data held in the register 8 is superimposed on the video signal and output. That is, in the conventional example, both the H level and the L level are supplied from the reference voltage generating circuit 3, whereas in the present embodiment, the H level is supplied from the reference voltage generating circuit 3 and the L level is supplied from the pedestal detecting circuit 2. There is a difference.

On the other hand, the circuit configuration for separating the HS and VS necessary for the timing control circuit 7 to generate various timing signals is the same as in FIG.

FIG. 3 is a circuit diagram in which a portion for sampling the pedestal is extracted from FIG. 2, and FIG. 4 is a waveform diagram showing its operation. FIG. 4A shows a video signal on the input side of the switch SW1. As mentioned above, this video signal is clamped equivalently. FIG. 4B shows a video signal integrated by the resistor Rs and the capacitor Cs. FIG.
(C) is a sample pulse for closing the switch SW1. As shown in this figure, the period of the color burst signal is sampled. FIG. 4D shows a waveform sampled and held in the capacitor Cs and output from the buffer amplifier. As can be seen from the above description, the capacitor Cs has a low pass filter function and a sampled level hold function.

FIG. 5 is a circuit diagram showing the periphery of the VBID encoding circuit extracted from FIG. 2, and FIG. 6 is a timing chart showing its operation. In FIG. 6, (a) shows the relationship between the input video signal and the L level and H level of the data. Further, (b) shows the timing when the switches SW2 to SW4 are turned on (closed), and (c) shows the output video signal on which the encoded data is superimposed.

As shown in FIG. 6A, the L level of the data is equal to the pedestal level of the input video signal and is supplied from the switch SW3, and the H level of the data is supplied from the switch SW4. Then, as shown in FIG.
As shown in (c), in the horizontal scanning line for encoding VBID, the switch SW2 is turned on only in the HS and pedestal (including color burst) portions of the video signal. Then, in the other effective screen of the horizontal scanning line for encoding the VBID, SW4 and SW3 are alternately turned on to superimpose 5-bit encoded data of H-L-H-L-H. .

As described above, in this embodiment, since the pedestal clamp circuit is not used, the color burst signal in the video signal on which VBID is superimposed is not damaged.

[2] Application Example of the Device of the Present Invention FIGS. 7 to 9 are block diagrams showing application examples of the device of the present invention. These will be described in order below.

(1) Application to Video Cassette Recorder FIG. 7 shows a system in which the data encoding apparatus according to the present invention is applied to a video cassette recorder (hereinafter referred to as "VCR"). This system works as a V
A CR 21 and a VCR 22 that operates as a recorder are connected. Then, the video signal reproduced by the VCR 21 is converted to V
The CR22 is used for dubbing and rewriting the copyright information inserted in the vertical blanking period of the video signal.

Both the VCR 21 and the VCR 22 have a function of recording / reproducing a video signal including a signal in the vertical blanking period. Further, the VCR 22 includes a VBID decoder 23, a copyright information extraction / change circuit 24 connected to the VBID decoder 23, and a VBID encoder 25 connected to the copyright information extraction / change circuit 24.
The recording / reproducing unit 26 connected to the VBID encoder 25 is provided. The VBID encoder 25 is a data encoding device according to the present invention.

Next, the operation of the system will be described. The reproduced video signal output from the VCR 21 on the reproducing side is input to the VCR 22 on the recording side. The video signal input to the VCR 22 is sent to the VBID decoder 23 and the VBID encoder 25. The VBID decoder 23 inserts the VBID inserted in the vertical blanking period of the video signal.
Is decoded and sent to the copyright information extraction / change circuit 24.
The copyright information extraction / modification circuit 24 extracts the generation restriction information from the copyright information and rewrites it with new generation restriction information.
Send to the VBID encoder 25. For example, when the decoded generation restriction information is the original and the dubbing is permitted only once, the generation restriction information is set to 1. The VBID encoder 25 creates a VBID based on the rewritten copyright information, superimposes it on the video signal, and then outputs the VBID to the recording / reproducing unit 26. The recording / reproducing unit 26 uses VB
The video signal on which the ID is superimposed is recorded on the magnetic tape.

(2) Application to television receiver FIG. 8 shows the data encoding device according to the present invention as an EDTV-.
It is built in a television receiver having an II decoder and is configured to encode wide information and record it in a VCR.

The television receiver 32 has an antenna 31.
The tuner 33 connected to the tuner 33, the EDTV-II decoder 34 connected to the tuner 33, and the ED
A wide information extraction circuit 36 connected to the TV-II decoder 34, the wide information extraction circuit 36 and the EDT.
A V-II decoder 34 and a VBID encoder 35 connected to the V-II decoder 34 are provided. The output of the VBID encoder 35 is connected to the VCR 37 and is configured to record here. VBID encoder 35
Is a data encoding device according to the present invention.

Next, the operation of the system will be described. The RF signal received by the antenna 31 is sent to the tuner 33, where the signal of the desired channel is selected. The video signal of the channel selected by the tuner 33 is E
The signal is decoded by the DTV-II decoder 34 and sent to the wide information extraction circuit 36 and the VBID encoder 35. The wide information extraction circuit 36 extracts wide information such as the aspect ratio of the original image and the subtitle position and sends it to the VBID encoder. The VBID encoder 35 uses the wide information extracted by the wide information extraction circuit 36 as the VBID encoder 35.
The ID is encoded and superimposed on the video signal decoded by the EDTV-II decoder 34. The video signal output by the VBID encoder 35 is sent to the VCR 37 and recorded there. When the video signal thus recorded is reproduced and displayed on the monitor, the monitor is controlled using the wide information in the reproduced video signal.

(3) Application to MUSE-NTSC Converter FIG. 9 shows the data encoding device according to the present invention MUSE-.
It is configured to be built in an NTSC converter (hereinafter abbreviated as "MN converter"), extract wide information from information decoded by a MUSE decoder, and encode this.

As shown in FIG. 9, the MN converter 4
Reference numeral 4 is configured to input the MUSE signal received by the antenna 41 and selected by the tuner 42, or the MUSE signal output from the MUSE signal source 43 such as a video disc player for reproducing the MUSE signal.
Then, the MUSE decoder 45 and the MUSE-NTSC converter 46 connected to the MUSE decoder 45.
And a wide information extraction circuit 48, and a VB connected to the MUSE-NTSC converter 46 and the wide information extraction circuit 48.
And an ID encoder 47. The VBID encoder 47 is a data encoding device according to the present invention.

Next, the operation will be described. The MUSE signal input to the MUSE decoder 45 is decoded here and sent to the MUSE-NTSC converter 46 and the wide information extraction circuit 48. The MUSE-NTSC converter 46 is
The MUSE signal is converted into an NTSC signal and sent to the VBID encoder 47. In addition, the wide information extraction circuit 48
Wide information such as aspect ratio is extracted and sent to the VBID encoder 47. The VBID encoder 47 creates a VBID based on this wide information, and MUSE-NTS
It superimposes on the NTSC system video signal sent from the C converter 46 and outputs it.

The present invention is not limited to the above-described embodiments and application examples, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

For example, the above embodiment relates to the apparatus for encoding the VBID in which the data is superimposed in the vertical blanking period of the video signal, but the present invention is the inconspicuous portion of the effective image of the video signal, for example, the upper end portion or the like. It can also be applied when the encoded data is superimposed on the lower end.

Although the VCR shown in FIG. 7 rewrites the generation restriction information in the copyright information, the present invention is generally effective for VCRs in which information in the vertical blanking period cannot be transmitted. For example, in a VCR having a TBC in the playback system, the information of the vertical blanking period is deleted in that TBC, so the VBID is decoded and extracted before passing the playback video signal through the TBC, and passed through the TBC. The VBID is encoded and superimposed on the video signal.

Further, the present invention can be applied to an apparatus for superposing encoded data on the Y signal.

[0046]

As described above in detail, according to the present invention, the color burst signal is not damaged even when the encoded data is superimposed on the composite video signal.

Further, since the pedestal level of the composite video signal or the Y signal is set to the predetermined level of the encoded data, there is no step between the predetermined level of the data and the pedestal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data encoding device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a circuit example when the data encoding device of FIG. 1 is configured using a C-MOS circuit.

FIG. 3 is a circuit diagram showing a pedestal sample circuit extracted from FIG.

FIG. 4 is a waveform diagram showing the operation of the circuit of FIG.

FIG. 5 is a circuit diagram showing the periphery of a VBID encoding circuit extracted from FIG.

6 is a timing chart showing the operation of the circuit of FIG.

FIG. 7 is a block diagram showing an example of a VCR incorporating a data encoding device according to the present invention.

FIG. 8 is a block diagram showing an example of a television receiver including a data encoding device according to the present invention.

FIG. 9 is a block diagram showing an example of an MN converter incorporating a data encoding device according to the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional VBID encoding device.

11 is a block diagram showing a data encoding device of FIG.
It is a figure which shows the example of a circuit at the time of comprising using a circuit.

12 is an input video signal and HS in the circuit of FIG.
It is a figure which shows the relationship between a clamp pulse.

13 is a diagram showing how the color burst signal is damaged in the circuit of FIG.

[Explanation of symbols]

1 ... Sync tip clamp circuit, 2 ... Pedestal level detection circuit, 4 ... VBID encoding circuit, 22 ... VC
R, 32 ... Television receiver, 44 ... MN converter, 25, 35, 47 ... VBID encoder

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H04N 5/91 7/01

Claims (4)

[Claims] 1. An apparatus for encoding data to be superimposed on a video signal, comprising: first means for clamping a sync tip of the video signal; second means for detecting a pedestal level of the video signal; And a third means for superimposing the detection level of the second means as a predetermined level of the encoded data on the output video signal of the first means. 2. A first means for clamping a sync tip of a video signal, a second means for detecting a pedestal level of the video signal, and a second means for the output video signal of the first means. A recording / reproducing apparatus, comprising: a data encoding device comprising: a third means for superimposing a detection level of the means as a predetermined level of encoded data. 3. A first means for clamping a sync tip of a video signal, a second means for detecting a pedestal level of the video signal, and a second means for the output video signal of the first means. A television receiver comprising a data encoding device comprising: a third means for superimposing the detection level of the means as a predetermined level of encoded data. 4. A first means for clamping a sync tip of a video signal, a second means for detecting a pedestal level of the video signal, and a second means for the output video signal of the first means. And a third means for superimposing the detection level of the means as a predetermined level of the encoded data.
USE-NTSC converter.