JPH0824165B2 - Integrated circuit - Google Patents

Description

FIELD OF THE INVENTION This invention relates to the field of integrated circuit manufacturing methods. More specifically, the present invention relates to a method of making connections to circuit components formed in deeply etched trenches in integrated circuits.

2. Description of the Related Art It is widely known that metal-oxide-semiconductor (MOS) capacitors have superior performance in integrated circuits as compared with other capacitor structures. One of the advantages of MOS capacitors is the completeness of the charge when alpha particles enter the capacitor. This is especially important in dynamic random access memory (dRAM). If the charge on the storage capacitor of the dRAM cell changes, the stored data will be erroneous. This is a form of soft error and is a widely recognized problem. MOS capacitors have very high α-particles and have to add enough energy to the electrons to bring them up to the conduction band of the oxide, so soft errors are unlikely to occur.

One recently developed example of a MOS capacitor is a trench capacitor. This capacitor is formed by etching a cavity in the surface of the substrate, forming an insulator on the side surface of the trench, and filling the trench with a conductive material. One plate of the capacitor is formed by the conductive material in the trench and the other is formed by the substrate. In order to have the soft error characteristics as described above, the charge must be stored in an inner conductive layer that is electrically isolated from the substrate by an insulator. Electrical contact to the conductive layers can be made on top of the trenches by conventional integrated circuit interconnection methods. However, the upper portion of the trench can be used for other purposes, with a better method of contacting the conductive layer. One purpose of this is to form a pass transistor in the upper part of the cavity and connect it to the capacitor, thus in the trench.
Form a dRAM cell. One type of trench dRAM cell is the subject of the original application of this application.

A problem with trench cell configurations is that the capacitors and transistors cannot be accessed separately.
The ability to access separate components is important in characterizing the components during the development and manufacture of integrated circuits that use trench cells and aids in circuit design.

Also, another embodiment described herein provides an electrical connection that facilitates electrical characterization of the transistor and capacitor by allowing separate connection to the transistor or capacitor. .

Means and Actions for Solving Problems The present invention will be described in the case of manufacturing a dRAM cell, which is an important application of the present invention. The cell described herein is a one transistor / one capacitor dRAM cell structure and array in which cell pass transistors are formed on the sidewalls of the trenches in the substrate containing the cell capacitors. Word lines and bit lines intersect above this trench. By stacking the transistors on the capacitors in this way, the area of the cell on the substrate becomes extremely small, and the problem of dense packing of cells is solved.

One plate of the capacitor and the channel and source regions of the transistor are formed in the bulk sidewall of the trench, and the gate of the transistor and the other plate of the capacitor are both formed in the polysilicon in the trench, but inside the trench. Separated from each other by an oxide layer.
The signal charge is transferred to the polysilicon capacitor plate by electrically connecting the source region of the vertical pass transistor to the polysilicon capacitor plate. The embodiment described herein provides an electrical connection that allows separate access to the capacitors.

Example dRAM cells are cells of one transistor / one capacitor connected to bit lines and word lines as shown schematically in FIG. 1A and operate as follows. Capacitor 12 stores a charge that represents an information bit (eg, the absence of a stored charge represents a logic 0, a 5 between the plates of the capacitor.
The stored charge, which corresponds to a voltage of volts, represents a logic one).
An information bit is accessed (to read a bit or write a new bit) by applying a voltage to the word line 14 connected to the gate 16 and turning on the transistor 18. The turned-on transistor 18 connects the capacitor 12 to the bit line 20 for a read or write operation.
Due to leakage current and other sources of decay of the charge on the capacitor 12, a periodic refresh operation of the charge is required,
For this reason, it is named Dynamic RAM (dRAM).

FIG. 1B is a plan view showing a portion of a dRAM array having bit lines 20 and word lines 14 and cell 30 of the preferred embodiment.
Is at the intersection of the lines. Note that bit line 20 runs under word line 14. The cells penetrate into the substrate below the line, resulting in the highest density memory. Denoting the minimum feature size by f and the minimum match by R, the cell area is [2
(F + R)] ² . For example, the minimum feature size is 1.0
At micron, with a minimum allowed crossing of alignment of 0.25 micron, the cell area is about 6.25 square microns.

FIG. 2 is a cross-sectional view of a dRAM cell of a reference example according to the applicant's earlier application, which is generally indicated by 30. A cell 30 is formed in a p + type silicon substrate 32 having a p type epitaxial layer 34,
n + type polysilicon bit line 20, bit line insulating nitride
42, field oxide 36, n + polysilicon word line 14, channel 18 of transistor 18, transistor 18
Gate oxide 46, n-type diffusion region 48 forming the source of transistor 18, n + type polysilicon region 50 forming one plate of capacitor 12 (p + type substrate 32 forming the other plate and ground). ), The oxide 52 forming the insulator between the plates of the capacitor 12, the word line 14 to the capacitor plate
Isolation oxide 56 isolated from 50, n-type diffusion region 22 forming the drain of transistor 18, n-type polysilicon region 21 connecting bit line 20 to drain region 22, and source 48.
Includes an n-type polysilicon region 49 connecting the n + -type capacitor plate 50. The gate 16 of transistor 18 is simply the portion of word line 14 that crosses channel region 44 and gate oxide 46. The view of cell 30 shown in FIG. 2 corresponds to the cross section taken along the vertical line 2-2 in FIG. 1B. It is clear in FIG. 1B that the trench containing the capacitor 12 and the transistor 18 has a square cross section.

In the cell 30, one plate of the capacitor 12 is an n + type region.
50 and the n-type region 48, and the other plate is the substrate 32 and the epitaxial layer 34. However, the doping of the epitaxial layer 34 is much lower than the doping of the p + type substrate 32, so that the capacitance of the n / p type junction of the region 48 and the epitaxial layer 34 and the n + type region 50 / oxide 52 / p type epitaxial layer. Layer 34
The capacitances of both are n + type region 50 / oxide 52 / p + type substrate 3
It is much smaller than the capacitance of 2 and can be ignored. Further, as will be described later, the area of the electrode plate of the epitaxial layer 34 is smaller than that of the substrate 32, so that the capacitance associated with the epitaxial layer 34 does not become a problem. Therefore, the bulk charge stored in the capacitor 12 is
Separated from substrate 32 (and epitaxial 34) by 52. In a trench with a cross section of 1 micron x 1 micron and a depth of 6 microns, the plate area of capacitor 12 is approximately 21 square microns, where 1 micron of depth is epitaxial layer 34 and bit line 20. The p + type substrate 32 is the common ground for all cells 30 in the array.

The transistor 18 of the cell 30 is entirely in bulk silicon with the polysilicon gate, the channel region 44 is part of the p-type epitaxial layer 34, and the source region 48.
The drain region 20 (which is also part of the plate of the capacitor 12) is an n-type diffusion in the epitaxial layer 34, and a gate oxide 46 is grown on the surface of the p-type epitaxial 34 trench side to form the gate 16 Is a portion of the polysilicon word line 14. The field oxide 36 is fairly thick and minimizes the bit line 20 capacitance.

The dimensions and material properties of cell 30 will be best understood from the following description of the method of manufacture of the first preferred embodiment. Figures 3A through 3G show a series of steps in the process.

1. On a 100-oriented p + type silicon substrate 32 having a resistivity of less than 1E-2 ohm cm, a p type epitaxial layer 34 is grown with a carrier concentration of 2E16 / cm ³ and its thickness is after all heat treatments. The final p-type epitaxial layer thickness is 2 microns. Field oxide 36 (including protective oxide 37) is formed by standard processing. As an example, the SWAMI process can be used (strain relief oxide growth, low pressure chemical reaction vapor deposition (LPCVD) to deposit nitrides, nitride-oxide-silicon patterns and plasma deposition). Etch, implant boron for channel stopper, grow second strain relief oxide, deposit second nitride, digit LPCVD oxide, LPCVD oxide-nitride LP that has been plasma etched and remains from the previous etch
Wet etch the CVD oxide filament and thermally grow the field oxide to a roughly planar structure, stripping the nitride). Whichever method is used, the final thickness of field oxide 36 is 5,000Å and protective oxide 37
Is about 200Å.

Embodiments of the invention are manufactured in separate regions 34 of substrate 32. Generally, the same process steps used to manufacture cell 30 are used to make embodiments of the invention. The different processing steps are shown in Figure 3B. The structure of FIG. 3B includes field oxide 36 and protective oxide 37. An ion implantation mask 63 is formed and a pattern is defined by using a known method. Energy of about 50 kiloelectron volts and about 2x
Neighboring ions having a density of 10 ¹² ions / cm ³ are ion-implanted and driven inward to form an n-type well 61.

Returning to FIG. 3A, 2,000Å polysilicon 2
0 is deposited by LPCVD, doped to a carrier concentration of 1E20 / cm ³ , patterned and etched to form the bit line 20. Optionally, the polysilicon bit lines may be replaced with n + type diffused bit lines. next,
Deposit 10,000Å nitride 42 by LPCVD.
See Figure 3A. The layer 42 may be a layer formed of digitized nitride and oxide.

2. Define a pattern of nitride 42 to define a 1 micron square trench. The patterned nitride 42 is then used as a reactive ion etch (RIE) mask to excavate trenches to a depth of 8 microns with hydrofluoric acid. RIE from trench wall using wet acid etch
Excludes damage and contamination by. See Figure 3C. Note that the RIE also partially removes oxide 42.

The trench 62 in Figure 3D etches slightly differently. Trench 62 is designed to surround a portion of n-type well 61. A simplified side view is shown in FIG. 3D, and FIG. 3E shows n.
FIG. 6 is a plan view showing a − well 61 and a trench 62.

Oxide 52 is grown to a thickness of 200Å on the walls and bottom of the trench. The trench is then filled with n + doped polysilicon as part of a 7,000 Å deposition of n + polysilicon by LPCVD. See Figure 3F.

4. Polysilicon 50 is planarized, such as by using spin-deposited photoresist, completely on the surface and in the trench, approximately 3,000 from the epitaxial layer 34 / substrate 32 interface.
Å Etch up. See Figure 3G. As will be seen later, the location of the top of the polysilicon 50 remaining in the trench generally determines the bottom of the channel of transistor 18. Note that the nitride layer 42 is further eroded by the plasma etch, but is still at least 2,000 Å thick.

5. Etch exposed portions of oxide 52 and continue this etch until overetching 1,000 to 2,000 liters of oxide. This overetch removes the top of the oxide 52 between the epitaxial layer 34 and the polysilicon 50 to a depth of 1,000 to 2,000 Å, as shown by the arrow 53 in FIG. 3H.
Further, as shown by an arrow 39 in FIG.
Between 1,000 and 2,000 of protective oxide 37 between the and bit line 60
Å is also removed. In fact, this overetch is 1,
Form two small annular fissures with a depth of 000 to 2,000Å and a width of 200Å. One of these small crevices surrounds the top of the polysilicon 50, as shown by arrow 53, and the other small crevice extends horizontally around the boundary of bit line 20, as shown by arrow 39.

6. Deposit 500Å polysilicon 51 by LPCVD. It is thick enough to ensure that the small crevices shown by arrows 53, 39 in Figure 3H are filled. Third I
See figure.

7. Thermally grow 500Å oxide 55. This is just enough oxidation to oxidize the entire polysilicon 51, except for the portion in the small crevices shown by arrows 53, 39 in Figure 3H, which is too far from the oxidation interface. Although this oxidation amount is extremely small, the epitaxial layer 34 is also consumed.
The high temperature of the thermal oxidation of polysilicon 51 causes the dopants in n + type polysilicon 50 to diffuse into epitaxial layer 34 through the polysilicon in the small crevices shown by arrow 53. This diffusion of the dopant causes the epitaxial layer 34 to
An n-type polysilicon region 49 and an n-type region 48 are formed therein. See Figure 3J. In addition, the dopant from the bit line 20 diffuses through the polysilicon in the small crevice indicated by arrow 39 into the epitaxial layer 34 as well, so that the n-type polysilicon region 21 and the n-type region 21 within the epitaxial layer 34 are also diffused.
22 is formed. See Figure 3J. Optionally, 500Å polysilicon 51 can be removed by a timed wet chemical silicon etch from areas other than the backfilled crack areas 39, 53. This can be followed by a thermal anneal to diffuse the n + type dopant into regions 53,39. The n + type polysilicon contacts formed in regions 53 and 39 are referred to as buried lateral contacts. As can be seen in FIG. 3G, the buried lateral contacts allow the trench transistor to be connected efficiently and in a compact manner to the trench capacitor and the polysilicon bit line.

8. Remove oxide 55 by etching and remove gate oxide
Thermally grow 46 and insulating oxide 56. 25 gate oxide 46
It is grown to a thickness of 0Å, so that the oxide 56
It is somewhat thicker as it can be grown on + -doped polysilicon 50. Finally, 7,000Å n +
Formed polysilicon is deposited by LPCVD and patterned and etched to form word lines 14. See FIG. 2 for the completed cell. Gate 16 (word line 14 facing channel 44) is oxide
It controls all of the channels 44, even with a thickness of 56.
This is the n-type region 48 that forms the source of transistor 18.
However, the dopant from the polysilicon 50 diffuses through the polysilicon region 49 and thus enters the epitaxial layer 34 both horizontally and vertically from region 49. This vertical diffusion extends to the extent that gate 16 controls all channels 44.

FIG. 3K is a simplified side view of separately accessed capacitors 12. No. 3J with the same reference numerals as the parts in Fig. 2
The illustrated part operates in the same manner as the part of FIG. 2 and is manufactured during the corresponding processing steps. Contact 65 is formed using known methods to provide a contact for n-well 61. N-type well 61 provides a short circuit between source region 48 and drain region 22 of pass transistor 18. Therefore, the contact 65 is connected to the capacitor plate 50 through the polycrystalline silicon layer 2, the drain region 22, the n-type well 61 and the source region 48. Thus, the polycrystalline silicon region 50, which acts as one plate of the capacitor 12, can be accessed from the surface of the substrate and can form a contact to the substrate 32.
This acts as the other plate of the capacitor 12. This allows the capacitors 12 to be electrically characterized separately.

4A to 4K show a manufacturing method of another preferred embodiment of the present invention. As is apparent from FIGS. 4B to 4E, the transistor of the preferred embodiment is the first embodiment except that the pattern shape of the ion implantation mask 63 is changed to form the n-well 61 in a narrow region as compared with the above-described embodiments. It is manufactured by the same process as in the embodiment. It should be noted that in the drawings, the parts using the same reference numerals as in FIGS. 3A to 3K are the same.

Here, FIG. 4K shows a sectional view of the separately accessed transistor 60 of the third embodiment.

The contact 65 is formed using a method known here to
It is a contact point for the shaped well 61. n-type well 61 is a trench
Inside the cylinder formed by 62 is a short-circuit between source region 48A and drain region 22A (source region 48A and drain region 22A form the inner ring of this cylinder). Therefore, the contact 65 is connected to the drain region 48B outside the cylinder through the polycrystalline silicon region 50, the source region 48A, the n-type well 61, the drain region 22A and the polycrystalline silicon layer 20. Thus, the source region 22B, gate 14 and source region 48B of the transistor of cell 60 are accessible from the surface of the substrate. Further, the capacitors of cell 60 can be separately accessed via contacts 65 and contacts to substrate 32 (not shown). Therefore, the cell
The characteristics of 60 capacitors and transistors can be measured.

Various modifications of the present invention belong to the scope of the present invention in that the modifications, alone or in combination, do not disturb the storage of the signal charge by the capacitor or the on / off operation of the transistor. These changes include the following:

The trench cross-section can be circular, rectangular, arbitrarily convex, corrugated, or any convenient shape, such as multiple-connection (ie, including multiple trenches), and can be continuous along the vertical direction. Or stepwise or both. Similarly, the sidewalls of the trench need not be vertical, but any shape that can be processed, such as bulging, tapered and sloping sidewalls, should work to varying degrees. In fact, any easily connected trench is functionally equivalent to the preferred embodiment parallelogram. Finally, the dimensions of the trench (depth, cross-sectional area,
(Diameter, etc.) can also be changed, but in actuality, it is a trade-off of process convenience, required capacitance, substrate area, etc.
Of course, the required capacitance is related to refresh time, transistor leakage current, supply voltage, immunity to soft errors, capacitor leakage current, etc.

The insulator of the capacitor can be any convenient material such as oxides, nitrides, oxide-nitrides, oxide-nitride-oxides, and other stacked combinations can be used. Alternatively, the oxide may be thermally grown, LPCVD, dry or vapor grown, and the like. The thickness of the insulator depends on the convenience of the process,
It is a trade-off of insulator reliability, dielectric constant, breakdown voltage, etc.
It can be changed significantly. Of course, if the cell and array are made in a semiconductor material other than silicon (such as gallium arsenide, aluminum gallium arsenide gallium, cadmium mercury telluride, germanium, indium arsenide, etc.),
The insulator of the capacitor is also made of the corresponding material. Further, the distribution of doping can be changed in the capacitor formed by the reverse bias junction. The selection method depends on the convenience of the process, the size of the cell, the performance of the capacitor and the like. Similarly, amorphous silicon can be used in place of polysilicon and the etch back to form the cracks can be wet or dry (plasma).

Transistors can be formed to operate at various threshold voltages by adjusting the threshold voltage (such as by making a shallow diffusion in the channel just prior to gate oxide growth or deposition). The doping level and doping type can be changed to change the characteristics of the transistor. Note that the channel length of the transistor is approximately determined by the depth of the trench, the channel width is roughly equal to the perimeter of the trench, and that n-channel and p-channel devices require oppositely doped regions. . The transistor gate may be polysilicon, metal, silicide or the like. All of these changes affect the performance of the transistor, but in terms of other characteristics of the cell, including the required read and write times, capacitance, refresh time, etc., the transistor acts properly as a pass transistor for the cell. If you do, you can accept these changes. Furthermore,
Although the embodiment described above is for a dRAM cell access component, the present invention can be used in other devices and structures.

The embodiment of the invention described above is a structure and method for separately accessing vertically integrated components.

 The following section is further disclosed in connection with the above description.

(1) An integrated circuit having a device, at least a portion of which is below a surface of a substrate, and a doped region having a conductivity type opposite to that of the substrate and in electrical contact with at least one of the devices.

(2) The integrated circuit as described in the item (1), wherein each transistor is a transistor connected to a capacitor.

(3) The integrated circuit as described in the item (2), wherein the doped region enables the capacitor to be connected to an interconnection portion on a surface of a substrate.

(4) A plurality of devices formed in the substrate, each device being formed in a bottom portion of the void formed in the substrate and formed in an upper portion of the void. A transistor, the transistor is connected to one plate of the capacitor, and a diffusion region having a conductivity type opposite to that of the substrate surrounds a cavity in the substrate, An integrated circuit that is the interconnection between the capacitors and the surface of the substrate.

(5) The integrated circuit described in the item (4), wherein the transistor is a field effect transistor.

(6) The integrated circuit as described in the item (4), wherein the transistor is connected to an electrode plate of a capacitor insulated from the substrate.

(7) A substrate having a void formed therein and a plurality of devices formed in the substrate, each device being formed at the bottom of the void formed in the substrate The transistor comprises a capacitor and a transistor formed in the upper part of the cavity, the transistor is connected to one plate of the capacitor, and the cavity is in a horizontal plane parallel to the surface of the substrate. An integrated circuit having a diffusion region of a conductivity type opposite to the substrate that surrounds a location and provides an interconnection between a connection between the transistor and the capacitor and a surface of the substrate.

(8) A substrate having a void formed therein, an insulating layer formed on the wall of the first portion of the trench, and the remaining portion of the first portion to fill the substrate with the wall of the void. A region of conductive material in contact with the source, a source in the substrate in contact with the conductive material where the conductive material contacts the substrate, and adjacent to the void but remote from the source. A channel region is formed in the substrate between the source and the drain, the channel being the first region.
A portion of the drain that is substantially different from the second portion of the cavity and a gate that is formed adjacent to the channel region and is insulated from the channel region;
An integrated circuit having a conductivity type opposite to the substrate and a region connecting the source to the drain on a portion of the substrate surrounding the cavity in a horizontal plane parallel to the surface of the substrate. .

(9) In a method of forming a connection to a component formed below a surface of a substrate, the diffusion in the substrate having a conductivity type opposite to that of the substrate extending from the surface of the substrate to one component. A method including the step of forming a region.

(10) Having a plurality of devices formed in a substrate, each device being formed in a capacitor at the bottom of the void formed in the substrate and at an upper portion of the void. A transistor, the transistor is connected to one plate of the capacitor and has a conductivity type opposite to that of the substrate, and a diffusion region in the substrate is formed from a connection portion between the transistor and the capacitor to the substrate. An integrated circuit that is the interconnection to the surface of the.

(11) The integrated circuit as described in the item (10), wherein the transistor is a field effect transistor.

(12) The integrated circuit as described in the item (10), wherein the transistor is connected to an electrode plate of a capacitor insulated from the substrate.

(13) Having a substrate having a cavity formed therein and a plurality of devices formed in the substrate, the cavity surrounding a portion of the substrate in a plane parallel to the surface of the substrate. , Each device is composed of a capacitor formed at the bottom of the void formed in the substrate and a transistor formed at the upper portion of the void, the transistor being one plate of the capacitor. And further comprising a diffusion region of a conductivity type opposite to the substrate that serves as an interconnection between the transistor and the capacitor and a surface of the substrate. Integrated circuit in.

(14) having a substrate having a cavity formed therein, the cavity surrounding a portion of the substrate in a plane parallel to the surface of the substrate, and further comprising a wall of the first portion of the trench A formed insulating layer, a region of conductive material that fills the remainder of the first portion and contacts the substrate at the walls of the void, and within the substrate, the conductive material is the substrate. A source in contact with the conductive material, a channel region formed between the source and the drain, the channel region being adjacent to the void but remote from the source, Is formed adjacent to the drain and the drain, which is adjacent to the second portion of the void which is substantially different from the first portion, and
An integrated circuit having a gate insulated therefrom and a region connecting the source to the drain on a portion of the substrate of opposite conductivity type to the substrate and surrounded by the void.

(15) In a method of forming a connection portion for a component formed below a surface of a substrate, the diffusion in the substrate having a conductivity type opposite to that of the substrate extending from the surface of the substrate to one component. A method including the step of forming a region.

[Brief description of drawings]

1A and 1B are diagrams showing an equivalent circuit of a dRAM cell and a local shape of a memory array, and FIG. 2 is a line 2-- in FIG. 1B.
Simplified side cross-sectional views of the reference example dRAM cell taken in section 2, FIGS. 3A to 3K, are a series of process steps for manufacturing the memory cell of one embodiment of the present invention. 4K is a diagram showing the steps of a series of processes for manufacturing a memory cell according to still another embodiment of the present invention. Explanation of main symbols 61: n-well 65: contact

Claims (6)

[Claims] 1. An integrated circuit comprising a substrate having at least one trench therein, the trench surrounding a portion of the substrate, the trench being surrounded by a trench side of the substrate and a trench bottom. Further, the integrated circuit surrounds the first insulating layer that at least partially covers the trench side portion and the trench bottom portion, and the trench that cooperates with the first conductive material inside the trench, and substantially the trench. An external source region disposed along a side portion and in contact with the first conductive material at a first portion of the trench side portion, and substantially on the trench side portion of a portion of the substrate surrounded by the trench. Inner source region that is disposed along a trench and is substantially concentric with a corresponding outer source region and is in contact with the first conductive material at a second portion along the trench side portion. An external drain region surrounding the cooperating trench and substantially spaced apart from the cooperating external source region along the trench sides, the external drain region being located between the external source region and the external drain region. A first drain region defining a channel region and a second outer drain region disposed substantially along the trench side of the portion of the substrate surrounded by the trench and spaced apart from the inner source region. An inner drain region having a concentric circle shape, the inner drain region defining a second channel region between the inner source region and the inner drain region, and the drain region and the source region. Is a predetermined conductivity type, and the integrated circuit is a second conductive material, and is a region bound by the second conductive material and the substrate side portion. Second conductive material at least partially within the trench encapsulating the first conductive material and providing a gate region of the drain region and the source region by being isolated from the channel region by the first insulating layer. A second insulating layer between the first conductive material and the second conductive material; a substrate common to the trench, having the same conductivity type as the drain region and the source region, and surrounded by the trench; Is a well region in the portion of the substrate surrounding the trench and in the portion of the substrate around the trench, the first conductive material forming a capacitor with the substrate and the first insulating layer, The material is a well region accessible from a circuit connection including the drain region, the well region, the channel region, and the source region, and has access to all capacitors for testing. An integrated circuit having said well region scan are possible. 2. A third contact which is in contact with the drain region but is not in direct contact with the substrate and the first and second conductive materials.
The integrated circuit according to claim 1, further comprising a conductive material. 3. A majority carrier concentration of the substrate substantially surrounding the first conductive material is higher than a concentration of a carrier outside the well region where the external drain region and the external source region are located. The integrated circuit according to claim 1. 4. The integrated circuit of claim 1, wherein the source region contacts the first conductive material and the drain region contacts the third conductive material via a polycrystalline silicon connection. 5. The integrated circuit according to claim 1, further comprising a field oxide layer between the third conductive material and the substrate. 6. An integrated circuit comprising a substrate having at least one trench therein, the trench surrounding a portion of the substrate, the trench being surrounded by a trench side of the substrate and a substrate trench bottom. The integrated circuit further includes a first insulating layer that at least partially covers the trench side portion and the trench bottom portion, and a first conductive material inside the trench that surrounds a portion of the substrate surrounded by the trench. A polycrystalline silicon external source connection that cooperates with the trench and a trench that surrounds the cooperation trench and is disposed substantially along the trench side and includes the first conductive material and the first trench side. An external source region in contact with the site, a polycrystalline silicon internal source connection in cooperation with the trench, and the trench side of the portion of the substrate surrounded by the trench. An internal source region that is disposed substantially along with, and is substantially concentric with a corresponding external source region, and to the trench side portion via a cooperating polycrystalline silicon internal source connection portion of the trench. An external drain surrounding the associated trench with the internal source region in contact with the first conductive material at a second portion along the trench and substantially spaced from the associated external source region along the trench side. A region substantially along the trench side of a portion of the substrate surrounded by the trench, the external drain region defining a first channel region between the external source region and the external drain region. An internal drain region that is substantially concentric with the corresponding external drain region away from the internal source region. An internal drain region defining a second channel region between the region and the internal drain region, the drain region and the source region being of a predetermined conductivity type, and the integrated circuit comprising: A conductive material at least partially within the trench containing the first conductive material in a region bounded by itself and the side of the substrate, and isolated from the channel region by the first insulating layer. A second conductive material that provides a gate region of the drain region and the source region by a second insulating layer between the first conductive material and the second conductive material; and a polycrystalline silicon drain connection that cooperates with the drain. A third conductive material in contact with the drain region via a polycrystalline silicon drain connection part that cooperates with the substrate, and the substrate and the first conductive material.
And the second conductive material do not make direct contact with each other, the third conductive material, the field oxide layer between the third conductive material and the substrate, the common to the trench, and the drain region and the source region. A well region of the same conductivity type within a portion of the substrate surrounded by the trench and within a portion of the substrate around the trench, substantially surrounding the first conductive material. The majority carrier concentration is higher than the concentration in the substrate outside the well region having the external drain region and the external source region, and
A conductive material forms a capacitor with the substrate and the first insulating layer, and the first conductive material is accessible from a circuit connection including the drain region, the well region, the channel region, and the source region. An integrated circuit having a well region that is made accessible to all capacitors for testing.