JPH08241249A - Storage device - Google Patents

Abstract

PURPOSE: To reduce the power consumption of a storage device by fixing a clock to a first logical level for a certain time. CONSTITUTION: While data which is held in an output buffer 12 and consists of first to fourth words is read out or data consisting of first to fourth words is taken into an input buffer 6, OR between a clock CLK and a disable signal DIS is operated by an OR circuit 11, and the clock supplied to a cache memory 1 is fixed to the high level, and the cache memory 1 is set to the precharge state. Thus, the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory unit and a central processing unit (hereinafter referred to as CP) in, for example, a large computer.
U)) and a storage device such as a cache memory.

[0002]

2. Description of the Related Art A high-speed operating CPU requires a high-speed operating memory, but if a high-speed large-capacity memory having an access time suitable for the operation of the CPU is used, the cost is generally high. Therefore, an inexpensive low-speed memory is often used as the main large-capacity memory.
The cache memory is a small-capacity, high-speed memory interposed between the CPU and a main large-capacity memory. CP
By accessing the cache memory, U can operate at high speed regardless of the speed of the low-speed large-capacity memory which is the main memory. FIG. 2 is a block diagram showing an example of a conventional instruction cache. This instruction cache includes a cache memory 1, match determination circuits 2 and 2.
It is composed of an input AND circuit 3, a selector 4, an instruction register 5 in a CPU (not shown), and an input buffer 6. The cache fetch address (hereinafter referred to as CFA) is composed of a tag part TAG, an index part Index, and a word position part WP. This CFA is
An index portion (hereinafter referred to as Index) is used as an address for fetching an instruction from the cache and as an address ad to the cache memory 1.

The cache memory 1 is in a precharged state when the clock CLK is at a high level (hereinafter referred to as "H"), and the clock CLK is at a low level (hereinafter referred to as "L").
In this case, it has a function of reading or writing data consisting of a plurality of words in synchronization with the clock CLK. In FIG. 2, the data including the plurality of words includes the tag portion TAG, the valid bit V, and the first word (hereinafter, 1).
stWord), 2nd word (hereinafter 2ndWo)
rd), a third word (hereinafter, 3rdWord), and a fourth word (hereinafter, 4thWord). Whether or not the cache is hit is determined by the hit signal HIT. That is, the cache memory 1
Tag part TAG and CFA of the data read from
When the coincidence determination circuit 2 matches the tag portion TAG of 1 and the valid bit V is active, the AND circuit 3 activates the hit signal HIT. When the cache is hit, 1stW is set by the word position part WP of CFA.
ord, 2ndWord, 3rdWord, 4thWo
Any one of rd is selected by the selector 4, and C (not shown)
It is sent to the instruction register 5 in the PU. On the other hand, if there is a miss in the cache, the instruction read from the external main memory device is the buffer latch signal B of the input buffer 6.
It is held at the word position designated by LTn and is for one line (that is, 1stWord to 4thWord in FIG. 2).
4 words) are stored in the buffer 6, they are written in the cache memory 1 together with the tag portion TAG and the valid bit V. Write or read is instructed by the write command WE. In addition to these signals, there are generally cache purge input, valid input, etc., but they are omitted because they are not directly related to the description. FIG. 3 is a time chart for explaining the operation of FIG. 2, in which the vertical axis represents the logic level and the horizontal axis represents time.

The operation of FIG. 2 will be described below with reference to this figure. The hatched portion in FIG. 3 indicates that it is indefinite, the intersecting portion indicates that the logic level is switched, and the portion of “H” or “L” indicates that the logic level is fixed. Show. Also, "H" or "L"
The doubled portion of both indicates that the logic level can be either "H" or "L" depending on the case. At time t1, the write command WE is “L”, so the access A is cache read. Time t2
At, since the write command WE is "H", the access A is a cache write. Since the cache memory 1 is a clock synchronous type, the precharge P of the cache memory 1 is performed while the clock CLK is "H" at the times t1 and t2, and the access A of the cache memory 1 is performed while the clock CLK is "L". . In the precharge P, the electric charge is stored in the data line inside the cache memory 1, and in the access A, the stored electric charge is discharged depending on the contents of the memory cell of the cache memory 1. As described above, when the precharge P and the access A are repeated, the current flows each time. Since the instruction is executed every clock, the cache memory 1 is accessed by the address held in the CFA every clock, and the charge and discharge are performed each time.

[0005]

However, in the cache memory 1 of FIG. 2, the precharge P and the access A are repeated every one clock to perform charging / discharging, so that a current flows each time and a large amount of power is consumed. Is consumed. Therefore, when the cache memory 1 is used in a large computer or the like, the power consumption becomes enormous.

[0006]

In order to solve the above-mentioned problems, a first invention comprises a memory, which is in a precharged state when a clock is at a first logic level and the clock is at a second logic level. In this case, the following means is provided in the storage device which is in the access state when, and which is in the access state and which reads or writes data consisting of a plurality of words in synchronization with the clock. That is, first latch means for holding the data composed of the plurality of words read from the memory by one access and the data composed of the plurality of words written in the memory by one access are stored in advance. The second latch means for holding and the clock is fixed to the first logic level while the data held in the first latch means is read out or while the data is taken in by the second latch means. Clock fixing means.

[0007]

According to the first aspect of the invention, since the memory device is configured as described above, while the data consisting of the plurality of words held in the first latch means is read out, or while the plurality of words are stored in the second latch means, the plurality of words are read. While the data consisting of words is acquired,
The clock supplied to the memory is fixed to the first logic level by the clock fixing means, and the memory enters the precharged state. Since this precharge is completed in a short time, power consumption is reduced in the read or write state as compared with the conventional storage device in which the clock is supplied for each word of the plurality of words. Therefore, the above problem can be solved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of an instruction cache showing a first embodiment of the present invention, in which elements common to those in the conventional FIG. ing. The instruction cache of FIG. 1 includes a cache memory 1, a match determination circuit 2, a 2-input AND circuit 3, a selector 4, an instruction register 5 in a CPU (not shown), an input buffer 6 as a second latch means, and a clock fixing means. It is composed of an OR circuit 11 and an output buffer 12 which is a first latch means. OR circuit 11
Has a function of taking the logical sum of the clock CLK and the disable signal DIS and inputting it to the clock input section CK of the cache memory 1. The output buffer 12 is CP
It has a function of holding data read from the cache memory 1 by one access from U. This instruction cache is a direct map type instruction cache in which one line consists of 4 words. Solid line arrows in the figure indicate signal lines and their flows. The CFA is an address for fetching an instruction from the cache, and the tag part T
It consists of AG, Index, and word position part WP. I
The ndex is input to the address input unit of the cache memory 1 and is for selecting one data in the cache memory 1. The cache memory 1 is a clock synchronization type memory and operates in synchronization with the clock CK.
The OR gate 11 ORs the clock CLK with the disable signal DIS to obtain the disable signal DIS.
Is "H", it is equivalent to the case where the clock CK supplied to the cache memory 1 is maintained at "H". When the write command WE is “H”, the data is written in the cache memory 1 at the falling edge of the clock CLK.

The input data DI and the output data DO of the cache memory 1 are the tag portion TAG, the valid bit V, and the four data in one line, 1stWord, 2n.
It consists of dWord, 3rdWord, and 4thWord. The input data DataIn is supplied from a data bus connected to an external main storage device (not shown) or the like and held in the input buffer 6 when the cache misses. The input buffer 6 is a gate type latch. When the input buffer latch signal BILTn is “H”, the input data DataIn passes to the output side of the input buffer 6, and the input data DataIn is held in the input buffer 6 at the fall of the input buffer latch signal BILTn. This input buffer latch signal BILTn is
1stWord, 2ndWord, 3rdWord, 4
BILT1 to BIL corresponding to each word of thWord
T4 is provided. Of the output data DO read from the cache memory 1, TAG is the match determination circuit 2
To the CFA TAG, and if they match, a match signal eq is output. The coincidence signal eq and the valid bit V are logically ANDed by the AND circuit 3 to output the output signal S3.
When both the clock CLK and the disable signal DIS are "L", the hit signal HI is passed through the AND circuit 14.
It becomes T. That is, when the clock CLK is "L", the disable signal DIS is inactive, the match signal eq is active, and the valid bit V is active, the hit signal HIT is active. The remaining data of the output data DO, that is, 1
stWord to 4thWord are latched in the output buffer 12. The output buffer 12 is a gate type latch similar to the input buffer 6. However, there is only one output buffer latch signal BOLT, and the output buffer 12
This signal determines the overall latch timing. 1stWord and 2ndW latched in the output buffer 12
For the ord, 3rdWord, and 4thWord, one word is selected by the selector 4, and a CP not shown is shown.
It is sent to the instruction register 5 in U. It is the word position part WP in the CFA that selects one word in the output buffer 12.

FIG. 4 is a block diagram of a computer system using the instruction cache of FIG. This computer system includes an instruction cache 21, a cache control unit 22, a CPU 23, and a main storage device 24 shown in FIG.
The instruction cache 21, the cache control unit 22, and the main storage device 24 are connected via a bus B. The cache control unit 22 outputs to the instruction cache 21 an output buffer latch signal BOLT, a disable signal DIS, a write command WE, and an input buffer latch signal BILTn.
And a function of receiving the bit signal HIT. Also, the cache control unit 22
Exchanges signals with the CPU 23 and the bus B, and C
A signal such as whether or not the output data DataOut of the instruction cache 21 is valid and whether or not to branch is output to and from the PU 23. Furthermore, from the CPU 23 to the instruction cache 21
CFA is supplied to the. Further, between the cache control unit 22 and the bus B, there is a signal necessary for accessing the bus B for reading data from the main memory device 24 in the case of a cache mishit. FIG. 5 is a time chart of FIG. 1 for explaining the operation at the time of a cache hit of the instruction cache of FIG. 1, in which the vertical axis represents the logic level and the horizontal axis represents time. Less than,
The operations (1) to (5) in FIG. 1 will be described with reference to this figure.

(1) At time t1, when the disable signal DIS becomes inactive, the cache memory 1 is accessed at the falling edge of the clock CLK. Since the write command is "L", the cache memory 1 to C
A word for one line pointed to by the index of FA is read out, and at this time, the output buffer latch signal BOLT is active, so it is latched in the output buffer 12.
At this time, the clock CLK is “L”, the disable signal D
IS is inactive, match signal eq is active, and valid bit V
Indicates that the hit signal HIT is active. That is, the hit signal Hit indicates that the cache is hit. Further, the selector 4 selects 1stWord latched in the output buffer 12 based on the selection code from the word position WP and sends it to the instruction register 5. (2) At time t2, when the disable signal DIS becomes active, the cache memory 1 is precharged and the output buffer latch signal BOLT is inactive. The selection code from the word position WP of the CFA points to the next word, but since the Index is in the same line, the selector 4 sends the 2stWord latched in the output buffer 12 to the instruction register 5. (3) At time t3, the selector 4 receives 3rdWo latched in the output buffer 12 in the same manner as at time t2.
rd is sent to the instruction register 5. (4) At time t4, the selector 4 latches the 4thWo latched in the output buffer 12 in the same manner as at time t2.
rd is sent to the instruction register 5. (5) At time t5, since Index has designated a new line, the operation is similar to that at time t1.
That is, since the disable signal DIS becomes inactive, the cache memory 1 is accessed and the same operation is performed. Here, if the instruction sequence changes due to branching or the like, C
Since it can be seen that FA branches before or almost at the same time, the disable signal DIS is deactivated and data is read from the cache memory 1. Even if this reading is in the middle of a line, when the next line is reached, the selection code from the word position WP is "0b".
Since it is (b; binary), the disable signal DIS is deactivated at that time and read from the cache memory 1.

FIG. 6 is a time chart for explaining the operation of the instruction cache of FIG. 1 at the time of a cache miss, in which the vertical axis represents the logic level and the horizontal axis represents time. Hereinafter, referring to this figure, the operations (6) to (6) in FIG.
(10) will be described. (6) At time t6, when the disable signal DIS becomes inactive, the cache memory 1 is accessed, and the word for one line pointed to by CFA is read from the cache memory 1. At this time, the clock CLK is “L”, disable signal DIS is inactive, match signal e
Since q is inactive and the valid bit V is active, the hit signal HIT is inactive. That is, the hit signal Hi
From t, it can be seen that the cache has missed. (7) At time t7, since the disable signal DIS becomes active, the cache memory 1 is precharged, and the BI supplied to the 1stWord position of the input buffer 6 in the input buffer latch signal BILTn.
Only LT1 is activated, and the instruction S24a read from the main memory 24 in FIG.
It is taken into the position of rd. (8) At time t8, similarly to time t7, only BILT2 of the input buffer latch signal BILTn becomes active, and the command S24b causes 2n of the input buffer 6 to be activated.
Captured in dWord. (9) At time t9, similarly to time t7, of the input buffer latch signal BILTn, only BILT3 becomes active, and the instruction S24c causes 3r of the input buffer 6 to be activated.
Captured in dWord. (10) At time t10, in the same manner as at time t7, BIL of the input buffer latch signal BILTn is
Only T4 becomes active, and the instruction S24d becomes the input buffer 6
Of the write command W at the same time that the disable signal DIS becomes inactive
E becomes active, and the contents in the input buffer 6, TAG and the like are written in the cache memory 1.

In Buffer-I (that is, the contents in the input buffer 6) in FIG. 6, "nn" indicates that the instruction is held, and "XX" indicates that it is indefinite. That is, "nnXXXXXXX" holds only the first word, the others are undefined, "nnnnXXXX" holds the first and second words, and others are undefined, "nnnnnnX".
X ″ indicates that the first, second and third words are held and the fourth word is indefinite. As described above, in the first embodiment, the times t2, t3, t4 and t7 are set. , T8,
Since the disable signal DIS becomes active at t9, the state becomes the same as when the clock CLK is fixed at "H", and the cache memory 1 continues the precharged state. Since this precharge ends in a short time, almost no current flows even if the precharge is continued thereafter.
That is, in the present embodiment, the fact that one line consists of four words is used, and in reading, one line is used for each line.
The cache memory 1 is read out to the output buffer 12 only once, and the precharged state is maintained for other times. On the other hand, in writing, writing is performed from the input buffer 6 to the cache memory 1 only once per line, and the precharge state is maintained for the other time. In reading, the pillow word "I would like" was added,
This is because it may not be possible to sequentially fetch addresses in the increasing direction due to branching or the like. In this case, since branching is obvious, the cache memory 1 is read. In the case where one line has four words shown in the embodiment, if there is no branching or the like, the four words are accessed only once, so that the power consumption becomes 1/4 of the conventional power consumption. In FIG. 6, generally, memory (main memory) access takes a plurality of clocks, so only the last clock at time t10
Since the write command WE is activated and the contents of the input buffer 6 and the TAG and the like are written in the cache memory 1, the power consumption is reduced by that amount as compared with the conventional case.

Second Embodiment FIG. 7 is a block diagram of an instruction cache showing a second embodiment of the present invention. This instruction cache is a direct-map, store-through data cache in which one line consists of 4 words. The difference from FIG. 1 is that the data address DA is used instead of CFA, and the selector 4
The destination of the data output from the cache memory 1 is a data register (not shown) other than the instruction register in the CPU. Data address DA
Is an address for fetching data from the cache, and is composed of tag parts TAG, Index, and word position part WP. FIG. 8 is a configuration diagram of a computer system using the data cache of FIG. 7, and elements common to those in FIG. 4 are designated by common reference numerals. In this computer system, the instruction cache 21 and the cache control unit 22 in FIG.
D and the cache control unit 22D, respectively. The cache control unit 22D has a function of controlling the data cache 21D, exchanges signals with the CPU 23 and the bus B, and continuously accesses with the CPU 23 whether data of DataOut of the data cache 21D is valid or not. There is a signal such as whether or not to do. Further, between the cache control unit 22D and the bus B, in the case of a cache mishit, the data S2 from the main storage device 24 is read.
There is a signal needed to access bus B to read 4's. FIG. 9 is a time chart for explaining the operation at the time of the cache hit in FIG. 7, in which the vertical axis represents the logic level and the horizontal axis represents time. The operations (1) to (5) in FIG. 7 will be described below with reference to this figure.

(1) At time t1, the disable signal DIS becomes inactive and the cache memory 1 is accessed. Then, the data for one line indicated by the data address DA is read from the cache memory 1. At this time, the output buffer latch signal BOLT is activated and the data for one line is latched in the output buffer 12. At this time, similarly to the case of the interval t1 of the first embodiment, it can be seen from the hit signal HIT that the cache is hit. Further, the selector 4 selects 1stWord latched in the output buffer 12 based on the selection code from the word position WP and sends it to DataOut. (2) At time t2, the disable signal DIS becomes active, so that the cache memory 1 is precharged and the output buffer latch signal BOLT becomes inactive.
The selection code from the word position WP of the data address DA points to the next word, but since the Index is in the same line, the selector 4 sends the 2stWord latched in the output buffer 12 to DataOut. (3) At time t3, the selector 4 receives 3rdWo latched in the output buffer 12 in the same manner as at time t2.
Send rd to DataOut. (4) At time t4, the selector 4 latches the 4thWo latched in the output buffer 12 in the same manner as at time t2.
Send rd to DataOut. (5) At time t5, since Index has designated a new line, the operation is similar to that at time t1.
That is, since the disable signal DIS becomes inactive, the cache memory 1 is accessed and the same operation is performed. However, unlike the case of the instruction of the first embodiment, the addresses to be accessed are not continuous in most cases. However, it is effective when the CPU can instruct continuous access, such as an instruction having a continuous access to data that is known to be continuous, such as an array. When the continuous access is not made, the disable signal DIS is deactivated every time and the data is read from the cache memory 1. FIG. 10 shows FIG.
2 is a time chart for explaining the operation at the time of a cache miss hit, in which the logical level is plotted on the vertical axis and the time is plotted on the horizontal axis.

The operations (6) to (10) in FIG. 7 will be described below with reference to this figure. (6) At time t6, since the disable signal DIS becomes inactive, the cache memory 1 is accessed, and the word for one line pointed to by the data address DA is read from the cache memory 1. At this time, As in the first embodiment, it can be seen from the hit signal HIT that a miss has occurred in the cache. (7) At time t7, since the disable signal DIS becomes active, the cache memory 1 is precharged, and the BI supplied to the 1stWord position of the input buffer 6 in the input buffer latch signal BILTn.
Only LT1 is activated, and the data S24a read from the main memory 24 in FIG.
It is taken into ord. (8) At time t8, similarly to time t7, only BILT2 of the input buffer latch signal BILTn becomes active, and the data S24b becomes 2 of the input buffer 6.
Captured in ndWord. (9) At time t9, similarly to time t7, of the input buffer latch signal BILTn, only BILT3 becomes active, and the data S24c becomes 3 of the input buffer 6.
Imported into rdWord. (10) At time t10, in the same manner as at time t7, BIL of the input buffer latch signal BILTn is
Only T4 becomes active, the data S24c is taken into 4thWord of the input buffer 6, and at the same time, the disable signal DIS becomes inactive, the write command WE becomes active, and the contents of the input buffer 6 and the TAG etc. are cached. Written to memory 1. Buf in FIG.
In fer-I, as in the first embodiment, "nn"
Indicates that the instruction is held, and "XX" indicates that it is undefined.

As described above, the second embodiment has the same advantages as the first embodiment. However, unlike the case of the instruction cache, it is not effective except for special continuous access at the time of cache hit, but it is effective at the time of cache miss hit. Further, in FIG. 10, in general, a plurality of clocks are required for memory (main memory) access, so only the last clock at time t10,
The write command WE becomes "H", and the input buffer 6
Since the contents and the TAG and the like are written in the cache memory 1, the power consumption is reduced by that much as compared with the conventional case.
The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications.

(A) In FIG. 1 and FIG. 7, the input buffer 6 and the output buffer 12 are separated, but since the input buffer 6 and the output buffer 12 do not work at the same time, one buffer is used for both. You may use it for both. That will result in lower power consumption. However, in that case, a control circuit that properly uses the input buffer 6 and the output buffer 12 is required. (B) In addition to the direct map, the cache method
The same applies to n-way set associative (n ≧ 2), perfect association, etc. The same applies to other than store-through. (C) The present invention is applicable not only to cache memories but to storage devices in general.

[0019]

As described in detail above, according to the first and second inventions, the first latch means for holding the data read by one access in the storage device having the memory, Second latch means for holding data written by one access is provided, and while the data held in the first latch means is read out or while the data is taken in by the second latch means, it is stored in the memory. Since the clock to be supplied is fixed to the first logic level by the clock fixing means to put the memory in the precharged state,
The power consumption can be reduced as compared with the conventional storage device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an instruction cache showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional instruction cache.

FIG. 3 is a time chart of FIG.

4 is a block diagram of a computer system using the instruction cache of FIG.

5 is a time chart at the time of a cache hit in FIG. 1. FIG.

FIG. 6 is a time chart at the time of a cache miss hit in FIG.

FIG. 7 is a configuration diagram of a data cache showing a second embodiment of the present invention.

8 is a configuration diagram of a computer system using the data cache of FIG.

9 is a time chart at the time of a cache hit in FIG. 7. FIG.

10 is a time chart at the time of a cache miss hit in FIG. 7. FIG.

[Explanation of symbols]

1 cache memory 6 input buffer 11 OR circuit 12 output buffer 23 processing device 24 main memory device DIS disable signal

Claims (2)

[Claims] 1. A memory is provided, which is in a precharged state when the clock is at a first logic level, and the clock is at a second logic level.
In the storage device that is in the access state when the logic level is, and reads or writes data consisting of a plurality of words in the memory in the access state in synchronization with the clock, First latch means for holding the read data composed of the plurality of words; second latch means for previously holding data composed of the plurality of words written in the memory in one access; Clock fixing means for fixing the clock to the first logic level while the data held in the first latch means is read out or while the data is taken in by the second latch means. Characteristic storage device. 2. A memory comprising a precharged state when the clock from the processing unit is at the first logic level, an access state when the clock is at the second logic level, and the processing when the clock is at the access state. When the data required by the device is present in the memory, the required data is read from the memory in synchronization with the clock, and when the data required by the processing device is not present in the memory, an external main A storage device for writing the required data from the storage device to the memory in synchronization with the clock, wherein the storage device holds data consisting of a plurality of words read from the memory by one access from the processing device; 1
Latching means, second latching means for preliminarily holding data consisting of a plurality of words written in the memory with one access from the processing device, and data held in the first latching means for reading. And a clock fixing means for fixing the clock to the first logic level while the data is fetched in the second latch means.