JPH08241247A - Computer apparatus and method and circuit for its memory access - Google Patents

Abstract

PURPOSE: To provide the computer apparatus ana the method ana circuit for memory access which reduce the burden to a CPU and increase the speed of access to a memory. CONSTITUTION: The address space of a memory 12 is divided into plural blocks, and plural blocks are divided into a data area and a standby area and are managed by an MMU(memory management unit) 11; and when a request of data write to a prescribed address of the memory 12 is issued from a CPU 10, a write control circuit 13 saves contents of the block including this prescribed address into a RAM 14 and writes write data in the address corresponding to the prescribed address of saved block data. The block including the prescribed address and a block of the standby area are exchanged, and block data in the RAM 14 is copied to the block including the prescribed address of the memory 12, ana block data transferred to the standby area is erased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method and circuit for accessing a memory having a limited number of write operations, and a computer device equipped with such a memory.

[0002]

2. Description of the Related Art Generally, a storage device such as a computer device has a main storage and a secondary storage. Of these, the main memory is a device that is selected by an address signal line from an arithmetic element (CPU) or the like, and the arithmetic element can directly refer to the data by accessing the address. There are two types of main memory such as a ROM that constantly stores instructions and data, and a RAM that holds instructions and data that are read out temporarily or from secondary storage. Of these, the RAM is a volatile memory whose stored contents can be freely changed and rewritten, but the contents are lost when the power is cut off. Further, the ROM is a non-volatile memory that retains its stored contents even when the power is cut off, but it is generally impossible to rewrite the stored contents. The contents of such a ROM are set at the time of manufacture or at the time of shipment of a device incorporating a computer, and are not changed when the device is used.

On the other hand, the secondary storage is a device in which the address cannot be directly accessed and the contents can be referred to only by the address signal from the arithmetic element, and the secondary storage requires a mechanical operation. Random access takes a lot of time. Generally, the contents of this secondary storage are once transferred to the RAM and then referred to by the arithmetic element. Such a secondary storage is generally large in capacity in comparison with the above-mentioned main storage in spite of its long access time. For this reason it is used to store large amounts of data. As an example of such a secondary storage, for example, a CDROM that stores fixed information, a storage content that is often changed, and when the stored information needs to be stored even when the power is cut off, magnetic storage is required. Devices such as disks are used. Furthermore, in order to compensate the slowness of the access speed of the main memory with respect to the operation speed of the arithmetic element, a cache memory with a high access speed may be provided.

As described above, the normal computer equipment is
The memory device as described above, the input / output device and the arithmetic device (C
PU). As a storage element other than the above, for example, there is an electrically rewritable nonvolatile semiconductor memory element (for example, EEPROM).

The difference between such a memory device and a RAM is that the contents are not lost even when the power is cut off. Therefore, although it is most suitable for holding the stored data, such an electrically rewritable semiconductor memory element has a small memory capacity, a slow access speed, a complicated rewriting procedure, and a reliability. Because there was a problem with sex,
It was used only for holding a small amount of information that is not frequently rewritten.

However, with the recent development of semiconductor technology, the storage capacity, access speed, rewriting procedure of the stored contents, price, etc. of such an electrically rewritable semiconductor memory element have been greatly improved. Also, the number of rewrites (lifetime) is increasing. Therefore, such an electrically rewritable semiconductor memory device has come to be used as a secondary storage device having a relatively small capacity.

[0007]

In such an electrically rewritable semiconductor memory device, an address can be directly selected and referred to by an address signal line similarly to the main memory. Since it is not rewritable almost infinitely,
For example, it is used to store a secondary storage disk operating system. Further, when writing data to such a memory element, it is necessary to put the address to be written into the erased state and then write the data to the address. Therefore, although the access speed is overwhelmingly higher than that of the secondary memory which requires mechanical operation, the writing speed becomes extremely slower than that of the memory used as the main memory.

The present invention has been made in view of the above conventional example, and an object of the present invention is to provide a memory access method and circuit capable of reducing the load on the CPU and increasing the access speed to the memory.

It is another object of the present invention to provide a computer device, a memory access method and a circuit thereof, in which the load of a CPU required for writing is reduced in a memory which is accessed in a block unit including a designated address.

[0010]

To achieve the above object, a computer device of the present invention has the following configuration. That is, it is a computer device having a memory with a limited number of times of writing, and managing means for dividing the address space of the memory into a plurality of blocks and dividing the plurality of blocks into a data area and a spare area. Write request generating means for generating a data write request to a predetermined address of the memory, and save means for saving the contents of a block including the predetermined address of the memory in response to a write request by the write request generating means, Write means for writing write data to an address corresponding to the predetermined address of the block data saved by the save means, and replacement means for replacing a block including the predetermined address of the memory and a block of the spare area,
And a copy unit for copying the block data written by the writing unit to a block containing the predetermined address of the memory replaced by the replacement unit, and an erasing unit for erasing the block data transferred to the spare area. .

In order to achieve the above object, the memory access method of the present invention comprises the following steps. That is, it is a memory access method for accessing a memory with a limited number of writes, in which the address space of the memory is divided into a plurality of blocks, and the plurality of blocks are divided into a data area and a spare area and managed. When a data write request to a predetermined address of the memory is generated, a step of saving the contents of a block including the predetermined address, and data requested to be written to an address corresponding to the predetermined address of the saved block data And the process of writing
Exchanging a block containing the predetermined address of the memory with a block of the spare area, and copying block data containing data requested to be written to the exchanged block containing the predetermined address of the memory, Erasing the block data transferred to the spare area.

To achieve the above object, the memory access circuit of the present invention has the following configuration. That is, a memory access circuit for accessing a memory with a limited number of writes, and managing means for dividing the address space of the memory into a plurality of blocks and dividing the plurality of blocks into a data area and a spare area. When a data write request to a predetermined address of the memory is generated, a saving means for saving the contents of the block including the predetermined address, and writing to the address corresponding to the predetermined address of the block data saved by the saving means Writing means for writing the requested data, a replacement means for replacing a block including the predetermined address of the memory with a block of the spare area, and a block including the predetermined address of the memory replaced by the replacement means. Block data written by the writing means in It has a copying means for copying, and erasing means for erasing the block data transferred to the spare area.

[0013]

In the above structure, the address space of the memory is divided into a plurality of blocks, and the plurality of blocks are divided into a data area and a spare area for management. Then, when a data write request to a predetermined address of the memory occurs, the contents of the block including the predetermined address are saved,
The data requested to be written is written to an address corresponding to the predetermined address of the saved block data, and the block including the predetermined address of the memory is replaced with the block of the spare area. In this way, the block data in which the write request data is written is copied to the block including the predetermined address of the memory thus replaced, and the block data transferred to the spare area is erased.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing the structure of a memory access circuit according to the first embodiment of the present invention.

In FIG. 1, 10 is a computing element (CPU) such as a microprocessor, 11 is a memory management unit (MMU), and 12 is an electrically rewritable memory such as a flash memory.
Reference numeral 13 is a write control circuit. Reference numeral 14 is a small capacity RAM for saving data in the write block of the memory 12. The RAM 14 may be built in the memory 12 depending on the memory 12, and in that case, the RAM 14 is omitted and is shown by a dotted line. Also, the CPU 10 and the MM
The U11 and the U11 may be incorporated in the same memory device. Reference numeral 15 is a latch circuit, which connects the CPU 10 to the memory 12
The data to be written in or the data read from the memory 12 is temporarily held. 16 is also a latch circuit,
Address information for accessing the memory 12 from is temporarily stored. When the data writing from the CPU 10 to the memory 12 is the same as the data writing to the normal memory (RAM), the latch circuit 16 is not always necessary. 17 is a bidirectional tristate buffer,
The data buses of the CPU 10 and the memory 12 are connected or separated from each other.

Reference numeral 100 is an address bus output from the CPU 10, and 101 is an R / W signal for controlling the reading and writing of data, which is output from either the CPU 10 or the write control circuit 13. 102 is BUS
The Y (busy) signal causes the write control circuit 13 to send the CPU
Notify that write processing is in progress. 103 is a data bus. Reference numeral 104 denotes a control signal bus that the write control circuit 13 outputs to the memory 12.
04, it is possible to set a command input mode such as a program terminal, block erase for intelligent memory, erase suspend, and the like. 105 is HO
When the write control circuit 13 uses the data bus, the address bus and the control signal by the LD (hold) request signal,
It is used for temporarily stopping the operation of the CPU 10 and releasing the data bus, address bus, and the like. The operation of the hold signal 105 differs depending on the CPU 10. However, in this embodiment, simply activating the signal 105 stops the operation of the CPU 10 and releases the data bus, the address bus and the like. An interrupt signal 106 is a signal for causing the CPU 10 to generate an interrupt. Reference numerals 107 and 108 respectively denote a local data bus and an address bus for the write control circuit 13 to access the RAM 14. Reference numeral 109 is a control bus for outputting a signal for controlling each circuit from the write control circuit 13.

In the above configuration, when the CPU 10 issues a request to read data from the memory 12, the address information output from the CPU 10 is transferred to the MM as in the case of accessing a memory such as a normal ROM or RAM.
It is converted by U11 and input as the address of the memory 12. As a result, data is read from the specified address of the memory 12 to the data bus 103 via the latch circuit 15 and the bidirectional tristate buffer 17, and the CPU
Read by 10.

A memory map of the memory 12 is shown in FIG.

As shown in FIG. 2, the memory space of the memory 12 is a memory management unit (MMU) 11
Is managed by being divided into block sizes that can be handled. For example, in the example of FIG. 2, 128 blocks (block
0 to block 127), of which 100 blocks are used as a storage area on the system, and the remaining 28 blocks are reserved as spare areas.

As shown at 12 in FIG. 2, b is arranged at consecutive addresses in the physical memory space of the memory 12.
Each of lock0 to block127 is 1 in FIG.
As shown in FIG. 1, it is managed by each of the registers R0 to R127 of the MMU 11. Then, according to the values of these registers, these data blocks are arranged as indicated by 120 in FIG. 2 in the logical space. Here, the head address of each block is stored in each register of the MMU 11 corresponding to each block used as a storage area on the system, and a spare area including 28 blocks (for example, block122, 124 to block127, etc.). ), A specific value "N1" is set in each of the registers (R122, R124 to R127, etc.).

Now, when the CPU 10 issues a write request to the memory 12 together with the address,
The write control circuit 13 first reads data from the corresponding address of the memory 12. At this time, CPU1
In order to prevent the data output from 0 and the data read from the memory 12 from colliding with each other on the data bus 103, the write control circuit 13 sets the output of the bidirectional tri-state buffer 17 to a high impedance state. .

Here, when all the cells of the memory 12 forming the word read from the memory 12 are in the erased state,
The control signal bus 104 for the memory 12 is set to the write state, and the address from the CPU 10 is latched by the latch circuit 16.
Then, the write data is latched in the latch circuit 15. Then, either the write sequence to the memory 12 is driven or a simple write cycle is activated to write the data to the designated address of the memory 12.

If necessary, the busy signal 102 is activated and the CPU 10 is made to wait. Further, in the case of the configuration including the latch circuit 16 as shown in FIG. 1, there is no problem even if the busy signal 102 is left as it is and the operation for releasing the CPU 10 is performed, but instead, the memory 12 is used.
On the other hand, when the next data access occurs, when the previous processing is not yet finished, the busy signal 102 is activated and the CPU 10 is waited.

When the content of the word read from the address to be written in the memory 12 is in the non-erased state, the following processing is required.

(A) Block corresponding to the write address
(block n) and one block (block m) in the spare area are exchanged.

(B) The data of the corresponding block (block n) is copied to the spare area (block m). However, in the area corresponding to the write address of the spare area, the data requested to be written is stored instead of the data of the corresponding block (block n). That is, the data to be written is stored at the address corresponding to the write address of the block, and the other addresses of the block remain the data of the original block (block n).

Either of the above (a) and (b) may be executed first. Such processing is performed by software,
Although it can be realized by any hardware, this embodiment shows a configuration example in hardware. As the operation condition, since the buffer for batch writing does not exist in the memory 12, the RAM 14 is shown as being necessary.

When the data read from the corresponding address of the memory 12 is in the non-erased state, the sequencer of the write control circuit 13 is activated, and (1) the HOLD (hold) signal 1 is sent to the CPU 10.
05 is activated to put various output signals of the CPU 10 into a high impedance state, and the write control circuit 13
Secure ownership of these buses. (2) The DMA transfer is activated to transfer the data of the corresponding block (block n) of the memory 12 to the RAM 14. (3) The CPU 10 latched by the latch circuit 15
The write data instructed to be written by is transferred to the corresponding address of the RAM 14. (4) The I / O registers in which the address table of the memory management unit (MMU) 11 is stored are sequentially searched, and the register (Rn) indicating the corresponding block (block n) is searched. (5) The contents of the register (Rn) of the MMU 11 and the register (Rm) pointing to the spare area are exchanged. This operation swaps the block (block n) with the spare area (block m: this block has been erased) (block n → bloc
km, block m → block n). (6) The contents of the RAM 14 (block data in which the write data is written) are copied to the address of the corresponding block (block n), that is, the block corresponding to the original spare area. (7) Original applicable block (block
Erase m). At the same time, the data bus 103, the address bus 100, and the control signal bus 104 are released.

FIG. 3 is a flow chart for explaining the operation of the write control circuit 13 of the memory access circuit of this embodiment. This processing is started by the CPU 10 outputting a data write request to the memory 12.

When a data write request from the CPU 10 is detected, first, in step S1, the data at the memory address requested to be written is read and stored. Next, in step S2, the bidirectional tri-state buffer 17
Of the data bus 103
Write data from the CPU 10 and the memory 1 above
2 to prevent the collision with the data read. Next, in step S3, it is determined whether the address has been erased based on the data read in step S1. If it has been erased, the process proceeds to step S11, and the write data output from the CPU 10 is written to the designated address of the memory 12.

On the other hand, if the address is not erased in step S3, the process proceeds to step S4 and the hold signal 1
05 is output to stop the operation of the CPU 10, and the block data of the memory 12 corresponding to the designated write address is copied to the RAM 14 in step S5. Next, in step S6, the write data instructed by the CPU 10 is written in the corresponding address of the block data in the RAM 14. Next, in step S7, the register values of the MMU 11 are exchanged, and RA
The block transferred to M14 and the block in the spare area are exchanged. Then, in step S8, the block data in the RAM 14 is copied to the original block in the memory 12. Next, in step S9, the blocks in the spare area of the memory 12 replaced in step S7 are erased. Finally, the hold signal 105 is turned off to make the CPU 10 operable and the bidirectional tristate buffer 17 is enabled.

As described above, according to the first embodiment,
It is possible to reduce the load on the CPU and speed up data access to the memory 12.

According to the first embodiment, by using the memory management unit (MMU) 11 and performing block erasure in the background, it is possible to electrically erase in the same way as a normal memory access in software. Writing / reading to / from the non-volatile memory 12 can be performed. Moreover, this has made it possible to construct a system that can maintain system performance.

[Second Embodiment] As shown in the first embodiment described above, in the present embodiment, the corresponding write address is in the non-erased state, and block replacement and copying in the memory can be executed only by hardware. However, the circuit configuration of the write control circuit 13 becomes quite complicated.

Therefore, in the second embodiment, by implementing a part of this circuit by software, the configuration of the write control circuit 13 is simplified, and the arbitration of the control signal from each circuit and the write sequence are controlled. An example of a configuration including a circuit will be described. In the second embodiment, the function of eliminating the memory block in which the write life has occurred will be described.

Memory management unit (MMU)
In 11, the address information of the block normally placed in the system use area simply stores one of the system use area addresses, which is a different value. A value not used in the system is stored as the address information of the block for the spare area. The values can be realized by different values, but if they are all the same value, detection of hardware and software becomes easy. Further, in order to distinguish from an area which has become unusable due to the end of its life without additional hardware, the configuration indicating a constant value is simpler as shown in FIG. The example is shown below.

FIG. 4 is a block diagram showing the structure of a memory access circuit according to the second embodiment of the present invention. The parts common to those in FIG. 1 are designated by the same reference numerals, and their description will be omitted. However, the configuration of the memory write control circuit 13a is simpler than that of the first embodiment described above. The area corresponding to the RAM 14 described above is not necessary because it is provided as the RAM 120 of the CPU 10. Further, the latch circuit 15 is not a simple latch but a register capable of bidirectionally outputting the contents held therein. The latch circuit 15 simply allows data to pass under the control of the write control circuit 13a, or instead of that. , It is possible to select whether to output the latched information to the latch circuit 15. Further, the CPU 10 can read the value of the address information output to the address bus 100 via the I / O port 18.

A specific value "N1" is stored in the address register of the memory management unit MMU11 which manages the memory block which is the spare area.
This value is an address value that is not used in the system including the memory access circuit of this embodiment.

When the word at the address corresponding to the write address read from the memory 12 is in the non-erased state, the write control circuit 13a causes the CPU 10 to generate the interrupt signal 106. This causes an interrupt to the CPU 10, and in the interrupt processing routine, the CP
The U10 (1) reads the information of the I / O port 18. (2) According to the information input from the I / O port 18, the corresponding block (block n) of the memory 12 to be written
Calculate the logical address of. Also, the address register (Rn) of the corresponding block (block n) in the MMU 11 is searched. (3) The stored contents of the corresponding block (block n) are stored in the CPU 1
0 is copied to the RAM 120. At this time, the write control circuit 13a monitors the address information of the read cycle,
When the address information matches the address latched in the latch circuit 16, the write value stored in the latch circuit 15 is output instead of the read value in the memory 12. (4) The write control circuit 13a is the block (block n)
Then, the batch erasing process is performed. (5) The address register in the memory management unit MMU11 is searched and the value of that register is "N1".
Find one. If you can't find it, you'll get a system error. (6) The contents of the address register retrieved in (5) and the contents of the address register (Rn) retrieved in (2) are exchanged (replacement with the spare area). (7) Corresponding block (block n) copied to RAM 120
Is stored as the logical address of the corresponding block in the memory 12 (the block value of the spare area is copied here).
Write back to. (8) The interrupt routine is completed and normal processing is not returned.

The above processing is performed.

In the second embodiment, compared with the first embodiment described above, the write control circuit 13a requires only a write sequence creating mechanism, a block erasing executing mechanism, and a write address coincidence detecting mechanism. , A bus signal generation for data transfer becomes unnecessary, and the configuration becomes simpler.

Further, since the write processing in the above (7) is always a write to the erased cell, multiple calls in this sequence do not occur. In addition, the latch circuit 15
Since the write value latched in 1 is already stored in the RAM in (3), there is no problem even if the content of the latch circuit 15 is changed in the normal write sequence.

Generally, an electrically erasable non-volatile element has a writing life, and eventually writing becomes impossible. For this reason, it is necessary to read the write data after completion of writing in all the write sequences and determine whether the write data matches the write value by comparing with the content of the latch circuit 15. If the comparison result is different, the write control circuit 13a outputs C
The PU 10 is notified of a defective area replacement request by an interrupt.

Even in this case, the CPU 10 (1)
Processes substantially equivalent to (8) are performed. The point that is largely different from the first embodiment described above is that the processing in (6) is changed as follows.

(6 ') The value of the register is "N1", the contents of the address register indicating the defective area block are written to the address register, and the address register indicating the defective area block is set to the predetermined value. By substituting "N2", it indicates that it cannot be used.

Further, block erase is not performed on the defective area block.

FIG. 5 is a flow chart showing the interrupt processing by the CPU 10 of the memory access circuit of the second embodiment, and the control program for executing this processing is the ROM 121.
Is stored in

First, in step S21, the I / O port 18
The address latched in the latch circuit 16 is input via. Next, in step S22, the logical address of the memory 12 corresponding to the address is calculated. Then, in step S23, the register (Rn) of the MMU 11 corresponding to the address of the block (block n) corresponding to the logical address is searched. In step S24, the data of the block (block n) is copied to the RAM 120, and the write data is written in the corresponding address. Then, in step S25, the data is transferred to the RAM 120,
The corresponding block of the memory 12 is erased.

Next, in step S26, it is checked whether or not a spare area exists in the memory 12, and if there is no spare area, the process advances to step S29 to process as an error. On the other hand, when the spare area is damaged in step S26, step S27
Then, the address register (Rn) of the MMU 11 is replaced with the address register of the spare area, and the contents of the spare area are copied to the corresponding block. Then, the process proceeds to step S28, the block data of the RAM 120 is transferred to the block of the memory 12, and the process ends.

As described above, in such an electrically rewritable non-volatile memory element, the reading speed can be accessed at the same speed as that of the ROM or the like, but when writing the data, the writing should be performed. After setting the write block corresponding to the address to be erased,
I have to write. Further, in such a memory device, it is not possible to erase in arbitrary memory cell units and it is necessary to erase after writing in small block units or the entire region of the device, so information of other cells in the same block can be written. A mechanism for saving and saving is required. Therefore, the write control circuit of this embodiment arbitrates the write information to the arithmetic element (CPU) and the control signal to the electrically rewritable semiconductor memory element.

Further, the memory management unit (M
The minimum memory block size handled by the MU) does not necessarily match the minimum batch erase block size of the non-volatile memory, but the minimum size handled by the memory management unit (MMU) is 2K to the batch erase block size (K =
It is possible to manage the memory by multiplying by 0, 1, 2, 3 ,. In this case, in order to prevent wasteful erasure of blocks, a control circuit may be further provided to erase only blocks that are really necessary in the nonvolatile memory.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. The present invention can also be applied to the case where it is achieved by supplying a program for implementing the present invention to a system or an apparatus.

According to the present invention, the system speed can be improved by improving the access speed to an electrically rewritable semiconductor device such as a flash ROM.

[0055]

As described above, according to the present invention, C
It is possible to provide a computer device, a memory access method, and a circuit that can reduce the load on the PU and increase the access speed to the memory.

Further, according to the present invention, in a memory accessed in block units including a specified address, there is an effect that the load of the CPU required for writing can be reduced.

[0057]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory access circuit according to a first embodiment of the present invention.

FIG. 2 shows a physical address space of a memory according to this embodiment,
It is a figure which shows the address register in a memory management unit, and the relationship with the logical address.

FIG. 3 is a flowchart showing processing in a write control circuit of the memory access circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a memory access circuit according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing processing in a write control circuit of the memory access circuit according to the second embodiment of the present invention.

[Explanation of symbols]

 10 arithmetic element (CPU) 11 memory management unit (MMU) 12 memory 13, 13a write control circuit 14, 120 RAM 15 latch circuit 16 address latch circuit 17 bidirectional tri-state buffer 18 I / O port 100 address bus 101 R / W Signal 102 BUSY signal 103 Data bus 104 Control signal bus 105 HOLD signal 106 Interrupt signal 107 Data bus 108 Address bus 109 Control bus

Claims (11)

[Claims] 1. A memory access circuit for accessing a memory having a limited write count, wherein an address space of the memory is divided into a plurality of blocks.
Management means for managing the plurality of blocks by dividing them into a data area and a spare area; and a saving means for saving the contents of the block including the predetermined address when a data write request to the predetermined address of the memory occurs, A writing unit that writes data requested to be written to an address corresponding to the predetermined address of the block data saved by the saving unit, and a replacement unit that replaces a block including the predetermined address of the memory and a block of the spare area Copy means for copying the block data written by the writing means to a block containing the predetermined address of the memory exchanged by the exchange means, and erasing means for erasing the block data transferred to the spare area. And a memory access circuit having 2. The memory access circuit according to claim 1, wherein the blocks in the spare area are erased in advance. 3. The management means has a plurality of registers corresponding to each of the plurality of blocks, and each of the registers stores an address of each block in the memory. 1. The memory access circuit described in 1. 4. The memory access circuit according to claim 1, wherein the memory is an EEPROM. 5. A memory access method for accessing a memory having a limited number of times of writing, wherein the address space of the memory is divided into a plurality of blocks,
Managing the plurality of blocks separately into a data area and a spare area, and when a data write request to a predetermined address of the memory occurs, a step of saving the contents of the block including the predetermined address and the saved Writing data requested to be written to an address corresponding to the predetermined address of the block data; replacing a block including the predetermined address of the memory with a block of the spare area; A step of copying the block data in which the data requested to be written is written to a block including the predetermined address of the memory, and a step of erasing the block data transferred to the spare area. Memory access method. 6. The memory access method according to claim 5, wherein the blocks of the spare area are erased in advance. 7. The memory access method according to claim 5, wherein the memory is an EEPROM. 8. A computer device comprising a memory having a limited number of times of writing, wherein an address space of the memory is divided into a plurality of blocks,
Managing means for managing the plurality of blocks separately into a data area and a spare area; a write request generating means for generating a data write request to a predetermined address of the memory; and a write request by the write request generating means A save means for saving the contents of a block of the memory including the predetermined address; a write means for writing write data at an address corresponding to the predetermined address of the block data saved by the save means; Replacement means for replacing a block containing a predetermined address with a block in the spare area, and copying means for copying the block data written by the writing means to the block containing the predetermined address of the memory replaced by the replacement means Erase the block data transferred to the spare area. Computer equipment, characterized in that it comprises a deleting means for, the. 9. The computer device according to claim 8, wherein the block of the spare area is erased in advance. 10. The management means has a plurality of registers corresponding to each of the plurality of blocks, and each of the registers stores an address of each block in the memory. 8. The computer device according to item 8. 11. The computer device according to claim 8, wherein the memory is an EEPROM.