JPH08236536A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To obtain a high-performance semiconductor device, which is high in current amplification factor and the like, by a method wherein lead-out layers, which are used as base lead-out parts, are respectively formed on semiconductor regions, which are used as base regions, and the like. CONSTITUTION: A semiconductor device is provided with first conductivity type first semiconductor regions 3, which are surrounded with first and second insulating parts 4, and first conductivity type second semiconductor regions 19 on the regions of parts of the regions 3, and the device is further provided with a second conductivity type third semiconductor region 5a covering the insulating part 4 in the same layer as that of the regions 19 and a second conductivity type fourth semiconductor region 5 covering the insulating part 4 in the same layer as that of the regions 19, further it is provided with first conductivity type first lead-out layers 18 on the regions 19 and a second conductivity type second lead-out layer 9a, which is formed on the region 5a and is insulated from the layers 18 by insulators 7 and 15, and moreover, is provided with a second conductivity type third lead-out layer 9, which is formed on the region 5 and is insulated from the layers 18 by the insulators 7 and 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a lateral bipolar transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, there has been a remarkable increase in the speed of system LSIs.
There is a strong demand for not only digital systems represented by large-scale computers but also analog LSIs such as mobile radios that operate at high speed. Generally, silicon bipolar transistors are used as semiconductor elements constituting analog LSIs because of their excellent linearity and mass productivity.

By the way, when designing an analog LSI, if only npn transistors with good performance are used, the number of elements will increase significantly. In order to avoid this, a vertical npn transistor and a horizontal pnp transistor are usually made to coexist. This is because the manufacturing process of the vertical npn transistor can be used for manufacturing the horizontal pnp transistor.

FIG. 11 shows the structure of a first example of a conventional lateral pnp transistor. In this transistor, an n-type epitaxial layer 3 is grown on a p-type silicon substrate 1 on which an n-type buried layer 2 is formed, the epitaxial layer 3 is patterned, and, for example, CVD is performed in a region where the epitaxial layer 3 is removed. (Chemical Vapor Deposition)
The insulating film 4 made of, for example, SiO ₂ is buried by using the method. Next, the oxide film 25 and the nitride film 26 are sequentially deposited on the entire surface, and only the nitride film 26 is patterned into a predetermined shape.
Then, a photoresist layer (not shown) is formed, the photoresist layer is patterned, and p-type impurities are ion-implanted using the patterned photoresist layer as a mask to form the emitter region 27.
Then, after removing the photoresist layer, a photoresist layer (not shown) is formed again, the photoresist layer is patterned, and p-type impurities are ion-implanted using the patterned photoresist layer as a mask. By doing so, the collector region 28 is formed. By doing so, a part of the epitaxial layer 3, for example, a portion between the emitter region 27 and the collector region 28 becomes the base region 30. After that, an interlayer insulating film 29 is formed, a connection hole is opened in the interlayer insulating film 29, and a metal is embedded in the connection hole to form the emitter electrode 21, the base electrode 22,
The collector electrode 23 is formed to complete the transistor.

In the conventional lateral pnp transistor shown in FIG. 11, since the base is drawn out through the buried layer 2, the base region 30 is extended to the base electrode 2.
The distance to 2 becomes longer and the base resistance increases. Further, in the above structure, the width of the base region 30 cannot be reduced. Therefore, there is a problem that the application to the high-speed circuit is limited because the base resistance increases and the base width cannot be reduced. Further, among the emitter regions 27, the emitter region 27
Since the minority carriers injected from the lower surface of the above have a long distance to reach the collector, the carriers are recombined in the middle of the carrier, hardly reaching the collector region 28, and the current gain is lowered.

Next, a second conventional lateral pnp transistor is used.
The structure of the example is shown in FIG. In this pnp transistor, an n-type buried layer 32 is formed on a p-type silicon substrate 31, and an n-type epitaxial layer 33 is formed on this buried layer 32. Then, this epitaxial layer is patterned and divided into an intrinsic base region 33a and a base lead region 33b with an insulating film 35 interposed therebetween. A p-type emitter region 44 is formed substantially in the center of the intrinsic base region 33a, and a p-type collector region 40 is formed so as to surround the emitter region 44.

The current amplification factor h _fe of a bipolar transistor is generally defined as the quotient of the collector current I _c divided by the base current I _b . Here, the width of the emitter diffusion layer 44 of the transistor shown in FIG. 12 is W, the depth is L, and the depth is X.
_{If j} , the collector current I _c is 2 · X _j · (W + L)
And the base current I _b is proportional to W · L. Therefore, the current gain rate h _fe is proportional to 2 · X _j · (W + L) / (W · L), that is, 2 · X _j · (1 / L + 1 / W). Therefore, in order to increase the current amplification factor, it is advantageous to form a fine emitter diffusion region 44.

However, in the conventional lateral pnp transistor shown in FIG. 12, since it is necessary to form a contact with the metal wiring in the emitter diffusion region 43, the emitter diffusion region 44 cannot be formed small and the current amplification factor is small. There was a problem that I could not increase.

Further, in the transistor shown in FIG. 12, since the collector is only the p ⁺ diffusion layer 40, there is a problem that the concentration between the collector 40 and the base 33a is high and the Early voltage is low.

Next, the third conventional lateral pnp transistor is used.
The manufacturing process of the example will be described with reference to FIG. First, as shown in FIG. 13, an n ⁺ buried layer 52 is formed on a p-type silicon substrate 51, and the n-type concentration on the buried layer 52 is relatively low, for example, about 1 × 10 ¹⁶ cm ⁻³ epitaxial. The layer 54 is formed to a thickness of about 1.0 μm by the vapor phase growth method. Next, a trench forming technique is used to form a deep trench and a shallow trench, and then an oxide film selective filling technique is used to fill the deep trench and the shallow trench with an oxide film to form an element isolation region 55 and an inter-electrode isolation region 56, respectively. (See FIG. 13A). Subsequently, an n-type impurity is implanted into the region 54a to be the base extraction layer to form a high concentration diffusion layer n ⁺ (see FIG. 13A).

Next, an insulating film such as a thermal oxide film 57 is formed on the entire surface of the substrate.
With a thickness of about 200 Å
It is left on the collector region 54 (see FIG. 13B).
Subsequently, a mask (not shown) is formed using, for example, a photoresist using a photo-etching method, and the intrinsic base region (emitter / collector region) 54 is p-doped through the thermal oxide film 57.
By ion-implanting a type impurity, for example, boron, an emitter region 59 and a collector region 60 having a concentration of about 1 × 10 ²⁰ cm ⁻³ are formed (see FIG. 13C).

After removing the mask, an insulating film 62 made of, for example, a silicon oxide film is formed on the entire surface by the CVD method to a thickness of about 3000 angstroms. Thereafter, a predetermined heat treatment is performed to activate the impurities implanted in the emitter region 59 and the collector region 60. Next, a connection hole for the emitter region 59, the base extraction region 54a, and the collector region 60 is opened in the insulating film 62 by using a photolithography method, and subsequently, for example, Al is formed on the entire surface of the substrate.
An emitter electrode 63, a collector electrode 64, and a base electrode 65 are formed by depositing a metal layer made of (1) to fill the connection hole and patterning the same (FIG. 13).
(See (d)).

In the conventional lateral pnp transistor manufactured by the manufacturing process shown in FIG. 13, since the base region 54 has a wide area, the minority carriers injected from the emitter to the base are recombined in the base region 54 to collect. Hardly reaches the region 60 (see FIG. 14A),
There is a problem that the current amplification factor h _fe is less than half that of the vertical npn transistor. This is not only improved by a method of reducing the distance between the electrodes of the emitter and the base as shown in FIG. 14B, but even if it can be improved, it is lithographically limited to reduce the distance between the electrodes. was there.

Next, a manufacturing method of a fourth example of the conventional lateral pnp transistor and vertical npn transistor will be described with reference to FIG.
The description will be made with reference to FIG. Using techniques antimony diffusion or the like on a p-type silicon substrate 121 n ⁺ -type diffusion layer (n-type high concentration diffusion layer) 122 is formed first, n by using the epitaxial growth method on the diffusion layer 122 ^- -type A silicon layer (n-type low concentration layer) 123 is formed (FIG. 1).
5 (a)). Subsequently, a deep groove and a shallow groove for element isolation are formed on the substrate, and a p-type impurity such as boron is implanted into the bottom of the deep groove by an ion implantation method to form a p ⁺ -type diffusion layer 124 for preventing leakage between transistors. After the formation of the silicon oxide, the silicon oxide film 12 is formed in the deep groove and the shallow groove.
6 and 127 are embedded (see FIG. 15A).

A polycrystalline silicon film is deposited on the entire surface and patterned to leave it only on the emitter / collector region and the base extraction region. The polycrystalline silicon films left in the emitter / collector region and the base extraction region are polycrystalline silicon films 128a and 128b, respectively.
Becomes Subsequently, a photoresist mask (not shown) is formed by using a photo-etching method, and using this mask, an n type transistor is formed in the collector region of the npn transistor and the base lead region (n ⁻ type epitaxial layer) of the pnp transistor. Impurities are ion-implanted to form the n ⁺ type diffusion layer 12
At the same time, the polycrystalline silicon film 128b on the diffusion layer 129 is doped with n ⁺ type. In addition, after removing the photoresist mask, a photoresist mask (not shown) is formed again by photolithography.
Using this mask, BF ₂ is ion-implanted into the polycrystalline silicon film 128a on the base region of the npn transistor and the emitter / collector region of the pnp transistor to p
^{The +} type polycrystalline silicon film 128a is formed (see FIG. 15B).

Next, after removing the photoresist mask, a silicon oxide film 130 is deposited on the entire surface, and npn,
And the silicon oxide film 130 on the n ⁻ epitaxial layer 123, which will be the operating region of the pnp transistor, and p
Opening 1 by etching ⁺ type polycrystalline silicon film 128a
31 and 132 are formed and an annealing process is performed to diffuse p-type impurities from the p ⁺ -type polycrystalline silicon film 128a to the n ⁻ epitaxial layer 123, and to remove the p ⁺ -type impurity on the n ⁻ epitaxial layer 123 of the npn transistor. Impurity diffusion layer (external base diffusion layer of npn transistor) 13
3 and a p ⁺ -type impurity diffusion layer (emitter / collector diffusion layer of pnp transistor) 134 is formed on the n ⁻ epitaxial layer 123 of the pnp transistor (see FIG. 15C). After that, the opening 131 on the pnp transistor side is protected by a photoresist 135, and a p-type impurity such as BF ₂ is ion-implanted to form a base diffusion layer 136 of the npn transistor (see FIG. 15C). .

Next, after removing the photoresist 135,
A silicon nitride film 137 is deposited on the entire surface, the opening 132 on the pnp transistor side is protected again by a photoresist 138, and anisotropic etching such as RIE (Reactive Ion E) is performed.
tching), a side wall 137a made of a silicon nitride film is formed in the opening 131 on the npn transistor side, and an opening 132 on the pnp transistor side is formed.
Then, a cap layer 137b made of a silicon nitride film is formed so as to close the opening 132 (see FIG. 16A).

Next, after removing the photoresist 138,
By depositing a polycrystalline silicon film 140 on the entire surface, ion-implanting an n-type impurity such as arsenic, and performing an annealing treatment, an n ⁺ -type diffusion layer 141 serving as an emitter diffusion layer is formed inside the opening 131 on the npn transistor side. Then, the n ⁺ -type polycrystalline silicon 140 is etched, leaving only the emitter extraction electrode portion of the npn transistor (FIG. 1).
6 (b)). Then, the base of the npn transistor,
The emitter electrode 142a, the base electrode 142b, and the collect electrode 142c are formed by opening connection holes for extracting the collector electrode, the emitter, the base, and the collector electrode of the pnp transistor, and depositing and patterning so that a metal such as Al is embedded and deposited. Are formed (see FIG. 16B). The cross-sectional structure of the lateral pnp transistor thus formed is shown in FIG.

Generally, in a lateral pnp transistor, carriers are made to flow in the horizontal direction with respect to the substrate surface to perform a bipolar operation. Therefore, in the lateral pnp transistor shown in FIG. 16C, it becomes an emitter / collector diffusion layer. Of the junction between the p ⁺ diffusion layer 134 and the n ⁻ epitaxial layer 203 serving as the base layer, only the portion extremely close to the surface contributes to the effective bipolar operation. As a result, only a small part of the current flowing through the emitter-base junction flows into the collector, making it difficult to obtain a large current gain and lowering the cutoff frequency. There is a problem that it is difficult to pass an electric current. Further, there is a problem that the base width becomes larger toward the lower side of the substrate surface, and it is difficult to control the base width because the base width is determined by the lateral diffusion of the emitter and collector diffusion layers.

Therefore, if the vertical type transistor is used like the npn transistor, the above-mentioned problem is solved, but this time, the vertical type npn transistor can be manufactured simultaneously by adding a few steps to the manufacturing process. There is a problem that the advantage of the lateral pnp transistor that cannot be obtained is not obtained at all, and the number of steps is significantly increased.

Next, the fifth conventional lateral pnp transistor is used.
The manufacturing method of the example will be described with reference to FIGS. 17 and 18. First, the high-concentration n-type buried layer 92 is formed on the p-type semiconductor substrate 91, and then the low-concentration n-type epitaxial layer 93 is formed (see FIG. 17A). Then, the epitaxial layer 93 is patterned by using a photo-etching method to form a groove, and an element isolation region 94 is formed by filling the groove with an insulating material such as a silicon oxide film (see FIG. 17A).

Next, an insulating film 95 is formed in the element region (see FIG. 17b). Subsequently, a photoresist layer is formed,
A mask 98 having openings in the emitter region and the collector region by patterning this photoresist layer
And a p-type impurity such as boron B is ion-implanted to form a collector region 99 and an emitter region 107 (see FIG. 17C).

Next, after removing the mask 98, a photoresist layer is formed again, and this photoresist layer is patterned to form a mask 102 having an opening in the base lead-out region, and an n-type impurity such as phosphorus P.
Is ion-implanted to form the low concentration n-type epitaxial layer in the base extraction region as the high concentration n-type region 104 (FIG. 18).
(See (a)). Subsequently, after removing the mask 102, an insulating film 106 is deposited on the entire surface (see FIG. 18B), and the insulating film is patterned to form the emitter region 1.
07, the collector region 99, and the base lead-out region 104 are formed with connection holes, and a metal film is deposited so as to fill the connection holes and patterned to form the emitter electrode 109a, the base electrode 109b, and the collector electrode 1.
09c is formed (see FIG. 18C).

In the manufacturing method shown in FIGS. 17 and 18, since the emitter 107 and the collector 99 are manufactured in the same step, the respective impurity profiles are almost the same and the current amplification factor cannot be increased. There was a problem.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a high performance semiconductor device and a method for manufacturing the same.

[0026]

A semiconductor device according to a first aspect of the present invention is a first conductivity type first semiconductor device which is formed so as to be surrounded by first and second insulating portions in the same layer of a semiconductor substrate.
Semiconductor region, a second semiconductor region of the first conductivity type formed in a partial region on the first semiconductor region, and the first insulating portion in the same layer as the second semiconductor region. A third semiconductor region of a second conductivity type different from the first conductivity type formed so as to cover the second semiconductor region, and a third semiconductor region formed in the same layer as the second semiconductor region so as to cover the second insulating portion. 2 conductivity type 4th
Of the semiconductor region, the first conductive type first lead layer formed on the second semiconductor region, and the third lead region formed on the third semiconductor region by an insulator. A second electrically conductive type second lead layer that is electrically insulated, and a first lead layer that is formed on the fourth semiconductor region and is electrically insulated from the first lead layer by an insulator. And a third lead layer of two conductivity type.

In the semiconductor device manufacturing process according to the first aspect of the present invention, a first conductivity type first semiconductor layer is formed on a semiconductor substrate, and the first semiconductor layer is etched into a predetermined shape.
Embedding a first insulator in the region removed by etching, and forming a second semiconductor layer of a second conductivity type different from the first conductivity type on the first semiconductor layer and the first insulator. Forming a second insulator layer on the second semiconductor layer, and patterning the second insulator layer to cover the first semiconductor layer; A step of sequentially forming a conductive type third semiconductor layer and a third insulator layer, and etching the third insulator layer and the third semiconductor layer to form a layer on the second insulator layer. A step of forming an opening in the opening, a step of forming a side wall made of a fourth insulating material in the opening, and a step of removing the second insulating material at the bottom of the opening, and then performing a fourth step of the first conductivity type. Forming a semiconductor layer and thermally diffusing impurities of the first conductivity type in the fourth semiconductor layer Characterized in that it comprises a step of forming a more said second semiconductor region of a first conductivity type in the semiconductor layer.

According to a first aspect of the semiconductor device of the second invention, a first semiconductor layer of the first conductivity type formed on a semiconductor substrate and a surface of the first semiconductor layer are formed separately. A first and a second semiconductor region of a second conductivity type different from the first conductivity type and an insulating film so as to cover the first semiconductor region, and a part of the first semiconductor region is formed. A second semiconductor layer of a second conductivity type that is in direct contact with the region.

The first aspect of the manufacturing process of the semiconductor device according to the second invention is that the first semiconductor layer of the first conductivity type is formed on the surface of the semiconductor substrate, and the first semiconductor layer is formed on the first semiconductor layer. A step of forming a first insulating film and forming a connection hole with the first semiconductor layer; and a step of forming a connection hole with the first semiconductor layer, having a predetermined shape so as to fill the connection hole, and having a second conductivity type different from the first conductivity type. A second semiconductor layer, a step of forming a first semiconductor region by introducing a second conductivity type impurity into the first semiconductor layer using the second semiconductor layer as a mask, and the second semiconductor layer And diffusing impurities of the second conductivity type in the semiconductor layer into the first semiconductor layer to form a second semiconductor region.

A second aspect of the semiconductor device according to the second aspect is the semiconductor device according to the first aspect, wherein the surface of the first semiconductor layer is in contact with the second semiconductor region, A third semiconductor region of the second conductivity type, which is formed so as to be separated from the first semiconductor region and has a lower concentration than that of the second semiconductor region, is further provided.

A second aspect of the manufacturing process of the semiconductor device according to the second invention is a process of forming a first semiconductor layer of the first conductivity type on the surface of a semiconductor substrate, and a step of forming the first semiconductor layer on the first semiconductor layer. A step of forming a first insulating film and forming a connection hole with the first semiconductor layer; and a step of forming a connection hole with the first semiconductor layer, having a predetermined shape so as to fill the connection hole, and having a second conductivity type different from the first conductivity type. A step of forming a second semiconductor layer, a step of introducing a second conductivity type impurity into the first semiconductor layer using the second semiconductor layer as a mask to form a first semiconductor region, A step of forming a sidewall of the second semiconductor layer with an insulator, and using the second semiconductor layer and the sidewall as a mask, introducing a second conductivity type impurity into the first semiconductor region to form a first semiconductor region. Forming a second semiconductor region of higher concentration; Characterized in that it comprises a step of forming a third semiconductor region of the second conductivity type impurity of the body layer is diffused into the first semiconductor layer.

A semiconductor device according to a third aspect of the invention is a first semiconductor of a second conductivity type formed on the surface of a first semiconductor layer of a first conductivity type on a semiconductor substrate and having a second conductivity type different from the first conductivity type. A region, a second semiconductor layer of the first conductivity type formed on the first impurity layer, and second and second semiconductors of the second conductivity type formed separately on the surface of the second semiconductor layer. 3 semiconductor regions, and the first semiconductor region and the second semiconductor region are directly connected in the second semiconductor layer.

In the manufacturing process of the semiconductor device according to the third aspect of the present invention, the first semiconductor layer of the first conductivity type is formed on the semiconductor substrate, and the surface of the first semiconductor layer is different from the first conductivity type. Forming a second conductive type first semiconductor region, forming a first conductive type second semiconductor layer on the first semiconductor layer, and forming a second conductive layer on the surface of the second semiconductor layer. Directly connecting the first semiconductor region and the second semiconductor region with the second semiconductor layer by performing a step of separately forming the second conductivity type second and third semiconductor regions and performing heat treatment. And a step of performing.

A semiconductor device according to a fourth aspect of the present invention includes first and second semiconductor layers of a first conductivity type formed on the surface of a semiconductor substrate so as to be surrounded by an insulating film, and the first semiconductor. A third and a fourth semiconductor layer of a second conductivity type different from the first conductivity type, which are separately formed so as to be embedded so as to face each other in the vicinity of the surface of the layer, The first of the second conductivity type is formed so as to cover the boundary surface with the third semiconductor layer and is connected to the third semiconductor layer.
And a second conductive type second semiconductor region formed in the first semiconductor layer so as to cover a boundary surface between the fourth semiconductor layer and the second semiconductor type and connected to the fourth semiconductor layer. , Are provided.

Further, in the manufacturing process of the semiconductor device according to the fourth invention, a step of forming a first conductivity type epitaxial layer on a semiconductor substrate and separating the epitaxial layer into a first semiconductor layer and a second semiconductor layer by an insulating film. And a first and a second groove facing each other in the first semiconductor layer, and a first conductivity type different from the first conductivity type formed separately so as to fill the first and second grooves, respectively. Two conductivity type third and fourth
And a step of diffusing the second conductivity type impurities of the third and fourth semiconductor layers into the first semiconductor layer to form separated first and second diffusion layer regions, It is characterized by having.

A semiconductor device according to a fifth aspect of the present invention is an epitaxial layer of a first conductivity type formed on a semiconductor substrate and a second conductivity type of a second conductivity type different from the first conductivity type formed on the surface of the epitaxial layer. The emitter region and the emitter region on the surface of the epitaxial layer are separated,
And a second conductivity type collector region having a depth deeper than that of the emitter region.

[0037]

According to the semiconductor device of the first aspect of the invention configured as described above, the first lead layer serving as the base lead portion is formed on the second semiconductor region serving as the base region. If the base electrode is formed on the base lead portion, the distance between the base region and the base electrode becomes much shorter than in the conventional case, and therefore the base resistance can be greatly reduced. Further, since the width of the base region can be reduced, it can be applied to a high speed circuit. Further, since most of the lower surface of the third semiconductor region serving as the emitter region is covered with the first insulating portion, it is conventional that minority carriers are injected from the lower surface into the first semiconductor region serving as the base region. Compared with the case, the current amplification factor can be reduced and the current amplification factor can be increased.

Further, in the manufacturing process of the semiconductor device of the first invention configured as described above, the first semiconductor layer serves as the intrinsic base region, and the first conductivity type formed in the second semiconductor layer is formed. The semiconductor region serves as a base region, one of the second semiconductor layers divided by the semiconductor region serves as an emitter region, the other serves as a collector region, and the fourth semiconductor layer serves as a base lead portion. Therefore, the semiconductor device according to the first invention. As in the case of (1), the base resistance can be significantly reduced, the width of the base region can be reduced, and the current amplification factor can be increased.

According to the first aspect of the semiconductor device of the second aspect of the invention configured as described above, the first semiconductor region serving as the emitter region can be made small, so that the current amplification factor is increased. Can be large.

According to the first aspect of the semiconductor device manufacturing process of the second aspect of the invention configured as described above, the second semiconductor region serving as the emitter region can be formed small, so that the current amplification factor is increased. Can be large.

According to the second aspect of the semiconductor device of the second invention configured as described above, the emitter region and the second region are provided.
Since it is possible to reduce the semiconductor region of, the current amplification factor can be increased. Further, since the third semiconductor region which is connected to the collector region and has a lower concentration than the collector region is provided between the first semiconductor region serving as the collector region and the emitter region (second semiconductor region), the early semiconductor region is provided. The voltage can be increased.

According to the second aspect of the manufacturing process of the semiconductor device of the second invention configured as described above, the second aspect
As in the case of the second aspect of the semiconductor device of the present invention, the emitter region can be made small and a third semiconductor region having a lower concentration than the collector region connected to the collector region is formed between the emitter region and the collector region. By doing so, the Early voltage can be increased.

Further, according to the third aspect of the invention configured as described above, the second semiconductor region serving as the collector region and the first semiconductor region having the same conductivity type as the collector region are connected under the collector region. Therefore, the depth becomes deeper than that of the third semiconductor region serving as the emitter region, and most of the minority carriers emitted from the emitter reach the collector, so that the current amplification factor can be increased.

According to the fourth aspect of the invention configured as described above, the first and second emitter and collector regions are formed.
The semiconductor region (or the diffusion layer region) is formed so as to cover the third and fourth semiconductor layers formed so as to be embedded so as to face each other in the first semiconductor layer which becomes the intrinsic base region. It is possible to increase the area where the emitter region and the collector region face each other, and it is possible to increase the current amplification factor.

Since the width of the intrinsic base region can be reduced, the cutoff frequency of the transistor can be increased.

According to the semiconductor device of the fifth aspect of the invention configured as described above, since the collector region is formed deeper than the emitter region, most of the minority carriers from the emitter reach the collector region. The current amplification factor can be increased.

[0047]

FIG. 1 shows the structure of an embodiment of the semiconductor device of the first invention. The semiconductor device of this embodiment is a lateral pnp transistor, and its manufacturing method will be described with reference to FIGS. First, as shown in FIG. 2A, a high-concentration n-type buried layer 2 is formed on a p-type silicon substrate 1 using a normal diffusion technique, and an n-type epitaxial layer 3 is formed on the buried layer 2. Grow. After that, a groove is formed in the epitaxial layer 3 and an insulating film is embedded in the groove to form the element isolation region 4 (see FIG. 2A).

Then, as shown in FIG. 2B, an epitaxial silicon layer 5 is grown on the element region 3 and the insulating film 4 by the non-selective epitaxial technique. On this occasion,
For example, diborane B ₂ H ₆ at a predetermined pressure, temperature and gas flow rate.
Are mixed, and the p-type is doped while growing the epitaxial layer.

Next, as shown in FIG. 2C, an insulating film is deposited on the epitaxial layer 5 and patterned to form an etching stopper film 7 for the epitaxial layer 5 on the element region 3. The etching stopper film 7 has a large etching selection ratio as compared with the material of the sidewall 15 (see FIG. 3A) described later and the underlying epitaxial layer 5 is formed.
It is desirable to use a material that can be removed by wet etching, such as SiO ₂ or the like, so as not to damage the substrate.

Thereafter, as shown in FIG. 2D, a polycrystalline silicon film 9 having a predetermined thickness is formed by CVD (Chemical Vapor Deposition).
position) method to deposit this polycrystalline silicon film 9
Then, p-type impurities such as boron are ion-implanted. Instead of the polycrystalline silicon film 9, a polycrystalline silicon film previously doped with p-type impurities or a refractory metal such as tungsten may be deposited. Then, the oxide film 10 and the nitride film 12 having a predetermined film thickness are sequentially deposited by the CVD method.

Next, as shown in FIG. 2E, the nitride film 12 and the oxide film 1 on the element forming region are formed by using a photo-etching method.
An opening 13 is formed in each of 0 and the polycrystalline silicon film 9.
After that, as shown in FIG. 3A, an insulator made of, for example, SiN is deposited to a predetermined thickness and etched by anisotropic etching such as RIE to form a sidewall 15 in the opening 13. Subsequently, as shown in FIG. 3B, the exposed etching stopper film 7 is removed by wet etching or the like, and an opening 1 for forming a base is formed.
Form 7. Thereafter, as shown in FIG. 3C, a polycrystalline silicon film 18 is deposited on the entire surface, n-type impurities such as arsenic are ion-implanted and annealed to diffuse arsenic in the epitaxial layer 5 to form a base region. 19 is formed. At this time, the epitaxial layer 5a sandwiched between the base regions 19 becomes the emitter region 5a. The epitaxial layer 5 other than the base region 19 and the emitter region 5a becomes the collector region. The polycrystalline silicon film 18
In place of, polycrystalline silicon preliminarily doped with n-type impurities may be used. Next, by patterning the polycrystalline silicon film 18, the base extraction electrode 18
To form. After that, as shown in FIG.
0 is deposited, an opening is formed in the insulating film 20, the nitride film 12, and the insulating film 10, a metal film is deposited so as to fill the opening, and the metal film is patterned to form the emitter electrode 21 and the base electrode 22. , And collector electrode 23 are formed.

As can be seen from FIGS. 1A and 1B, the thus formed semiconductor device of the present embodiment has the base region 19 formed so as to surround the emitter region 5a and surrounds the base region. A collector region 5 is formed in the. The conductive film layer (polycrystalline silicon layer) 9a on the emitter region 5a is the emitter extraction region, and the conductive film layer 9 on the collector region 5 is the collector extraction region.
The emitter extraction region 9a and the base extraction electrode 18 are electrically insulated by the etching stopper 7 and the side wall 15, and the base extraction electrode 18 and the collector extraction region 9 are also electrically insulated by the etching stopper 7 and the side wall 15.

In this embodiment, the distance between the base region 19 and the base electrode 22 is much shorter than in the conventional case, so that the base resistance can be greatly reduced. Further, since the width of the base region 19 can be formed in a self-aligning manner, the base width can be reduced and it can be used for a high speed circuit. Further, since most of the lower surface of the emitter region 5a is covered with the insulating film 4, the minority carriers are less likely to be injected into the base region from this lower surface, and the current amplification factor is increased as compared with the conventional case. be able to.

As described above, the semiconductor device of this embodiment has high performance.

Next, the manufacturing process of the first embodiment of the semiconductor device according to the second invention will be described with reference to FIG. First, FIG.
As shown in (a), by adding an n-type impurity such as antimony by thermal diffusion or the like onto the silicon substrate 31 containing about 4 × 10 ¹⁴ cm ⁻³ of p-type impurity such as boron B. The n ⁺ diffusion layer 32 is formed. Subsequently, an epitaxial layer 33 containing n-type impurities is formed on the entire surface. Next, after forming deep and shallow grooves by anisotropic etching, these grooves are filled with an insulator such as an oxide film,
Element isolation regions 34 and 35 are formed respectively. afterwards,
An oxide film 36 is formed on the element region by using a thermal oxidation method or the like (see FIG. 4A).

Next, after selectively removing the oxide film 36 in a portion which will become a base contact with the emitter region in the future, a polycrystalline silicon film is grown on the entire surface by using a low pressure CVD method or the like, and this polycrystalline silicon film is formed. By patterning into a predetermined shape, a polycrystalline silicon film 37 for extracting an emitter and a polycrystalline silicon film 38 for extracting a base are formed as shown in FIG. 4B. Then, using a photo-etching method or the like, a mask of a photoresist (not shown) is formed,
For example, an n-type impurity such as phosphorus is injected into the epitaxial layer 33 through the polycrystalline silicon film 38 to form a base extraction n ⁺ compensation diffusion layer 41, then the mask is removed, and the photoetching method is used again. A photoresist mask (not shown) is formed, and a p-type impurity such as boron is injected into the polycrystalline silicon film 37 and the epitaxial layer 33 around it to form a collector region 42 (FIG. 4C). ), The mask is removed.

Next, an insulating film 43 such as an oxide film is formed on the entire surface by CVD.
Method, and then heat treatment is performed to diffuse p-type impurities from the polysilicon film 37 into the epitaxial layer 33 to form an emitter region 44 (FIG. 4).
(See (d)). Subsequently, the insulating film 43 is patterned to form the emitter contact hole 45, the collector contact hole 46, and the base contact hole 47 (see FIG. 4D). At this time, the oxide film 36 on the bottoms of the collector contact hole 46 and the base contact hole 47 is also removed at the same time (see FIG. 4D). Thereafter, for example, a film made of a wiring material with a metal is formed on the contact holes 45, 4
6, 47 are deposited so as to be embedded, and patterned to form an emitter electrode, a collector electrode, and a base electrode (not shown) to form a transistor.

In the semiconductor device of the first embodiment, since the emitter region 44 is formed by diffusion through the fine contact surface between the emitter-leading polycrystalline silicon film 37 and the epitaxial layer 33, the conventional structure is used. In comparison, it can be formed finer and the current amplification factor can be increased.

Next, a manufacturing process of the second embodiment of the semiconductor device according to the second invention will be described with reference to FIG. In the semiconductor device of this embodiment, the same steps as those in the first embodiment are performed up to the step shown in FIG. After that, FIG.
As shown in (a), a photoresist mask (not shown) is formed by using a photo-etching method or the like.
A base extraction n ⁺ compensation diffusion layer 41 is formed by injecting a type impurity into the epitaxial layer 33 through the polycrystalline silicon film 38, and after removing the mask, the photoresist mask (see FIG. (Not shown), and a p-type impurity such as boron B is added to the polycrystalline silicon film 37 and the epitaxial layer 33 around it.
To form ap ⁻ collector layer 40.
Subsequently, a sidewall 39 made of, for example, a nitride film is formed on the side portion of the polycrystalline silicon film 37 (see FIG. 5B).

Next, a photoresist mask (not shown) is formed by using a photo-etching method or the like, and a p-type impurity such as phosphorus is ion-implanted into the polycrystalline silicon film 37 and the epitaxial layer 33 around it. To form the p ⁺ collector 42 (see FIG. 5C). Next, after removing the mask, an insulating film 43 such as an oxide film is formed on the entire surface by CV.
After growing using the D method, heat treatment is performed to diffuse p-type impurities from the polysilicon film 37 into the epitaxial layer 33 to form the emitter region 44 (FIG. 5).
(See (d)). Subsequently, the insulating film 43 is patterned to form the emitter contact hole 45, the collector contact hole 46, and the base contact hole 47 (see FIG. 5D). After that, for example, a metal film is deposited so as to fill the contact holes 45, 46, 47, and patterned to form an emitter electrode, a collector electrode, and a base electrode (not shown) to form a transistor.

In the semiconductor device of the second embodiment, the emitter region 44 can be finely formed as in the first embodiment, so that the current amplification factor can be increased. Furthermore, since the p ⁻ collector layer 40 is formed between the base region 33 and the collector region (p ⁺ layer) 42, the Early voltage can be increased.

Next, a manufacturing process of an embodiment of the semiconductor device according to the third invention will be described with reference to FIG. First, an n-type high-concentration impurity layer 52 is formed on a p-type silicon substrate 51, and then a p-type with a relatively high concentration of, for example, about 1 × 10 ¹⁸ cm ⁻³ is formed in a region directly below a collector region 60 described later. Diffusion layer 5
3 is formed in the n-type impurity layer 52 (see FIG. 6A).

Next, on the entire surface, a relatively low concentration of n-type, for example, 1 ×
An epitaxial layer 54 having a thickness of about 10 ¹⁶ cm ^{−3 is} formed to a thickness of about 1.0 μm by vapor phase epitaxy, and the epitaxial layer 54, the n-type impurity layer 52, and the silicon substrate 51 are etched by using a trench technique. To form a deep groove, and the epitaxial layer 54 is etched to form a shallow groove (see FIG. 6B). Then, by burying an oxide film (SiO ₂ ) or the like in these deep trenches and shallow trenches, element isolation regions 55 and inter-electrode isolation regions 56 for isolating the emitter / collector region 54 and the base contact region 54a are formed (FIG. 6). (See (b)). Then, a thermal oxide film 57 is grown on the entire surface of the substrate to a thickness of about 200 angstroms and patterned to remain on the emitter / collector region 54 (see FIG. 6B).

Next, a photoresist mask (not shown) is formed by photolithography, and p-type impurities such as boron are ion-implanted into the emitter / collector region 54 through the thermal oxide film 57 using this mask. By doing 1
An emitter region 59 and a collector region 60 having a concentration of about × 10 ²⁰ cm ^-3 are formed and the mask is removed (FIG. 6).
(C)).

Subsequently, an insulating film 62 made of, for example, SiO _{2 is} deposited on the entire surface by the CVD method to a thickness of about 3000 angstroms, and heat treatment is performed to activate the p-type impurities ion-implanted in the emitter region 59 and the collector region 60. (See FIG. 6D). The diffusion layer 53 and the collector region 60 are connected by this heat treatment. Next, after forming a connection hole to the emitter region 59, the collector region 60, and the base lead-out region 54a in the insulating film 62, a metal film made of, for example, Al is deposited so as to fill the connection hole and patterned. The emitter electrode 63, the collector electrode 64, and the base electrode 65 are formed, thereby forming a bipolar transistor (see FIG. 6D).

In the semiconductor device of this embodiment, the diffusion layer region 53 of the same conductivity type as that of the collector region 60 is formed immediately below the collector region 60 so as to be electrically connected to the collector region 60. The minority carriers escaping from the emitter region 59 to the lower base region 54 in the conventional case can be captured by the diffusion layer 53,
The current amplification factor is greatly improved.

Next, a manufacturing process of an embodiment of the semiconductor device according to the fourth invention will be described with reference to FIGS. 7 and 8. In this manufacturing process, only the operation region of the lateral pnp transistor will be described, but the unillustrated portions such as the vertical npn transistor are formed in the same manner as in the conventional example described with reference to FIGS. 15 and 16.

First, as shown in FIG. 7A, an n ⁺ diffusion layer 72 is formed on a p-type silicon substrate 71 by a technique such as antimony diffusion, and an n ⁻ epitaxial layer is formed thereon by an epitaxial growth method. 73 is formed. Then, deep trenches and shallow trenches for element isolation are formed on this substrate, and p-type impurities such as boron are implanted into the bottom of the deep trenches by an ion implantation method to form ap ⁺ diffusion layer 74 serving as a channel stopper. The element isolation region 75 and the inter-electrode isolation region 76 are formed by filling the trench and the shallow trench with, for example, SiO ₂ (see FIG. 7A).

Next, a photoresist mask 78 is formed by using a photo-etching method, and the mask 78 is guided to the portions of the n ⁻ epitaxial layer 73 which will be the operating region of the pnp transistor, which will be the emitter region and the collector region. Then, anisotropic etching such as RIE is performed to form the groove 79 (see FIG. 7B). At this time, since the selection ratio of silicon to the insulating film 76 by anisotropic etching can be made sufficiently large, the opening of the mask does not need to be aligned with the groove 79, and the insulating film 76 in the periphery of the operating region can be formed. There is no problem even if it spreads over the area. Therefore, the groove 7
The width of 9 can be made smaller than the resolution of the photo-etching method (see FIG. 7B).

Next, after removing the photoresist mask 78, a polycrystalline silicon film 80 serving as an emitter / collector extraction electrode is deposited on the entire surface (see FIG. 7C). The polycrystalline silicon film 80 serves as a base lead electrode in a vertical npn transistor. At this time, FIG. 7 (c)
In the above, the trench 79 is completely filled with the polycrystalline silicon film 80, but it is not always necessary to fill it.

Subsequently, the polycrystalline silicon film 80 is patterned by using a photo-etching method and anisotropic etching, and then an n-type impurity such as phosphorus is ion-implanted into the base extraction region (the collector extraction region in the vertical npn transistor). To form the n ⁻ type epitaxial layer into the n ⁺ type diffusion layer 82, and at the same time, the polycrystalline silicon film 8 on these regions is formed.
0b is doped to the n ⁺ type (see FIG. 8A). Then, a p-type impurity such as boron is introduced into the portion of the polycrystalline silicon film 80a for extracting the emitter and the collector (the base in the vertical npn transistor) by an ion implantation method to form p ⁺ -type polycrystalline silicon. Next, for example, a silicon oxide film 83 is deposited on the entire surface as an insulating film, a photoresist mask 84 is formed, and the silicon oxide film 83 and the polycrystalline silicon film 80a are etched using anisotropic etching to surround the base formation region. The opening 86 is formed in a shape (see FIG. 8A).

Next, after removing the photoresist mask 84, annealing is performed to diffuse from the p ⁺ polycrystalline silicon film 80a to the n ⁻ epitaxial layer 73, thereby forming an emitter / collector diffusion layer (in a vertical npn transistor, an external base). A p ⁺ type impurity diffusion layer 87 to be a diffusion layer) is formed (see FIG. 8B). Then, the internal base diffusion layer (not shown) of the vertical npn transistor is selectively p-typed.
After forming a type impurity such as BF ₂ by ion implantation, a silicon nitride film 88 is deposited on the entire surface and a photoresist mask (not shown) is formed.
By performing anisotropic etching such as IE, the nitride film 88 is left only in the opening 86 and its periphery, thereby forming a silicon nitride film cap 88 that closes the opening 86 of the lateral pnp transistor (see FIG. 8B). ). At this time, a nitride film side wall (not shown) is formed in the opening formed on the transistor region of the vertical npn transistor.

Next, after removing the photoresist mask, a polycrystalline silicon film is deposited on the entire surface, and arsenic is ion-implanted and annealed to form an emitter diffusion layer (not shown) of the vertical npn transistor. The polycrystalline silicon is removed by etching, leaving only the emitter electrode of the vertical npn transistor.

Finally, the silicon oxide film 83 is patterned to form the base of the vertical npn transistor, the contact opening (not shown) for taking out the collector electrode, and the horizontal p.
After forming a collector opening for taking out the emitter, base, and collector electrodes of the np transistor, a metal film is deposited so as to fill the opening and patterned to form an emitter electrode 89a, a base electrode 89b, and a collector electrode 89c ( FIG. 8C).

As described above, according to the semiconductor device of the present embodiment, the groove 79 is formed in the epitaxial layer 73 at the portion connected to the emitter and collector extraction polycrystalline silicon of the lateral transistor, and the inside of this groove is formed. Since the emitter / collector diffusion layer 87 is formed by diffusion from the buried emitter / collector polycrystalline silicon film 80a, it is possible to increase the area where the emitter diffusion layer and the collector diffusion layer face each other, and thus the current gain is increased. Can be increased. Further, since the base width can be controlled by the interval between the trenches 79 in the emitter / collector diffusion layer forming region, the base width can be easily thinned and the cutoff frequency of the transistor can be increased. In addition, since the effective emitter area can be controlled by the depth of the groove 79 in the emitter / collector diffusion layer forming region, the operating current of the transistor can be easily controlled, and the circuit design can be facilitated. There is also.

Next, a manufacturing process of an embodiment of the semiconductor device according to the fifth invention will be described with reference to FIGS. 9 and 10.
First, a high-concentration n-type region 92 is formed on a p-type semiconductor substrate 91, and a low-concentration n-type epitaxial layer 93 is formed thereon (see FIG. 9A). Subsequently, a groove for element isolation is formed in the semiconductor substrate, and an element isolation 94 is formed by filling the groove with an insulating film made of, for example, SiO ₂ (see FIG. 9A).

Next, an insulating film 95 is deposited in the element region, and an opening 96 for defining an emitter region is further formed in this insulating film.
Then, a polycrystalline silicon film 97 is deposited on the entire surface and is connected to the n-type epitaxial layer 93 to be an emitter region through the opening 96 (see FIG. 9B).

Next, a photoresist mask 98 is formed to cover the emitter region and the intrinsic base region, and the polycrystalline silicon film 97 is etched by anisotropic etching using this mask 98. Then, a p-type impurity such as boron is ion-implanted with high energy to deeply form the collector region 99 (see FIG. 9C).

Subsequently, after removing the mask 98, a photoresist mask 100 having openings in the polycrystalline silicon film 97 and the collector region 99 is formed, and a p-type impurity such as boron is formed in the polycrystalline silicon film 97 and the collector region 99. Is ion-implanted with low energy (see FIG. 9D).

Next, after removing the photoresist mask 100, a photoresist mask 102 having an opening in the base lead-out portion is formed, and an n-type impurity such as phosphorus is ion-implanted to lower the concentration n of the base lead-out portion.
The type epitaxial layer 93 is made into a high concentration n ⁺ type region 104 (see FIG. 10A).

Subsequently, after removing the photoresist mask 102, an insulating film 106 is deposited on the entire surface and heat treatment is performed to diffuse the p-type impurities in the polycrystalline silicon film 97 into the epitaxial layer 93, and the emitter region 107. Are shallowly formed (see FIG. 10B).

Next, the emitter region 10 is formed on the insulating film 106.
7, collector region 99, and base lead portion 104
After forming an opening for making contact with the metal film, a metal film is deposited so as to fill the opening and patterned to form an emitter electrode 109a and a base electrode 109.
b, the collector electrode 109e is formed to complete the lateral transistor.

As described above, the emitter region 107
Since the collector region 99 can be formed to be shallow and the collector region 99 can be formed to be deep, the ratio of the minority carriers injected from the emitter region 107 to the collector region 99 increases and the current amplification factor is improved as compared with the conventional case. Can be made.

Although the lateral pnp transistor has been described in each of the first to fifth embodiments,
It goes without saying that the invention can also be applied to a lateral npn transistor.

[0085]

As described above, according to the present invention, a high performance semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a structure of an embodiment of a semiconductor device of the first invention.

FIG. 2 is a process sectional view showing a manufacturing process of an embodiment of the semiconductor device of the first invention.

FIG. 3 is a process sectional view showing a manufacturing process of an embodiment of the semiconductor device of the first invention.

FIG. 4 is a process cross-sectional view showing the manufacturing process of the first embodiment of the semiconductor device according to the second invention.

FIG. 5 is a process sectional view showing a manufacturing process of a second embodiment of a semiconductor device according to the second invention.

FIG. 6 is a process sectional view showing a manufacturing process of an embodiment of a semiconductor device according to the third invention.

FIG. 7 is a process cross-sectional view showing a manufacturing process of an embodiment of a semiconductor device according to the fourth invention.

FIG. 8 is a process sectional view showing a manufacturing process of an embodiment of a semiconductor device according to the fourth invention.

FIG. 9 is a process sectional view showing a manufacturing process of an embodiment of a semiconductor device according to the fifth invention.

FIG. 10 is a process sectional view showing a manufacturing process of an embodiment of a semiconductor device according to the fifth invention.

FIG. 11 is a configuration diagram showing a structure of a first example of a conventional semiconductor device.

FIG. 12 is a perspective view showing the structure of a second example of the conventional semiconductor device.

FIG. 13 is a sectional view of a manufacturing process of a third example of the conventional semiconductor device.

FIG. 14 is a manufacturing process sectional view of a third example of the conventional semiconductor device.

FIG. 15 is a sectional view of the manufacturing process of the fourth example of the conventional semiconductor device.

FIG. 16 is a sectional view of a manufacturing process of a fourth example of a conventional semiconductor device.

FIG. 17 is a manufacturing step sectional view of a fifth example of the conventional semiconductor device.

FIG. 18 is a sectional view of a manufacturing process of a fifth example of the conventional semiconductor device.

[Explanation of symbols]

1 p-type semiconductor substrate 2 n-type buried layer 3 n-type epitaxial layer 4 element isolation region 5 epitaxial silicon layer 5a emitter region 7 etching stopper film 9 polycrystalline silicon film 9a emitter extraction region 10 oxide film 12 nitride film 13 opening 15 sidewall 17 Opening 18 Polycrystalline silicon film (base extraction electrode) 19 Base region 20 Insulating film 21 Emitter electrode 22 Base electrode 23 Collector electrode 25 Oxide film 26 Nitride film 27 Emitter region 28 Collector region 29 Interlayer insulating film 30 Base region 31 P-type silicon Substrate 32 n ⁺ Diffusion layer 33 Epitaxial layer 33a Intrinsic base region 33b Base extraction region 34, 35 Element isolation region 36 Oxide film 37 Emitter extraction polycrystalline silicon film 38 Base extraction polycrystalline silicon film 39 side Wall 40 Collector region 41 n ⁺ Compensation diffusion layer (base extraction region) 42 Collector region 43 Insulating film 44 Emitter region 45 Emitter contact hole 46 Collector contact hole 47 Base contact hole 51 p-type silicon substrate 52 n-type high concentration impurity layer 53 p Type diffusion layer 54 n-type epitaxial layer 54a base contact region 55 element isolation region 56 inter-electrode isolation region 57 thermal oxide film 59 emitter region 60 collector region 62 insulating film 63 emitter electrode 64 collector electrode 65 base electrode 71 p-type silicon substrate 72 n ⁺ diffusion layer 73 n ^- polysilicon film 80b n-type epitaxial layer 74 p ⁺ diffusion layer 75 the element isolation region 76 between electrodes isolation region 78 photoresist mask 79 groove 80 polycrystalline silicon film 80a p-type impurity-doped Pure object-doped polycrystalline silicon film 83 a silicon oxide film 84 a photoresist mask 86 opening 87 p ⁺ -type diffusion layer 88 a nitride film (cap) 89a emitter electrode 89b base electrode 91 p-type semiconductor substrate 92 heavily doped n-type region 93 n-type epitaxial layer 94 element isolation region 95 insulating film 96 opening 97 polycrystalline silicon film 98 photoresist mask 99 collector region 100 photoresist mask 102 photoresist mask 104 high-concentration n-type region 106 insulating film 107 emitter region 109a Emitter electrode 109b Base electrode 109c Collector electrode 121 p-type silicon substrate 122 n ⁺ type diffusion layer 123 n ⁻ type silicon layer (epitaxial layer) 124 Leak prevention p ⁺ type diffusion layer 126, 127 Silicon oxide film (element isolation region) Area) 128a polycrystalline silicon film (p ⁺ ) 128b polycrystalline silicon film (n ⁺ ) 129 n ⁺ type diffusion layer 130 silicon oxide film 131, 132 opening 133 p ⁺ type impurity diffusion layer 134 p ⁺ type impurity diffusion layer 135 photo Resist 136 Base diffusion layer 137a Side wall (silicon nitride film) 137b Cap layer (silicon nitride film) 140 Polycrystalline silicon film 142a Emitter electrode 142b Base electrode 142c Collector electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiko Iinuma 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center (72) Inventor Chihiro Yoshino Sachi-ku, Kawasaki-shi, Kanagawa Komukai Toshiba Town 1 Stock Company Toshiba Research and Development Center

Claims (13)

[Claims] 1. A first semiconductor region of a first conductivity type formed so as to be surrounded by first and second insulating portions in the same layer of a semiconductor substrate, and a part of the first semiconductor region. Formed in the area of
A second semiconductor region of a conductivity type and a third semiconductor region of a second conductivity type different from the first conductivity type and formed in the same layer as the second semiconductor region so as to cover the first insulating portion. A fourth semiconductor region of the second conductivity type formed so as to cover the second insulating portion in the same layer as the second semiconductor region, and a fourth semiconductor region formed on the second semiconductor region. 1 of conductivity type
And a second lead layer of the second conductivity type formed on the third semiconductor region and electrically insulated from the first lead layer by an insulator. And a third lead-out layer of the second conductivity type which is formed on the semiconductor region and is electrically insulated from the first lead-out layer by an insulator. 2. A first semiconductor layer of a first conductivity type is formed on a semiconductor substrate, the first semiconductor layer is etched into a predetermined shape, and the region removed by etching is filled with a first insulator. A step of forming a second semiconductor layer of a second conductivity type different from the first conductivity type on the first semiconductor layer and the first insulator, and a step of forming a second semiconductor layer on the second semiconductor layer. Forming a second insulating layer, and patterning the second insulating layer so as to cover the first semiconductor layer; and a second conductive type third semiconductor layer and a third insulating layer. Sequentially forming a layer of the second insulating layer, a step of etching the third insulating layer and the third semiconductor layer to form an opening on the second insulating layer, and a fourth step in the opening. Forming a side wall made of an insulating material, and removing the second insulating material at the bottom of the opening. And then forming a fourth semiconductor layer of the first conductivity type, and thermally diffusing the impurities of the first conductivity type in the fourth semiconductor layer to form the first conductivity type in the second semiconductor layer. And a step of forming a semiconductor region of the mold, and a method of manufacturing a semiconductor device. 3. A first conductivity type first semiconductor layer formed on a semiconductor substrate, and a second conductivity type formed separately on the surface of the first semiconductor layer and different from the first conductivity type. Type first and second semiconductor regions, and a second conductivity type that is formed so as to cover the first semiconductor region via an insulating film and has a portion in direct contact with the first semiconductor region. A second semiconductor layer, and a semiconductor device comprising: 4. A step of forming a first semiconductor layer of a first conductivity type on a surface of a semiconductor substrate, a first insulating film being formed on the first semiconductor layer, and the first semiconductor layer And a step of forming a second semiconductor layer of a second conductivity type different from the first conductivity type, the second semiconductor layer having a predetermined shape so as to fill the connection hole. Forming a first semiconductor region by introducing a second conductivity type impurity into the first semiconductor layer by using the mask as a mask; and a second conductivity type impurity of the second semiconductor layer in the first semiconductor layer. And a step of forming a second semiconductor region by diffusing into a layer, and a method of manufacturing a semiconductor device. 5. A surface of the first semiconductor layer is formed so as to be in contact with the second semiconductor region but separate from the first semiconductor region. 4. The semiconductor device according to claim 3, further comprising a low-concentration second-conductivity-type third semiconductor region. 6. A step of forming a first semiconductor layer of a first conductivity type on the surface of a semiconductor substrate, a first insulating film being formed on the first semiconductor layer, and the first semiconductor layer And a step of forming a second semiconductor layer of a second conductivity type different from the first conductivity type, the second semiconductor layer having a predetermined shape so as to fill the connection hole. Forming a first semiconductor region by introducing a second conductivity type impurity into the first semiconductor layer using the mask as a mask; forming a sidewall of the second semiconductor layer with an insulator; Forming a second semiconductor region having a concentration higher than that of the first semiconductor region by introducing a second conductivity type impurity into the first semiconductor region using the second semiconductor layer and the sidewall as a mask; Diffusion of second conductivity type impurities of the second semiconductor layer into the first semiconductor layer The method of manufacturing a semiconductor device which was characterized in that it comprises a step of forming a third semiconductor region. 7. A first semiconductor region of a second conductivity type different from the first conductivity type, which is formed on the surface of a first semiconductor layer of the first conductivity type on a semiconductor substrate, and the first impurity. A second semiconductor layer of the first conductivity type formed on the layer, and a second semiconductor layer formed separately on the surface of the second semiconductor layer.
A semiconductor device having conductive second and third semiconductor regions, wherein the first semiconductor region and the second semiconductor region are directly connected in the second semiconductor layer. . 8. A first semiconductor layer of a first conductivity type is formed on a semiconductor substrate, and a first semiconductor region of a second conductivity type different from the first conductivity type is formed on the surface of the first semiconductor layer. A step of forming, a step of forming a second semiconductor layer of a first conductivity type on the first semiconductor layer, and a second and a third semiconductor of a second conductivity type on the surface of the second semiconductor layer. A step of forming the regions separately and a heat treatment are performed to form the first semiconductor region and the second semiconductor region.
And a step of directly connecting the semiconductor region of the second semiconductor layer with the second semiconductor layer. 9. A first conductivity type first and a second conductivity type formed on a surface of a semiconductor substrate so as to be respectively surrounded by an insulating film.
And a second semiconductor layer different from the first conductivity type, which is separately formed so as to be embedded so as to face and face the vicinity of the surface of the first semiconductor layer.
Second conductivity that is formed in the first semiconductor layer so as to cover the boundary surface between the third and fourth semiconductor layers of conductivity type and is connected to the third semiconductor layer. A second semiconductor region of the second conductivity type, which is formed in the first semiconductor layer so as to cover an interface between the first semiconductor region and the fourth semiconductor layer and is connected to the fourth semiconductor layer. A semiconductor device comprising: 10. The semiconductor device according to claim 9, wherein the second semiconductor layer has a first conductivity type impurity concentration higher than that of the first semiconductor layer. 11. A step of forming an epitaxial layer of a first conductivity type on a semiconductor substrate and separating the epitaxial layer into first and second semiconductor layers by an insulating film, and facing the first semiconductor layer. Third and fourth semiconductors of a second conductivity type different from the first conductivity type formed by forming the first and second trenches, which are formed so as to fill the first and second trenches, respectively. A layer, and a step of diffusing the second conductivity type impurities of the third and fourth semiconductor layers into the first semiconductor layer to form separated first and second diffusion layer regions. A method of manufacturing a semiconductor device, comprising: 12. An epitaxial layer of a first conductivity type formed on a semiconductor substrate, an emitter region of a second conductivity type different from the first conductivity type formed on the surface of the epitaxial layer, and an epitaxial layer of the epitaxial layer. A semiconductor device, comprising: a second conductivity type collector region formed on the surface of the collector region, the collector region being separated from the emitter region and being deeper than the emitter region. 13. The method according to claim 4, wherein the first semiconductor region is formed deeper than the second semiconductor region.