JPH08235138A - Computer system - Google Patents

Abstract

PURPOSE: To improve the throughput of memory access processing from a vector processor and actualize efficient synchronous processing of common data as to the computer system which uses a buffer storage to transfer the common data between processors. CONSTITUTION: The computer system having the communication buffer storage which holds a copy of data including operand data of a specific scalar instruction shared by scalar processors 10 and 11 in block units is so constituted that the communication buffer storage holds even a copy of data including input/ output control information shared by the scalar processors 10 and 11 and an input/output processor 12 in block units. Further, whether or not each block in the communication buffer storage includes a copy of the operand data of the specific scalar instruction is discriminated and a block which does not include the copy is preferentially replaced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main memory shared multiprocessor computer system, and more particularly to a computer system in which shared data is exchanged via a buffer memory provided in a memory controller.

[0002]

2. Description of the Related Art Conventionally, in a so-called multiprocessor computer system having a plurality of processors, an instruction for synchronizing the contents of shared data shared between the processors performing parallel processing (multitasking). As such, the following instruction is used. TS (Test-and-Set) instruction Sets a designated bit in shared data to "1" and generates a condition code based on the set value of the bit immediately before the setting. CS (Compare-and-Swap) command and CDS (Compare
-Double-and-Swap) instruction Read shared data, check whether the set value has been updated by another processor, and if it has not been updated, perform update processing as it is, but if it has been updated Transfers the current set value to the register for holding the previous set value.

The above-mentioned instructions are used when updating the contents of shared data shared between the processors. Therefore, before executing the above instruction, the contents of the shared data held in the individual buffer storages are the same among all processors, and the contents of the shared data held in the main storage are the same. It is essential that they also match (that is, all shared data is synchronized between processors). Therefore, in general, the above-mentioned instruction is treated as a special type of instruction (hereinafter, referred to as “specific scalar instruction”), and the access accompanying the specific scalar instruction is forcibly performed to the main memory (that is,
A processing procedure such as buffer storage is not used) is adopted to avoid complication of the processing for realizing the synchronous control. However, on the other hand, in the case of a computer system having a vector processor, in order not to reduce the throughput of the memory access processing from the vector processor,
It is desirable to prevent memory access processing to the main memory from occurring as much as possible. Therefore, in a computer system having a vector processor and a plurality of scalar processors for processing the specific scalar instruction, synchronization between a plurality of scalar processors is provided by providing a dedicated buffer memory (communication buffer memory) for holding shared data. There has been proposed one that makes the processing efficient ("Computer system" described in Japanese Patent Laid-Open No. 3-228169).

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the "computer system" described in Japanese Patent No. 28169, the shared data to be stored in the communication buffer storage is limited to the operand data of the specific scalar instruction, but other than this, for example, asynchronously with the scalar processor. There is shared data shared by a plurality of processors, such as scalar processor and input / output control information accessed from the input / output processor for the purpose of performing input / output. The input / output control information mentioned here includes the following. I / O device control word Holds start / interrupt control information for I / O device. I / O activation queue block This holds the I / O device control word related to the I / O device for which the activation request is issued in a queue structure. After the enqueue operation by the scalar processor, the dequeue operation by the I / O processor is performed. I / O interrupt queue block Holds I / O device control words related to I / O devices for which interrupt factors are suspended in a queue structure. After the enqueue operation by the I / O processor, the dequeue operation by the scalar processor is performed. All of these input / output control information are secured in a continuous area (hereinafter referred to as "specific area") on the main memory designated at the time of power-on reset of the system. And
The access processing to these I / O control information is performed not only when there is a start / interrupt request to the I / O device, but also when there is no particular request, to check the existence of the I / O device start request. As a result, the access process from the I / O processor to the I / O activation queue block is performed every predetermined monitoring time.

Therefore, in a computer system having a vector processor, the frequency of occurrence of memory access requests for input / output control information from the scalar processor and the input / output processor is suppressed in order not to reduce the throughput of the memory access processing from the vector processor. Therefore, it is necessary to consider so that the memory access processing to the main memory does not occur as much as possible. In particular, in the computer system that employs the method of reading the vector data required by the vector processor in parallel from the main memory and loading all the vector element data into the vector register, the input / output control information described above is used. Even if the reading of the vector element data is delayed by only one element due to the passing of the data, the load time of the vector data to the vector register will increase and the throughput of the memory access processing from the vector processor will drop significantly. was there.

Therefore, it is possible to improve the throughput of the memory access process from the vector processor by utilizing the communication buffer storage for the transfer of the input / output control information. In this case, however, a new problem as described below will occur. Occurs.

Conventionally, when trying to store new block data in the communication buffer storage,
If there is no free block in the block group (collection of multiple blocks) selected as the storage destination candidate,
Only one old block is selected from the block group, and "replacement" (replacement processing) is performed to overwrite the block with new block data. In this case, a block including a copy of operand data of a specific scalar instruction as shared data (hereinafter abbreviated as “type 1 block”) and a data of input / output control information not including a copy of operand data of a specific scalar instruction If a block including a copy of the first type block (hereinafter abbreviated as “second type block”) is treated as a replacement processing candidate, all the first type blocks are swept out from the communication buffer storage and the second type There is a problem in that it may be occupied only by blocks, making it difficult to realize an efficient purpose of efficiently synchronizing shared data between a plurality of processors provided with a communication buffer storage.

Therefore, an object of the present invention is to solve the above-mentioned problems and utilize the communication buffer storage also at the time of passing the input / output control information shared by the scalar processor and the input / output processor. In addition to improving the throughput of the access processing, the communication buffer storage is occupied only by the block that does not include the copy of the operand data of the specific scalar instruction and the copy of the data of the I / O control information due to the block replacement processing. It is to provide a computer system capable of preventing such a situation and realizing efficient synchronous processing of shared data between a plurality of processors.

[0009]

To achieve the above object, a computer system of the present invention includes main memory shared by a plurality of processors and operand data of a specific instruction shared by different processors. In a computer system having a storage controller having a communication buffer storage for holding a copy of data in block units, the communication buffer storage is also in block units for the copy of data including input / output control information shared by a plurality of processors. It is configured to be held by.

Further, the plurality of processors include all of a scalar processor, an input / output processor and a vector processor, and the storage controller directly outputs the operand data of the vector instruction from the main memory when executing the vector instruction. To the vector processor,
When executing a specific instruction in the scalar processor, a copy of data including operand data of the specific instruction is stored in the communication buffer storage in block units, and input / output control shared by the scalar processor and the input / output processor when executing the input / output instruction A copy of data containing information is stored in the communication buffer storage in block units.

Request data location determining means for detecting whether or not a storage position of request data designated by memory request addresses from a plurality of processors is included in the specific area on the main memory; When the request data location determining unit detects that the storage location of the request data is included in the specific area on the main memory, issues an access request to the request data to the communication buffer storage. And an access control means for performing the operation.

Further, for each of the blocks held in the communication buffer storage, block type information holding block type information indicating whether or not the block is a type 1 block including a copy of operand data of the specific instruction. In the replacement processing of the holding means and the block held in the communication buffer storage, the second type block which does not include the copy of the operand data of the specific instruction is preferentially replaced with the first type block. The replacement block selecting means for selecting a block so as to be the target of the above.

[0013]

The operation based on the above configuration will be described.

The computer system of the present invention comprises a main memory shared by a plurality of processors, and a communication buffer memory for holding a copy of data including operand data of a specific instruction shared by different processors in block units. In a computer system having a storage controller, the communication buffer storage holds the copy of data including input / output control information shared by a plurality of processors in block units. Request data location determining means for detecting whether or not the storage location of the request data designated by the memory request address is included in the specific area on the main memory, and the request data by the request data location determining means. Is stored in the specific area on the main memory When it is detected that is contained in, it has a configuration having a, and access control means for issuing a request for access to the requested data to the communication buffer storage.

In the above case, the plurality of processors include all of the scalar processor, the input / output processor and the vector processor, and the storage control device stores the operand data of the vector instruction in the main memory when executing the vector instruction. Directly to the vector processor, and when executing a specific instruction in the scalar processor, stores a copy of data including operand data of the specific instruction in the communication buffer storage in block units, and when executing an input / output instruction, the scalar processor and A copy of data including input / output control information shared by the input / output processors is stored in the communication buffer storage in block units.

Therefore, when the input / output control information stored in the specific area on the main memory is read as request data from the scalar processor and the input / output processor, the first operation is the same as when reading the operand data of the specific instruction. If the access request is issued to the communication buffer memory and the input / output control information is held in the communication buffer memory, the access request to the main memory is not made. This is also utilized when passing shared input / output control information, and the throughput of memory access processing from the vector processor can be improved.

Further, for each of the blocks held in the communication buffer storage, block type information holding block type information indicating whether or not the block is a type 1 block including a copy of operand data of the specific instruction. In the replacement processing of the holding means and the block held in the communication buffer storage, the second type block which does not include the copy of the operand data of the specific instruction is preferentially replaced with the first type block. Replacement block selecting means for selecting a block so as to be a target of the above.

Therefore, the type 1 block including the copy of the operand data of the specific instruction is less likely to be the target of the replacement process than the block of the type 2 that does not include the copy of the operand data of the specific instruction. As long as there are type 2 blocks in the group, it is unlikely that all type 1 blocks will be flushed from the communication buffer store. Therefore, it is possible to prevent the communication buffer storage from being occupied only by the second type block that does not include the copy of the operand data of the specific instruction due to the block replacement process, and efficiently synchronize the shared data between the plurality of processors. Processing can be realized.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a computer system of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of a computer system of the present invention. In the figure, 10 and 11 are scalar processors, 12 is an input / output processor, 2 is a vector processor, 3 is a storage controller, 4 is scalar processors 10 and 11, and an input / output processor 1.
2, the main memory shared by the vector processor 2,
Reference numeral 5 is a communication buffer storage control device, and 6 is a communication buffer storage.

FIG. 2 is a block diagram showing the internal structure of the communication buffer storage control device in FIG.
In the figure, the communication buffer storage controller 5
Is a component other than the communication buffer memory 6, a communication buffer address register 51 that holds an address for accessing the communication buffer memory 6, an address (block address) on the main memory of the block data stored in the communication buffer memory 6, and An address array 52 holding a valid bit indicating whether or not the block data is stored in the communication buffer memory 6,
The replacement array 53 for holding the replacement priority indicating bits between the respective block data stored in the communication buffer memory 6 and the block stored in the communication buffer memory 6 are a specific scalar instruction (“specific instruction” in the claims). (Corresponding to) operand data, block type information holding means 54 for holding block type information indicating whether or not the memory request address from the processor is an address included in a specific area on the main memory. And a window comparator 5B (corresponding to "request data location determining means" in claims) and the like.

Here, the contents of the address array 52, the replacement array 53, the block type information holding means 54, and the communication buffer memory 6 are all related only to the block group designated by the column address in the communication buffer address register 51. Can be referred to. Further, the vector processor 2 has a vector register 21 for holding vector data, and a large amount of data is transferred between the vector register 21 and the main memory 4 with high throughput. This means that even if something like an intermediate buffer is provided between the vector register 21 and the main memory 4, steady data transfer is performed between the intermediate buffer and the main memory 4. Therefore, the vector processor 2 generally employs a method of directly accessing the main memory 4.

First, the contents of the conventional processing for the operand read request of the specific scalar instruction,
The contents of the processing for the read request of the input / output control information performed in this embodiment will be described.

When the scalar processor 10 reads necessary shared data for the purpose of synchronizing the shared data between a plurality of processors, the scalar processor 10
Is a read request for operand data (hereinafter abbreviated as “synchronous variable”) of a specific scalar instruction (hereinafter, concretely assumed to be a TS (Test-and-set) instruction) to the storage controller 3. To issue. This specific scalar instruction is transmitted to the communication buffer storage control device 5, and the communication buffer storage access control means 58 starts access to the communication buffer storage 6 triggered by the decode signal 10c of the specific scalar instruction transmitted at the same time.

On the other hand, when the input / output processor 12 reads out the necessary shared data for the purpose of checking the presence / absence of the input / output activation request, the input / output processor 12 stores the main input / output control information. A read request for an I / O activation queue block in a specific area in the memory 4 is issued to the storage controller 3. When the address 5aa added to the read request is transmitted to the communication buffer storage controller 5 and the window comparator 5B detects that the address 5aa is included in the specific area, the communication buffer storage access control means 58 causes the communication buffer storage access control means 58 to operate. Access to the memory 6 is started.

In both cases of the shared data synchronization processing and the input / output activation request check, when the access to the communication buffer memory 6 is started, the address 5aa added to the read request is set to the communication buffer address register 51. After that, the block address including the effective bit read from the address array 52 by the column address therein and the block address in the communication buffer address register 51 are input to the hit detection means 55,
It is checked whether or not a copy of the data in the main memory 4 of one block containing the target operand data or the input / output control information has already been stored in the communication buffer memory 6.

The hit detecting means 55 reads the block address and effective bit of the block group designated by the column address in the communication buffer address register 51 from the address array 52,
The block address in which the setting value of the effective bit is “1” is compared with the block address input from the communication buffer address register 51. Then, when the values of the respective block addresses match, it is confirmed that the block data including the request data (synchronization variable or input / output activation queue block) has already been stored in the communication buffer storage 6 by the communication buffer storage access control. Report to means 58. Upon receiving this report, the communication buffer storage access control means 58 stops issuing the prepared access request to the main memory 4, and then reads and reads the synchronization variable or the input / output activation queue block from the communication buffer memory 6. The request is returned to the scalar processor 10 or the input / output processor 12 that issued the request.

The output from the hit detecting means 55 is also inputted to the replacement array updating means 57, and the replacement priority indicating bit Rij (corresponding block) of the corresponding block group held by the replacement array 53 is held. The setting value of the replacement priority between the block i and the block j in the group) is updated according to a predetermined replacement algorithm. However, the block type information holding means 5
According to 4, it is determined that the block i is a block including the synchronization variable and the block j is a block not including the synchronization variable, and when the replacement array updating unit 57 is instructed, the corresponding replacement priority instruction is performed. It is assumed that the bit Rij is unconditionally set to "1" (the replacement priority of the block j is higher than that of the block i).

In the case of synchronous processing of shared data, the scalar processor 10 that has received the synchronization variable generates the condition code of the TS instruction from the value of the synchronization variable and sets the designated bit in the synchronization variable to "1". Then, the write request to the storage controller 3 is issued. Further, in the case of checking the I / O activation request, the I / O processor 12 that has received the I / O activation queue block enters if the I / O activation queue block holds one or more I / O device control words. A dequeue operation is performed to activate the output device, and one I / O device control word is fetched. Then, the write request for the updated input / output activation queue block is issued to the storage controller 3.

For the write request of the synchronization variable or the I / O activation queue block, the communication buffer storage access control means 58 starts the access to the communication buffer storage 6 by the same processing as the read request. At this time, the writing of the synchronization variable or the I / O activation queue block is performed not only to the communication buffer memory 6 but also to the main memory 4
Also to. This is because the contents of the main memory 4 which the vector processor 2 only refers to and the contents of the communication buffer memory 6 need to be always matched.

Next, the communication buffer storage 6
The case where the synchronization variable or the input / output activation queue block is not stored in the inside will be described.

The hit detecting means 55 reads the block address and the effective bit of the block group designated by the column address in the communication buffer address register 51 from the address array 52, and the effective bit set value is "1". Address and communication buffer address register 51
Compare with the block address input from. As a result, when the block address values do not match,
It is detected that the block data including the request data (synchronization variable or I / O activation queue block) is not stored in the communication buffer memory 6.

Then, using this detection result as a trigger, a read request of block data including request data prepared in advance to the main memory 4 is issued, and the target block data is sent from the main memory 4 to the communication buffer memory 6 Transferred to and stored in. At this time, the block address of the block data is registered in the address array 52, the value "1" is set in the valid bit held by the address array 52, and the block data is stored in the block type information holding means 54 as a synchronization variable. Whether or not to include is set. When all the block data is stored in the communication buffer storage 6, and after the block address of the block data is registered in the address array 52, the request data is stored in the communication buffer storage 6 from the beginning. Common processing is performed.

Finally, the replacement (replacement processing) of the data in the communication buffer memory 6 will be described.

The hit detecting means 55 detects that the block data including the request data (synchronous variable or input / output activation queue block) is not stored in the communication buffer memory 6, and at the same time, the hit data in the communication buffer address register 51 is detected. Address array 5 for block group specified by column address
When the setting values of the valid bits in 2 are all “1”, it is recognized that all the blocks belonging to the block group have been used, and the replacement block selection unit 56 determines based on the replacement array 53. Select one block to be replaced. The replacement array 53 includes a block type information holding unit 54 and a replacement array updating unit 5.
The latest value is set by 7 and always indicates "" replacement priority of block including synchronization variable "<" replacement priority of block not including synchronization variable "". Therefore, the block containing the synchronization variable (“first” in the claims)
The case where the replacement block selecting means 56 selects a block so that the block corresponding to the “seed block” is replaced with the block not including the synchronization variable (corresponding to the “second kind block” in the claims) is the entire block group. Only when is occupied only by the block containing the synchronization variable.

[0036]

As described in detail above, according to the computer system of the present invention, a copy of data including main memory shared by a plurality of processors and operand data of a specific instruction shared by different processors. In a computer system having a storage controller having a communication buffer storage for holding each of the blocks, the communication buffer storage holds the copy of the data including the input / output control information shared by a plurality of processors in the unit of block. Configured as
Request data location determining means for detecting whether a storage location of request data designated by memory request addresses from a plurality of processors is included in the specific area on the main memory, and the request data location determining means Access control means for issuing an access request for the request data to the communication buffer storage when it is detected that the storage location of the request data is included in the specific area on the main memory. , Is provided.

In the above case, the plurality of processors include all of the scalar processor, the input / output processor, and the vector processor, and the storage control device stores the operand data of the vector instruction in the main memory when executing the vector instruction. Directly to the vector processor, and when executing a specific instruction in the scalar processor, stores a copy of data including operand data of the specific instruction in the communication buffer storage in block units, and when executing an input / output instruction, the scalar processor and A copy of data including input / output control information shared by the input / output processors is stored in the communication buffer storage in block units.

Therefore, when the input / output control information stored in the specific area on the main memory is read as request data from the scalar processor and the input / output processor, the first operation is the same as when reading the operand data of the specific instruction. If the access request is issued to the communication buffer memory and the input / output control information is held in the communication buffer memory, the access request to the main memory is not made. This is also utilized when passing shared input / output control information, and the effect that the throughput of memory access processing from the vector processor can be improved is obtained.

Further, for each of the blocks held in the communication buffer storage, block type information holding block type information indicating whether or not the block is a type 1 block including a copy of operand data of the specific instruction. In the replacement processing of the holding means and the block held in the communication buffer storage, the second type block which does not include the copy of the operand data of the specific instruction is preferentially replaced with the first type block. Replacement block selecting means for selecting a block so as to be a target of the above.

Therefore, the type 1 block containing the copy of the operand data of the specific instruction is less likely to be the target of the replacement process than the block of the type 2 containing no copy of the operand data of the specific instruction. As long as there are type 2 blocks in the group, it is unlikely that all type 1 blocks will be flushed from the communication buffer store. Therefore, it is possible to prevent the communication buffer storage from being occupied only by the second type block that does not include the copy of the operand data of the specific instruction due to the block replacement process, and efficiently synchronize the shared data between the plurality of processors. The effect that the processing can be realized is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a computer system of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a communication buffer storage control device in FIG.

[Explanation of symbols]

10, 11 Scalar processor 10c, 11c Decode signal of specific scalar instruction 12 Input / output processor 120, 121, 122 Input / output device 2 Vector processor 21 Vector register 3 Storage controller 4 Main memory 5 Communication buffer Storage controller 5a Versus processor interface 5aa Address from processor 5b Main memory interface 51 Communication buffer address register 52 Address array 53 Replacement array 54 Block type information holding means 55 Hit detection means 56 Replace block selection means 57 Replacement array update means 58 Communication buffer memory access control means 59 Main memory Register that holds the lower limit address of the upper specific area 5A Specific area in main memory Register that holds the upper limit address of 5B Window comparator 6 Communication buffer storage

Claims (4)

[Claims] 1. A storage controller comprising: a main memory shared by a plurality of processors; and a communication buffer memory for holding, in block units, a copy of data including operand data of a specific instruction shared by different processors. In the computer system having the above-mentioned item, the communication buffer memory holds the copy of data including input / output control information shared by a plurality of processors in block units. 2. A plurality of processors include all of a scalar processor, an input / output processor, and a vector processor, and the storage controller directly outputs operand data of the vector instruction from the main memory when executing the vector instruction. To the vector processor, and when executing the specific instruction in the scalar processor, store a copy of the data including the operand data of the specific instruction in the communication buffer storage in block units, and execute the input / output instruction in the scalar processor and the input / output. 2. The computer system according to claim 1, wherein a copy of data including input / output control information shared by processors is stored in the communication buffer storage in block units. 3. Request data location determining means for detecting whether or not a storage position of request data designated by memory request addresses from a plurality of processors is included in the specific area on the main memory, When the request data location determining unit detects that the storage location of the request data is included in the specific area on the main memory, issues an access request to the request data to the communication buffer storage. 3. The computer system according to claim 1, further comprising: an access control unit for controlling the access. 4. Block type information holding block type information indicating whether or not each of the blocks held in the communication buffer memory is a type 1 block including a copy of operand data of the specific instruction. In the replacement processing of the holding means and the block held in the communication buffer storage, the second type block that does not include a copy of the operand data of the specific instruction is preferentially replaced with the first type block. 4. The computer system according to claim 3, further comprising replacement block selecting means for selecting a block so as to be a target of.