JPH0823050A - Bga type semiconductor device - Google Patents
Bga type semiconductor deviceInfo
- Publication number
- JPH0823050A JPH0823050A JP6156905A JP15690594A JPH0823050A JP H0823050 A JPH0823050 A JP H0823050A JP 6156905 A JP6156905 A JP 6156905A JP 15690594 A JP15690594 A JP 15690594A JP H0823050 A JPH0823050 A JP H0823050A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- semiconductor device
- type semiconductor
- multilayer wiring
- bga type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数のボ−ル端子を底
面に有したＢＧＡ（ボ−ルグリッドアレイ）型半導体装
置に関し、特に、パッケ−ジの軽量薄型化とコストダウ
ンを図り、放熱性を高めたＢＧＡ型半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA (ball grid array) type semiconductor device having a plurality of ball terminals on its bottom surface, and more particularly, to reduce the weight and thickness of the package and reduce the cost. The present invention relates to a BGA type semiconductor device having improved heat dissipation.
【０００２】[0002]
【従来の技術】従来のＢＧＡ型半導体装置の断面構造を
図４に示す。このＢＧＡ型半導体装置は、多層配線２を
有する多層配線基板１と、多層配線基板１の表面に形成
された配線パタ−ン３と、多層配線基板１上に設けられ
たＬＳＩチップ４と、ＬＳＩチップ４の電極（図示せ
ず）と配線パタ−ン３を接続するボンディングワイヤ５
と、ＬＳＩチップ４およびその周囲を封止するモ−ルド
樹脂６と、多層配線基板１の底面に形成された複数のボ
−ル端子７から構成されている。ボ−ル端子７は多層配
線基板１の底面に設けられたボ−ル形成ランド８の上
に、ハンダペ−スト印刷法やボ−ル振込法等により形成
される。2. Description of the Related Art FIG. 4 shows a sectional structure of a conventional BGA type semiconductor device. This BGA type semiconductor device includes a multilayer wiring board 1 having multilayer wiring 2, a wiring pattern 3 formed on the surface of the multilayer wiring board 1, an LSI chip 4 provided on the multilayer wiring board 1, and an LSI. Bonding wire 5 for connecting the electrode (not shown) of the chip 4 and the wiring pattern 3
And a molding resin 6 for sealing the LSI chip 4 and its surroundings, and a plurality of ball terminals 7 formed on the bottom surface of the multilayer wiring board 1. The ball terminal 7 is formed on the ball forming land 8 provided on the bottom surface of the multilayer wiring board 1 by a solder paste printing method or a ball transfer method.
【０００３】この装置では、多層配線基板１の多層配線
２により、ＬＳＩチップ４の周囲のボンディングワイヤ
５の接続部と、底面にあるボ−ル端子７が接続されてい
る。多層配線基板を用いる理由は、配線基板技術では0.
３ｍｍのピッチが限界であることから、単層では不可能
な複雑な回路の配線引き回しを可能にするためである。
多層配線２の各層の導体はバイアホ−ル２ｂで相互に接
続されている。In this device, the multi-layer wiring 2 of the multi-layer wiring substrate 1 connects the connection portion of the bonding wire 5 around the LSI chip 4 and the ball terminal 7 on the bottom surface. The reason for using a multi-layer wiring board is that it is 0 in wiring board technology.
Since the pitch of 3 mm is the limit, it is possible to route the wiring of a complicated circuit which is impossible with a single layer.
The conductors of each layer of the multilayer wiring 2 are connected to each other by a via hole 2b.
【０００４】モ−ルド樹脂６は、全体を封止し、かつ、
配線パタ−ン３とＬＳＩチップ４の電極の間を接続する
ボンディングワイヤ５を保護するもので、多層配線基板
１の片面（ＬＳＩチップ４側）のみに施されている。The mold resin 6 seals the whole, and
It protects the bonding wire 5 that connects between the wiring pattern 3 and the electrodes of the LSI chip 4, and is provided only on one surface (the LSI chip 4 side) of the multilayer wiring board 1.
【０００５】このような構成を有するＢＧＡ型半導体装
置は、その底面のボ−ル端子７を用いてプリント基板配
線等に実装される。ボ−ル端子７をプリント配線基板等
の回路パタ−ンに接続することにより、この回路パタ−
ンとＬＳＩチップ４とが接続される。The BGA type semiconductor device having such a structure is mounted on a printed circuit board wiring or the like by using the ball terminal 7 on the bottom surface thereof. By connecting the ball terminal 7 to a circuit pattern such as a printed wiring board, this circuit pattern is
And the LSI chip 4 are connected.
【０００６】[0006]
【発明が解決しようとする課題】しかし、このような従
来のＢＧＡ型半導体装置には以下の問題がある。 (1) モ−ルド樹脂で封止しているため、厚さと重量が増
す。重さが増すと、半導体装置（パッケ−ジ）を搭載す
るＰＷＢを薄くすることができない。 (2) ＬＳＩチップがモ−ルド樹脂で封止されているた
め、放熱性が悪い。熱抵抗は通常６０℃／Ｗほどもある
ので、無風で出力０．５Ｗの半導体素子の収納が限度で
ある。 (3) モ−ルド樹脂を多層配線基板の片面のみに施してい
るため、多層配線基板の反りが発生し、下面のボ−ルの
高さが不均一となる。However, such a conventional BGA type semiconductor device has the following problems. (1) Since it is sealed with mold resin, the thickness and weight increase. If the weight increases, the PWB on which the semiconductor device (package) is mounted cannot be thinned. (2) Since the LSI chip is sealed with mold resin, heat dissipation is poor. Since the thermal resistance is usually about 60 ° C./W, there is no limit to the storage of semiconductor elements having an output of 0.5 W and no wind. (3) Since the mold resin is applied only to one surface of the multilayer wiring board, the multilayer wiring board is warped, and the height of the balls on the lower surface becomes uneven.
【０００７】(4) ＬＳＩチップが不良品であっても、多
数のボンディングワイヤを用いたボンディング作業を経
て多層配線基板との接続が終わらないと、ＬＳＩチップ
の不良が検査できず、作業および部品のロスが大きい。
特にボンディングワイヤとして通常、金線を用いるた
め、そのロスによるコストアップが大きい。ボンディン
グワイヤを用いたボンディング作業の時間は、ピン数３
００のＬＳＩチップの場合チップ当たり７５秒から１５
０秒となる。ＬＳＩチップの不良率が１０％とすると、
例えばチップ当たり５０円のコスト高となる。(4) Even if the LSI chip is defective, if the connection with the multilayer wiring board is not completed after the bonding work using a large number of bonding wires, the defect of the LSI chip cannot be inspected. The loss is large.
In particular, a gold wire is usually used as the bonding wire, so that the cost increases due to the loss. The number of pins for bonding work using the bonding wire is 3
For 00 LSI chips, 75 seconds to 15 per chip
It will be 0 seconds. If the defect rate of the LSI chip is 10%,
For example, the cost increases by 50 yen per chip.
【０００８】それ故、本発明の目的は薄型、軽量のＢＧ
Ａ型半導体装置を提供することにある。Therefore, an object of the present invention is a thin and lightweight BG.
An object is to provide an A type semiconductor device.
【０００９】本発明の他の目的は、放熱性がすぐれたＢ
ＧＡ型半導体装置を提供することにある。Another object of the present invention is B which has excellent heat dissipation.
It is to provide a GA type semiconductor device.
【００１０】本発明のさらに他の目的は、下面のボ−ル
が一平面上に位置するＢＧＡ型半導体装置を提供するこ
とにある。Still another object of the present invention is to provide a BGA type semiconductor device in which the ball on the lower surface is located on one plane.
【００１１】本発明の別の目的は、半導体素子の不良を
工程の早い段階で検出し、不良半導体素子の組み込みに
よるコスト増大が防止できる、ＢＧＡ型半導体装置を提
供することにある。Another object of the present invention is to provide a BGA type semiconductor device capable of detecting a defect of a semiconductor element at an early stage of the process and preventing an increase in cost due to the incorporation of the defective semiconductor element.
【００１２】[0012]
【課題を解決するための手段】本発明では、薄型、軽量
で、放熱性がすぐれ、下面のボ−ルが一平面上に位置
し、かつ不良半導体素子の組み込みによるコスト増大が
防止されたＢＧＡ型半導体装置を提供するため、導体ボ
−ルから成る複数の端子を下面に有する多層配線基板
と、その上に載置された半導体素子を具え、ボ−ル端子
が半導体素子の電極端子にそれぞれ接続されているＢＧ
Ａ型半導体装置において、この多層配線基板とその上に
設けられた半導体素子をＴＡＢテ−プキャリアで接続し
たＢＡＧ型半導体装置を提供する。According to the present invention, the BGA is thin, lightweight, has excellent heat dissipation, has a ball on the lower surface located on one plane, and prevents an increase in cost due to the incorporation of defective semiconductor elements. In order to provide a semiconductor device of the type, a multilayer wiring board having a plurality of terminals formed of conductor balls on the bottom surface and a semiconductor element mounted on the multilayer wiring board are provided, and the ball terminals are respectively electrode terminals of the semiconductor element. BG connected
Provided is an A-type semiconductor device, which is a BAG-type semiconductor device in which this multilayer wiring board and a semiconductor element provided thereon are connected by a TAB tape carrier.
【００１３】ＴＡＢテ−プキャリア（アウタ−リ−ド）
と多層配線基板の表面の配線パタ−ンの接続部は、１０
ないし４０％の金を含む金−錫合金で成ることが好まし
い。このような組成の合金を用いると、２５０℃程度の
比較的低い温度かつ短時間で接合できるので、接合の際
有機基板を劣化させない。TAB tape carrier (outer lead)
And the connection part of the wiring pattern on the surface of the multilayer wiring board is 10
It is preferably composed of a gold-tin alloy containing 40 to 40% gold. When an alloy having such a composition is used, bonding can be performed at a relatively low temperature of about 250 ° C. and in a short time, so that the organic substrate is not deteriorated during bonding.
【００１４】ＴＡＢテ−プキャリアは、５０ないし１５
０ミクロンの厚さのポリイミド等の絶縁体フィルムの上
にエポキシ系その他の接着剤により貼り付けられた導体
（主に銅）箔を所要のパタ−ンにフォトエッチングし
て、インナ−リ−ド、アウタ−リ−ドを形成させたもの
である。銅層の表面には、通常、ニッケル下地処理を施
した上に厚さ0.２ないし0.６ミクロンの金めっきを施
す。アウタ−リ−ドは多層配線基板との接続のため、通
常、接続前に所定の形状に曲げ加工される。The TAB tape carrier is 50 to 15
An inner lead is obtained by photo-etching a conductor (mainly copper) foil attached to an insulating film such as polyimide having a thickness of 0 micron with an epoxy or other adhesive to a desired pattern. , An outer lead is formed. The surface of the copper layer is usually nickel plated and then gold plated to a thickness of 0.2 to 0.6 microns. Since the outer lead is connected to the multilayer wiring board, it is usually bent into a predetermined shape before connection.
【００１５】半導体素子は例えばピン数２００ないし５
００のＬＳＩチップである。ＴＡＢテ−プキャリアのイ
ンナ−リ−ドとの接続のため、電極端子には通常、金バ
ンプを設けるが、金バンプを設けず超音波接合により接
続することも可能である。The semiconductor device has, for example, 200 to 5 pins.
00 LSI chip. For connection with the inner lead of the TAB tape carrier, gold bumps are usually provided on the electrode terminals, but it is also possible to connect by ultrasonic bonding without providing gold bumps.
【００１６】多層配線基板は通常２ないし４層のものが
用いられる。もちろん５層以上でもよい。導体層の数は
半導体素子のピン数や、電源層、グラウンド層の設け方
により変わる。絶縁体としてはセラミック、ガラス／エ
ポキシ、ポリイミド等を用いる。As the multilayer wiring board, one having 2 to 4 layers is usually used. Of course, five layers or more may be used. The number of conductor layers varies depending on the number of pins of the semiconductor element and how to provide the power supply layer and the ground layer. As the insulator, ceramic, glass / epoxy, polyimide or the like is used.
【００１７】多層配線基板の配線パタ−ンには、セラミ
ック多層基板の場合はペ−スト印刷による銅厚膜が、ガ
ラス／エポキシ、ポリイミド等の有機多層基板の場合は
厚さ１０ないし２０ミクロンの銅箔が用いられる。ＴＡ
Ｂテ−プキャリアのアウタ−リ−ドと接合するための表
面パッドの部分の銅層の表面には、厚さ５ないし１５ミ
クロンの錫めっきを施す。これによりＴＡＢテ−プキャ
リアのアウタ−リ−ドとの接合部を１０ないし４０％の
金を含む金−錫合金で構成することができる。For the wiring pattern of the multilayer wiring board, a thick copper film formed by paste printing in the case of a ceramic multilayer board and a thickness of 10 to 20 microns in the case of an organic multilayer board of glass / epoxy, polyimide or the like. Copper foil is used. TA
The surface of the copper layer in the portion of the surface pad for bonding with the outer lead of the B tape carrier is tin-plated with a thickness of 5 to 15 μm. As a result, the joining portion of the TAB tape carrier with the outer lead can be made of a gold-tin alloy containing 10 to 40% of gold.
【００１８】ＴＡＢテ−プキャリアのアウタ−リ−ドと
多層配線基板の表面の接続パッドを１０ないし４０％の
金を含む金−錫合金で接合すると、２５０℃程度の比較
的低温で接合できるので、有機基板を劣化させないで接
合を行なうことができる。特開平５−１３６３１８号に
記載されたように、加熱器具を用いると３ないし５秒間
で３００ないし５００ピンを同時に接合できる。When the outer lead of the TAB tape carrier and the connection pad on the surface of the multilayer wiring board are joined with a gold-tin alloy containing 10 to 40% of gold, they can be joined at a relatively low temperature of about 250.degree. Therefore, the bonding can be performed without degrading the organic substrate. As described in Japanese Patent Laid-Open No. 5-136318, using a heating device, 300 to 500 pins can be simultaneously joined in 3 to 5 seconds.
【００１９】多層配線基板の裏面に形成する導体ボ−ル
には、４０％の鉛を含む共晶はんだ合金、１０％の錫を
含む耐熱はんだ合金、単体の銅等が用いられる。ボ−ル
の形成にはボ−ル振込法や、はんだペ−スト印刷法を用
いる。A eutectic solder alloy containing 40% of lead, a heat-resistant solder alloy containing 10% of tin, a single piece of copper or the like is used for the conductor ball formed on the back surface of the multilayer wiring board. A ball transfer method or a solder paste printing method is used for forming the ball.
【００２０】[0020]
【作用】本発明のＢＧＡ型半導体装置は、底面に複数の
ボ−ル端子を設けた多層配線基板と、多層配線基板上に
載置された半導体素子と、そして半導体素子の電極と多
層配線基板の表面の配線パタ−ンを接続するＴＡＢテ−
プキャリアから成り、このＴＡＢテ−プキャリアのイン
ナ−リ−ドが半導体素子の電極に、アウタ−リ−ドが多
層配線基板の表面の配線パタ−ンにそれぞれ接続されて
いる。それ故、多層配線基板下面の複数の導体ボ−ル
は、多層配線基板の配線パタ−ンとバイアホ−ル、基板
表面の配線パタ−ン、ＴＡＢテ−プキャリアのアウタ−
リ−ド、インナ−リ−ドを経て半導体素子の電極端子
に、それぞれ接続される。The BGA type semiconductor device of the present invention comprises a multilayer wiring board having a plurality of ball terminals on the bottom surface, a semiconductor element mounted on the multilayer wiring board, and electrodes of the semiconductor element and the multilayer wiring board. TAB cable to connect the wiring pattern on the surface of
The TAB tape carrier has an inner lead connected to the electrode of the semiconductor element and an outer lead connected to the wiring pattern on the surface of the multilayer wiring board. Therefore, the plurality of conductor balls on the bottom surface of the multi-layer wiring board have wiring patterns and via holes on the multi-layer wiring board, wiring patterns on the board surface, and outer layers on the TAB tape carrier.
They are respectively connected to the electrode terminals of the semiconductor element through the leads and the inner leads.
【００２１】半導体素子の電極端子と多層配線基板との
接続がＴＡＢテ−プキャリアのアウタ−リ−ド、インナ
−リ−ドによって行なわれるので、多層配線基板との接
続が終わらなくても、ＬＳＩチップの不良を検査でき、
作業および部品のロスを防ぐことができる。特にボンデ
ィングワイヤとして通常用いられる金線のロスによるコ
ストアップが解消される。Since the connection between the electrode terminals of the semiconductor element and the multilayer wiring board is made by the outer lead and the inner lead of the TAB tape carrier, even if the connection with the multilayer wiring board is not completed, Can inspect LSI chips for defects,
Work and parts loss can be prevented. In particular, the cost increase due to the loss of the gold wire normally used as a bonding wire is eliminated.
【００２２】ＴＡＢテープキャリアを用いた場合従来の
モ−ルド樹脂による封止が不要となるため、ＢＧＡ型半
導体装置を薄くすることができ、放熱をよくすることが
できる。また、モ−ルド樹脂を多層配線基板の片面のみ
に施すことによる多層配線基板の反りが生じないから、
下面のボ−ルの高さを均一にすることができる。When the TAB tape carrier is used, the BGA type semiconductor device can be thinned and the heat dissipation can be improved because the conventional sealing with the mold resin is unnecessary. Moreover, since the warp of the multilayer wiring board does not occur due to the mold resin being applied to only one surface of the multilayer wiring board,
The height of the balls on the lower surface can be made uniform.
【００２３】[0023]
【実施例】以下に実施例を示し、本発明をより具体的に
説明する。 ［実施例１］図１に本発明によるＢＧＡ型半導体装置の
断面を示す。また図２に一部分の拡大断面図を示す。こ
のＢＧＡ型半導体装置は、底面に複数のボ−ル端子７を
設けた多層配線基板１と、多層配線基板１上に設けられ
たＬＳＩチップ４（半導体素子）と、ＴＡＢテ−プキャ
リア１１から主に構成されている。ＴＡＢテ−プキャリ
ア１１は、ポリイミドフィルム１２上に貼り付けられた
インナ−リ−ド１３とアウタ−リ−ド１４を有する。イ
ンナ−リ−ド１３はＬＳＩチップ４の電極バンプ４ａに
接合され、アウタ−リ−ド１４は、接合部１５を介して
多層配線基板１の表面の配線パッド２ａに接合されてい
る。ボ−ル端子７は多層配線基板１の底面のボ−ル形成
ランド８の上に形成される。多層配線基板１の各層の配
線パタ−ン２の導体はバイアホ−ル２ｂで相互に接続さ
れている。EXAMPLES The present invention will be described more concretely with reference to the following examples. [Embodiment 1] FIG. 1 shows a cross section of a BGA type semiconductor device according to the present invention. Further, FIG. 2 shows a partially enlarged sectional view. This BGA type semiconductor device includes a multilayer wiring board 1 having a plurality of ball terminals 7 on the bottom surface, an LSI chip 4 (semiconductor element) provided on the multilayer wiring board 1, and a TAB tape carrier 11. It is mainly composed. The TAB tape carrier 11 has an inner lead 13 and an outer lead 14 attached on a polyimide film 12. The inner lead 13 is joined to the electrode bumps 4a of the LSI chip 4, and the outer lead 14 is joined to the wiring pads 2a on the front surface of the multilayer wiring board 1 via the joining portions 15. The ball terminal 7 is formed on the ball forming land 8 on the bottom surface of the multilayer wiring board 1. The conductors of the wiring patterns 2 of the respective layers of the multilayer wiring board 1 are connected to each other by via holes 2b.
【００２４】ＬＳＩチップ４は３００ピンの半導体素子
である。ＴＡＢテ−プキャリア１１は、厚さ７５ミクロ
ンのポリイミドフィルム１２上に厚さ２５ミクロンの銅
箔をエポキシ系接着剤で貼り付けたものである。この銅
箔のフォトケミカルエッチングによりインナ−リ−ド１
３、アウタ−リ−ド１４、およびフィルム上の配線パタ
−ンが形成される。これらの上には厚さ0.５ミクロンの
ニッケルめっきを施した上に厚さ0.５ミクロンの金めっ
きが施されている。The LSI chip 4 is a 300-pin semiconductor element. The TAB tape carrier 11 is formed by attaching a copper foil having a thickness of 25 μm on a polyimide film 12 having a thickness of 75 μm with an epoxy adhesive. Inner lead 1 by photochemical etching of this copper foil
3, the outer lead 14, and the wiring pattern on the film are formed. These are plated with nickel having a thickness of 0.5 micron and gold with a thickness of 0.5 micron.
【００２５】多層配線基板１は４層の導体層を有するセ
ラミック基板である。各層の配線パタ−ン２の導体は銅
ペ−スト厚膜印刷により形成される。最上層の配線パタ
−ンには７ないし１０ミクロンの錫めっきが施されてい
る。バイアホ−ル２ｂを介する各層の導体の接続には、
モリブデンペ−ストの穴埋め印刷を用いた。The multilayer wiring board 1 is a ceramic board having four conductor layers. The conductor of the wiring pattern 2 of each layer is formed by copper paste thick film printing. The wiring pattern of the uppermost layer is plated with tin of 7 to 10 microns. To connect the conductors of each layer through the via hole 2b,
Fill-in-place printing of molybdenum paste was used.
【００２６】上述のＢＧＡ型半導体装置は以下のように
して製造した。ＬＳＩチップ４の電極と一致する位置に
インナ−リ−ド１３を有するＴＡＢテ−プキャリア１１
を製造した。すなわち、厚さ７５ミクロンのポリイミド
フィルム１２上に厚さ２５ミクロンの銅箔をエポキシ系
接着剤で貼り付けた。この銅箔のフォトケミカルエッチ
ングによりインナ−リ−ド１３、アウタ−リ−ド１４及
びフィルム上の配線パタ−ンを形成した。これらの上に
厚さ0.５ミクロンのニッケルめっきを施し、さらに厚さ
0.５ミクロンの金めっきを施した。The BGA type semiconductor device described above was manufactured as follows. A TAB tape carrier 11 having an inner lead 13 at a position corresponding to the electrode of the LSI chip 4.
Was manufactured. That is, a 25-micron-thick copper foil was attached to a 75-micron-thick polyimide film 12 with an epoxy adhesive. An inner lead 13, an outer lead 14 and a wiring pattern on the film were formed by photochemical etching of this copper foil. 0.5 micron thick nickel plating is applied on top of these and further
It was plated with 0.5 micron of gold.
【００２７】セラミック板上に銅ペ−スト厚膜印刷によ
り形成された４層の導体層を有する多層配線基板を用意
し、その最上層の配線パタ−ンに無電解めっき法により
７ないし１０ミクロンの錫めっきを施した。ＬＳＩチッ
プ４の表面の電極部には、金めっきでパンプ４a を形成
した。A multilayer wiring board having four conductor layers formed by copper paste thick film printing on a ceramic plate is prepared, and the wiring pattern of the uppermost layer is made to have a thickness of 7 to 10 μm by electroless plating. Tin plated. A bump 4a was formed on the electrode portion on the surface of the LSI chip 4 by gold plating.
【００２８】これらの部品を次のようにして組み立て
た。ＬＳＩチップ４のパンプ４a とＴＡＢテ−プキャリ
ア１１のインナ−リ−ド１３とを超音波シングルポイン
トボンダ−により接合した。接合後、ＬＳＩチップ４の
表面および接合部をエポキシ系の封止レジン１６でポッ
ティング封止した。ポッティング封止には、液状の封止
レジンをディスペンサ−（部分塗布用筆）で塗布した。These parts were assembled as follows. The pump 4a of the LSI chip 4 and the inner lead 13 of the TAB tape carrier 11 were joined by an ultrasonic single point bonder. After the joining, the surface of the LSI chip 4 and the joined portion were potted and sealed with an epoxy type sealing resin 16. For potting sealing, a liquid sealing resin was applied with a dispenser (partial coating brush).
【００２９】ここまでの組立品（ＴＡＢチップ）にバ−
ンイン試験を行なった。バ−ンイン試験は、通電しなが
ら温度１５０℃で１０時間加熱し、エ−ジングしながら
良品を選別するものである。良品チップのみについて、
アウタ−リ−ド１４に曲げ加工した。曲げ加工は金型を
用いて連続的に行なった。曲げ加工後のアウタ−リ−ド
１４を多層配線基板１の表面の配線パッド２ａと位置合
わせし、加熱接合ツ−ルを用いて３００本のピンを同時
接合した。接合ツ−ルの温度は２５０℃とし、１０ｋｇ
／ｃｍ2 の加圧下に５秒間で接合した。多層配線基板１
は縦横とも３１ｍｍ、厚さ0.３５ｍｍのものである。A bar is attached to the assembly (TAB chip) up to this point.
An in-line test was conducted. In the burn-in test, a good product is selected by heating at a temperature of 150 ° C. for 10 hours while energizing and aging. Only good chips
The outer lead 14 was bent. Bending was continuously performed using a mold. The outer lead 14 after bending was aligned with the wiring pad 2a on the surface of the multilayer wiring board 1, and 300 pins were simultaneously bonded using a heating bonding tool. The temperature of the joining tool is 250 ℃, 10kg
Bonding was carried out for 5 seconds under a pressure of / cm @ 2. Multilayer wiring board 1
Has a length and width of 31 mm and a thickness of 0.35 mm.
【００３０】最後に多層配線基板１の下面にボ−ル７を
形成した。直径２０ないし２５μｍのはんだ粒子（錫
６、鉛４）をイミダゾ−ル系フラックス、アルコ−ルと
混合してはんだペ−ストとし、これをメタルマスクスク
リ−ン印刷法によりボ−ル形成ランド１２の上に塗布し
た。全体を温度２３０℃のリフロ−炉に通し、窒素ガス
気流中ではんだ粒子を溶融し、はんだの表面張力でボ−
ル７を形成させた。ボ−ルの数は２２５、ボ−ルのピッ
チは１．５ｍｍである。Finally, the ball 7 was formed on the lower surface of the multilayer wiring board 1. Solder particles (tin 6 and lead 4) having a diameter of 20 to 25 μm are mixed with an imidazole flux and an alcohol to form a solder paste, which is formed on a ball forming land 12 by a metal mask screen printing method. Applied on. The whole is passed through a reflow oven at a temperature of 230 ° C, the solder particles are melted in a nitrogen gas stream, and the surface tension of the solder is used to blow the solder particles.
Le 7 was formed. The number of balls is 225, and the pitch of the balls is 1.5 mm.
【００３１】これで組立が終了するので、この後、接合
部、ボ−ル部等について外観検査を行なった。バ−ンイ
ン試験は多層配線基板１との接続前に済んでいるので、
行なう必要がない。Since the assembly is completed by this, the joint portion, the ball portion and the like are visually inspected thereafter. Since the burn-in test is completed before the connection with the multilayer wiring board 1,
There is no need to do it.
【００３２】完成したＢＧＡ型半導体装置は厚さが１．
４ｍｍ、重量が３．１ｇであった。これは、ボ−ル数２
２５の従来のＢＧＡ型半導体装置に比べて厚さが約１／
３、重量が約６割である。従来のＢＧＡ型半導体装置は
さらに放熱板を取り付ける必要があるが、本発明のもの
は放熱板を必要としないので、放熱板込みの重量で比較
すると、本発明のものは従来品の約１／３である。The completed BGA type semiconductor device has a thickness of 1.
It was 4 mm and weighed 3.1 g. This is the number of balls 2
Compared with the 25 conventional BGA type semiconductor devices, the thickness is about 1 /
3, the weight is about 60%. Although the conventional BGA type semiconductor device needs to be further attached with a heat sink, the present invention does not require a heat sink. Therefore, comparing the weight including the heat sink, the present invention has about 1 / th of the conventional product. It is 3.
【００３３】ＴＡＢチップと多層配線基板との接続前に
不良品検査を行なうため、不良ＬＳＩチップの組み込み
による材料および労力のロスが減少し、これにより約６
％のコスト減が達成された。Since the defective product inspection is performed before the connection between the TAB chip and the multi-layer wiring board, the loss of material and labor due to the incorporation of the defective LSI chip is reduced.
% Cost reduction was achieved.
【００３４】［実施例２］実施例１における多層配線基
板１としてポリイミド多層配線基板を用いた。その他の
構成は実施例１と同じである。[Example 2] A polyimide multilayer wiring board was used as the multilayer wiring board 1 in Example 1. Other configurations are the same as those in the first embodiment.
【００３５】［実施例３］本発明によるＢＧＡ型半導体
装置の別の例の断面を図３に示す。このＢＧＡ型半導体
装置では、ＴＡＢテ−プキャリア１１の代わりにフリッ
プＴＡＢ３１を用いた。フリップＴＡＢはＬＳＩチップ
４を接続後ポリイミドフィルムおよびアウタリードを除
去してインナーリ−ド部のみが残される。フリップＴＡ
Ｂは構造上多層配線基板１への接続ピッチとＬＳＩチッ
プ４への接続ピッチが同じなので、位置合わせには画像
認識付高精度接合機を用いた。フリップＴＡＢを用いる
と、ベ−スフィルムがない分ＴＡＢ部分を小型化すると
ともに、ボ−ルグリッドのピッチを小さくして、全体を
小型化できる。例えばボ−ルグリッドのピッチを１．０
ｍｍとし、３００ピンのＬＳＩチップ４に対して多層配
線基板１の寸法を２０ｍｍ角にすることができた。[Embodiment 3] FIG. 3 shows a cross section of another example of the BGA type semiconductor device according to the present invention. In this BGA type semiconductor device, a flip TAB 31 is used instead of the TAB tape carrier 11. After connecting the LSI chip 4 to the flip TAB, the polyimide film and the outer leads are removed and only the inner lead portion is left. Flip TA
Since the connection pitch of B to the multilayer wiring board 1 and the connection pitch to the LSI chip 4 are the same structurally, a high-accuracy bonding machine with image recognition was used for alignment. When the flip TAB is used, the TAB portion can be downsized because there is no base film, and the pitch of the ball grid can be reduced to downsize the whole. For example, the pitch of the ball grid is 1.0
The size of the multilayer wiring board 1 can be 20 mm square with respect to the LSI chip 4 having 300 pins.
【００３６】[0036]
【発明の効果】本発明によると、樹脂モ−ルドによる封
止を用いないので、薄型、軽量で、放熱性がすぐれたＢ
ＧＡ型半導体装置が得られ、そしてＢＧＡ型半導体装置
の下面のボ−ルの高さも均一にすることができる。また
多層配線基板の接続前に不良品検査が可能となるため、
不良ＬＳＩチップの組み込みによるコスト増大が防止さ
れる。According to the present invention, since the sealing by the resin mold is not used, it is thin and lightweight and has excellent heat dissipation.
A GA type semiconductor device can be obtained, and the height of the ball on the lower surface of the BGA type semiconductor device can be made uniform. In addition, since it is possible to inspect defective products before connecting the multilayer wiring board,
Cost increase due to incorporation of defective LSI chips is prevented.
【図１】本発明のＢＧＡ型半導体装置の断面図。FIG. 1 is a sectional view of a BGA type semiconductor device of the present invention.
【図２】本発明のＢＧＡ型半導体装置の部分拡大断面
図。FIG. 2 is a partially enlarged sectional view of a BGA type semiconductor device of the present invention.
【図３】本発明のＢＧＡ型半導体装置の断面図。FIG. 3 is a sectional view of a BGA type semiconductor device of the present invention.
【図４】従来のＢＧＡ型半導体装置の断面図。FIG. 4 is a sectional view of a conventional BGA type semiconductor device.
１ 多層配線基板 ２ 多層配線パタ−ン ２ａ 配線パッド ２ｂ バイアホ−ル ３ 配線パタ−ン ４ ＬＳＩチップ ４ａ 電極バンプ ５ ボンディングワイヤ ６ モ−ルド樹脂 ７ ボ−ル、ボ−ル端子 ８ ボ−ル形成ランド １１ ＴＡＢテ−プキャリア １２ ポリイミドフィルム １３ インナ−リ−ド １４ アウタ−リ−ド １５ 接合部 １６ 封止レジン ３１ フリップＴＡＢ 1 Multilayer Wiring Board 2 Multilayer Wiring Pattern 2a Wiring Pad 2b Via Hole 3 Wiring Pattern 4 LSI Chip 4a Electrode Bump 5 Bonding Wire 6 Mold Resin 7 Ball, Ball Terminal 8 Ball Formation Land 11 TAB tape carrier 12 Polyimide film 13 Inner lead 14 Outer lead 15 Joining portion 16 Sealing resin 31 Flip TAB
Claims (3)
有する多層配線基板と、この多層配線基板の上に載置さ
れた半導体素子とを具え、前記端子が前記半導体素子の
電極端子にそれぞれ接続されているＢＧＡ（ボ−ルグリ
ッドアレイ）型半導体装置において、 前記多層配線基板と前記半導体素子を接続するＴＡＢテ
−プキャリアを具え、 このＴＡＢテ−プキャリアのインナ−リ−ドが前記半導
体素子の電極端子に、アウタ−リ−ドが前記多層配線基
板の表面の配線パタ−ンに、それぞれ接続されているこ
とを特徴とするＢＧＡ型半導体装置。1. A multi-layer wiring board having a plurality of terminals formed of conductor balls on a lower surface thereof, and a semiconductor element mounted on the multi-layer wiring board, wherein the terminals are electrode terminals of the semiconductor element. A BGA (ball grid array) type semiconductor device connected to each other comprises a TAB tape carrier for connecting the multilayer wiring board and the semiconductor element, and the inner lead of the TAB tape carrier is A BGA type semiconductor device characterized in that an outer lead is connected to an electrode terminal of the semiconductor element and to a wiring pattern on a surface of the multilayer wiring board, respectively.
−ドと前記多層配線基板の表面の配線パタ−ンの接続部
が、１０ないし４０％の金を含む金−錫合金で構成され
ている、請求項１のＢＧＡ型半導体装置。2. The connecting portion between the outer lead of the TAB tape carrier and the wiring pattern on the surface of the multi-layer wiring board is composed of a gold-tin alloy containing 10 to 40% of gold. The BGA type semiconductor device according to claim 1.
リードだけより成るフリップ型である、請求項１または
２のＢＧＡ型半導体装置。3. The BGA type semiconductor device according to claim 1, wherein the TAB tape carrier is a flip type which is composed only of inner leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6156905A JP2956480B2 (en) | 1994-07-08 | 1994-07-08 | BGA type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6156905A JP2956480B2 (en) | 1994-07-08 | 1994-07-08 | BGA type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0823050A true JPH0823050A (en) | 1996-01-23 |
| JP2956480B2 JP2956480B2 (en) | 1999-10-04 |
Family
ID=15637960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6156905A Expired - Fee Related JP2956480B2 (en) | 1994-07-08 | 1994-07-08 | BGA type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2956480B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012120982A1 (en) | 2011-03-07 | 2012-09-13 | Jx日鉱日石金属株式会社 | COPPER OR COPPER ALLOY REDUCED IN α-RAY EMISSION, AND BONDING WIRE OBTAINED FROM COPPER OR COPPER ALLOY AS RAW MATERIAL |
-
1994
- 1994-07-08 JP JP6156905A patent/JP2956480B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012120982A1 (en) | 2011-03-07 | 2012-09-13 | Jx日鉱日石金属株式会社 | COPPER OR COPPER ALLOY REDUCED IN α-RAY EMISSION, AND BONDING WIRE OBTAINED FROM COPPER OR COPPER ALLOY AS RAW MATERIAL |
| US9597754B2 (en) | 2011-03-07 | 2017-03-21 | Jx Nippon Mining & Metals Corporation | Copper or copper alloy, bonding wire, method of producing the copper, method of producing the copper alloy, and method of producing the bonding wire |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2956480B2 (en) | 1999-10-04 |
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