JPH0823000A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve electrostatic breakdown voltage without deteriorating high frequency characteristics, in a semiconductor integrated circuit device using a compound semiconductor substrate. CONSTITUTION:A P-type first semiconductor region 9a which electrically connects a bonding pad 2S for an input signal with a bonding pad 2G for supplying a ground potential is formed in the upper part of a semiconductor substrate 3 composed of compound semiconductor. One end of an N-type second semiconductor region 9b which is electrically connected with a bonding pad 2V for supplying a power supply potential is brought into contact with a channel region 9a2 of the first semiconductor region 9a. In the contact part, a protective circuit constituting a PN junction part 10 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a semiconductor integrated circuit device using a compound semiconductor substrate.

[0002]

2. Description of the Related Art As the information-oriented society advances, it is required to develop an integrated circuit capable of processing high density information at high speed. A semiconductor integrated circuit device using a compound semiconductor substrate typified by gallium arsenide (GaAs) has attracted attention because it meets the demand.

Compound semiconductor substrates such as GaAs are
This is because it has excellent advantages such as a large carrier mobility compared with a semiconductor of a single element such as silicon (Si) and the like, which can be expected to improve the device operation speed, a large substrate resistance, and a small stray capacitance.

Conventionally, in a semiconductor integrated circuit device using a compound semiconductor substrate, an element formed on the compound semiconductor substrate is protected from static electricity or the like between an input pad or an output pad and an internal circuit. There was a protection circuit. The protection circuit is composed of, for example, MES • FET, and the input pad or the output pad is the MES.
-It was configured to be electrically connected to the gate of the FET.

Regarding such a protection circuit, for example, Baifukan Co., Ltd., issued November 30, 1986,
"Ultrafast compound semiconductor device" P297, Fig. 8.31
Is disclosed in.

However, in the case of the protection circuit composed of MES.FET, its gate portion forms a Schottky junction with the compound semiconductor substrate (see P59 of the above-mentioned document, FIGS. 3.2 and P40). As shown in FIG. 2.20), the structure is such that sufficient electrostatic breakdown voltage cannot be obtained. For this reason, the semiconductor integrated circuit device using the compound semiconductor substrate in that case is vulnerable to static electricity, and requires attention when handling it.

Therefore, in order to solve such a problem,
A protection circuit including a diode and a resistor is provided between the input pad or the output pad and the internal circuit.

[0008]

SUMMARY OF THE INVENTION However, the present inventor has found that the above-described conventional technique using a diode and a resistor as a protection circuit for a semiconductor integrated circuit device using a compound semiconductor substrate has the following problems. .

That is, in this case, since a protective element such as a diode or a resistor is interposed between the input pad or the output pad and the internal circuit, there is a problem that the high frequency characteristics of the signal are deteriorated. On the other hand, when a protective element is inserted to the extent that the high frequency characteristics are not impaired, there is a problem that a sufficient protective effect against electrostatic breakdown cannot be obtained.

An object of the present invention is to provide a technique capable of improving electrostatic breakdown voltage in a semiconductor integrated circuit device using a compound semiconductor substrate without impairing high frequency characteristics.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0012]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention is provided with a signal pad, a power supply potential supply pad, and a ground potential supply pad on a compound semiconductor substrate, and the signal pad and the ground potential supply are provided. A first semiconductor region that is electrically connected to a power supply pad is provided in the compound semiconductor substrate, and is electrically connected to the power supply potential supply pad, and a power supply potential is supplied to the power supply potential supply pad. To protect the semiconductor integrated circuit formed on the compound semiconductor substrate by providing an opening / closing portion that disconnects the conduction state between the signal pad and the ground potential supply pad by depleting the first semiconductor region. Is a protection circuit.

[0014]

According to the above semiconductor integrated circuit device of the present invention, the following actions can be obtained.

First, when the semiconductor integrated circuit device is not operating and the power supply voltage is not applied to the power supply voltage supply pad, the signal pad and the ground potential supply pad are electrically connected through the first semiconductor region. Because it is done
At this time, even if an overvoltage or overcurrent due to static electricity or the like is applied to the signal pad, the charge can be released to the ground potential supply pad side, and the overvoltage or the like is directly applied to the internal circuit. It becomes possible to prevent it.

On the other hand, in the operation of the semiconductor integrated circuit device, when the power supply voltage is applied to the power supply voltage supply pad, the channel portion of the first semiconductor region connecting the signal pad and the ground potential supply pad is connected. Is depleted by the opening / closing section, and the conduction state between the signal pad and the ground potential supply pad can be cut off, so that it is possible to prevent the problem that the protection circuit deteriorates the high frequency characteristics of the input signal. .

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is an overall plan view of a semiconductor chip which constitutes a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a plan view of essential parts of the semiconductor chip of FIG. 1, and FIG.
-III sectional view, FIG. 4 is a sectional view taken along the line IV-IV of FIG. 2, and FIG. 5 and FIG. 6 are explanatory views schematically showing main-part sectional views of the semiconductor integrated circuit device of this embodiment.

The semiconductor integrated circuit device of this embodiment is a mobile communication LSI (Large Scale Integrated Circuit) which constitutes a mobile communication device such as a car telephone. A semiconductor chip constituting the semiconductor integrated circuit device of this embodiment is shown in FIG.

The semiconductor chip 1 is constructed by using a compound semiconductor as a substrate as described later, and a plurality of bonding pads 2 are arranged in the vicinity of the outer periphery of its main surface. The bonding pad 2 is made of, for example, aluminum (A
l) System electrodes, which are arranged at predetermined intervals along the outer periphery of the semiconductor chip 1.

The bonding pad 2 electrically connects a semiconductor integrated circuit formed on the main surface of the semiconductor chip 1 and a circuit external to the semiconductor chip 1 through a bonding wire (not shown) connected to the bonding pad 2. It is a terminal for connecting to. In addition, the broken line in FIG.
The formation area of a semiconductor integrated circuit is shown.

Here, FIG. 2 shows a plan view of a main part of the semiconductor chip 1. In addition, lines III-III and IV- in FIG.
Sectional views taken along line IV are shown in FIGS. 3 and 4, respectively.

A semiconductor substrate 3 which constitutes the semiconductor chip 1.
Consists of a compound semiconductor such as GaAs,
On its main surface, for example, a semiconductor integrated circuit element such as an n-channel type MES • FET4 forming an input circuit is formed.

Source region 4 constituting MES • FET4
The s and drain regions 4d are formed by introducing n-type impurity silicon (Si) into the upper portion of the semiconductor substrate 3,
The impurity concentration is, for example, about 1 × 10 ¹⁸ pieces / cm ³ .

A source electrode 4sp and a drain electrode 4 are provided on the source region 4s and the drain region 4d, respectively.
dp is formed in an ohmic contact state. The source electrode 4sp and the drain electrode 4dp are formed of, for example, gold (A
u) -germanium (Ge) alloy, and the insulating film 5
Through the connection holes 6a and 6b formed in the holes a and 5b, they are electrically connected to the upper wirings 7a and 7b, respectively.
The wirings 7a and 7b are made of, for example, Al-based electrodes.

On the upper part of the semiconductor substrate 3, a channel region 4c is formed between the source region 4s and the drain region 4d so as to connect them. The channel region 4c is formed by introducing, for example, n-type impurity Si, and the impurity concentration thereof is, for example, about 3 × 10 ¹⁷ pieces / cm ³ .

A gate electrode 4g is formed on the channel region 4c.
Are formed in a Schottky contact state. The gate electrode 4g is made of, for example, Al and is electrically connected to the upper wiring 7c through a connection hole 6c formed in the insulating films 5a and 5b. The wiring 7c is made of, for example, an Al-based electrode, and is electrically connected to the input signal bonding pad (signal pad) 2S.

The source electrode 4sp and the drain electrode 4
The dp and the gate electrode 4g are formed by a lift-off method, for example. The insulating film 5c is an insulating film used at the time of forming the lift-off, and is, for example, silicon dioxide (Si
O ₂ ). The insulating film 5 means the insulating films 5a to 5c. The insulating film 8 is a surface protective film and is made of, for example, silicon nitride (Si ₃ N ₄ ).

Further, in this embodiment, the semiconductor substrate 3
In the area where the bonding pad 2 is formed, a protection circuit 9 for protecting the semiconductor integrated circuit in the semiconductor chip 1 from static electricity is formed.

The protection circuit 9 has a first semiconductor region 9a and a second semiconductor region 9b. First semiconductor region 9a
Are input signal bonding pads 2S and ground potential supply bonding pads (ground potential supply pads).
The lead-out regions 9a1 and 9a1, which are regions electrically connected to the 2G, are formed directly below the bonding pad 2S for the input signal and the bonding pad 2G for supplying the ground potential in the upper part of the semiconductor substrate 3, and those regions. It is composed of a channel region 9a2 formed so as to connect them between 9a1 and 9a1.

The lead-out region 9a1 is formed by introducing, for example, magnesium (Mg), which is a p-type impurity, and is electrically connected to the bonding pads 2S and 2G via the metal layers 9S and 9G formed in ohmic contact therewith. It is connected. The extraction region 9a1 is formed by, for example, an ion implantation method, and its impurity concentration is, for example, 1 × 1.
It is about 0 ¹⁸ pieces / cm ³ . In addition, the metal layers 9S and 9G
Is made of, for example, an AuZn alloy.

The channel region 9a2 is formed by introducing, for example, p-type impurity Mg, and its width, cross-sectional area, impurity concentration, and the like are one of those of the channel region 9a2 during operation of the semiconductor integrated circuit device, as will be described later. It is set to such an extent that it is closed by the depletion layer formed in the part. The channel region 9a2 is formed by, for example, an ion implantation method, and the impurity concentration thereof is, for example, 2 × 10 ¹⁷ pieces /
It is about cm ³ .

On the other hand, the above-mentioned second semiconductor region 9b is a lead-out region 9b1 formed directly below the bonding pad (power-source potential supply pad) 2V for supplying a power-source potential on the upper part of the semiconductor substrate 3, and the lead-out region 9b1. And a semiconductor region 9b2 electrically connected to the semiconductor region 9b2.

The lead-out region 9b1 is formed by introducing, for example, Si of an n-type impurity, and the bonding pad 2V is formed on the lead-out region 9b1 via a metal layer 9V formed in ohmic contact therewith.
Is electrically connected to. Extraction region 9b1 is formed of, for example, by ion implantation, the impurity concentration is 1 × 10 ¹⁸ / cm ^3, for example, about.

The semiconductor region 9b2 is formed by introducing, for example, n-type impurity Si, and one end thereof is brought into contact with the above-mentioned channel region 9a2 to form a pn junction (opening / closing portion) 10 at the contact portion. ing. That is, a portion for opening and closing the channel region 9a2 is formed in the pn junction 10. Semiconductor region 9b2 is formed of, for example, by ion implantation, the impurity concentration is, for example, 3 × 10 ¹⁷ / cm ³ or so.

The operation of the semiconductor integrated circuit device of this embodiment will be described with reference to FIGS. In FIGS. 5 and 6, the depletion layer 1 in the pn junction 10 is
In order to make 1 easy to see, hatching is not shown in the entire first semiconductor region 9a and a part of the semiconductor region 9b2.

FIG. 5 schematically shows a cross section of the main part of the semiconductor integrated circuit device when it is not operating. That is, the case where the power supply voltage is not applied to the bonding pad 2V for supplying the power supply potential is shown.

In this case, as shown in FIG. 5, since the depletion layer 11 (oblique line) formed in the pn junction 10 is small and does not close the channel region 9a2, the bonding pad 2S for the input signal and the ground potential are formed. The supply bonding pad 2G is electrically connected through the first semiconductor region 9a.

Therefore, at this time (when not operating), even if an overvoltage or an overcurrent due to static electricity is applied to the bonding pad 2S for input signal, the electric charge is supplied to the ground potential through the first semiconductor region 9a. Since it can be released to the bonding pad 2G side, it is possible to prevent the overvoltage or the like from being directly applied to the semiconductor integrated circuit of the semiconductor chip 1.

On the other hand, FIG. 6 schematically shows a cross section of a main part of the semiconductor integrated circuit device during operation. That is,
Power supply voltage V to bonding pad 2V for supplying power supply potential
It shows the case where CC is applied.

In this case, the channel region 9a2 of the first semiconductor region 9a connecting the bonding pad 2S for the input signal and the bonding pad 2G for supplying the ground potential is
Since it is closed by the depletion layer 11 formed in the pn junction portion 10, it is possible to disconnect the conduction state between the input signal bonding pad 2S and the ground potential supply bonding pad 2G.

Therefore, in this case (during operation), it is possible to prevent the protection circuit 9 from being interposed between the input signal bonding pad 2S and the semiconductor integrated circuit, so that the high frequency characteristic of the input signal is improved. The protection circuit 9 can prevent the deterioration.

As described above, according to this embodiment, the following effects can be obtained.

(1). When the semiconductor integrated circuit device is not operating and the power supply voltage is not applied to the bonding pad 2V for supplying the power supply potential, the bonding pad 2S for the input signal and the bonding pad for supplying the ground potential are provided. Since 2G is electrically connected to the second semiconductor region 9a through the first semiconductor region 9a, even if an overvoltage or an overcurrent due to static electricity or the like is applied to the bonding pad 2S for an input signal, the electric charge is supplied to the ground potential. Bonding pad 2
It can be released to the G side, and the overvoltage and the like can be prevented from being directly applied to the semiconductor integrated circuit.

(2) Due to the above (1), it is possible to prevent the semiconductor integrated circuit device from being destroyed by static electricity during transportation thereof.

(3). By the above (1), it becomes possible to easily handle the semiconductor integrated circuit device during transportation and the like.

(4) During operation of the semiconductor integrated circuit device, when the power supply voltage is applied to the power supply voltage supply bonding pad, the signal bonding pad and the ground potential supply bonding pad are connected. The channel region of the first semiconductor region is depleted by the pn junction, and the conduction state between the signal bonding pad and the ground potential supply bonding pad can be cut off. It is possible to prevent the problem of degrading the characteristics.

(5) By the above (1) and (4), in a semiconductor integrated circuit device using the semiconductor substrate 3 made of a compound semiconductor, the electrostatic breakdown voltage can be improved without impairing the high frequency characteristics. Becomes That is, it becomes possible to improve the performance and reliability of the semiconductor integrated circuit device.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, in the above-described embodiment, the case where the p-type impurity Mg is used as the impurity in the extraction region in the lower layer of the input signal bonding pad and the ground potential supply bonding pad has been described, but the present invention is not limited to this. Instead, it can be variously changed, and may be, for example, p-type impurity carbon (C) or beryllium (Be). In addition, the impurity of the second semiconductor region is changed to the n-type impurity Si.
However, the present invention is not limited to this and can be variously changed, and for example, selenium (Se) which is an n-type impurity may be used.

Further, in the above-mentioned embodiment, the case where the first semiconductor region and the second semiconductor region are formed by the ion implantation method has been described, but the present invention is not limited to this and, for example, MOCVD (Metal Organic Chemic).
It can also be formed by an epitaxial method such as the al Vapor Deposition) method.

Further, although the case where the opening / closing portion of the channel region of the protection circuit is constituted by the pn junction has been described in the above embodiment, the present invention is not limited to this.
For example, it may be as shown in FIGS.

That is, the metal layer 9V1 is provided on the channel region 9a2 of the first semiconductor region 9a above the semiconductor substrate 3 so as to be in a Schottky contact state, and the metal layer 9V1 is provided.
And the bonding pad 2V for supplying the power supply potential 7
By electrically connecting through d, a reverse bias voltage is applied from the metal layer 9V1 to the channel region 9a2 side of the semiconductor integrated circuit device during operation,
A depletion layer may be formed in the channel region 9a2 immediately below the metal layer 9V1 to form an opening / closing portion.

Also in this case, it is possible to obtain the same effect as that of the above-mentioned embodiment. However, in this case, since the impurity introduction step for forming the second semiconductor region is not necessary, it is possible to reduce the manufacturing time and the cost.
The impurity in the first semiconductor region 9a is, for example, p-type impurity Mg, as in the above-described embodiment.

In the above embodiment, the case where the present invention is applied to the input protection circuit has been described, but it may be applied to the output protection circuit.

Further, in the above embodiment, the case where the present invention is applied to the semiconductor integrated circuit device in which only the MES • FET is shown on the semiconductor substrate has been described, but the present invention is not limited to this, and for example, a Schottky It can also be applied to a semiconductor integrated circuit device provided with another semiconductor integrated circuit element such as a barrier diode.

In the above description, the case where the invention made by the present inventor is mainly applied to the mobile communication LSI which is the background field of application has been described, but the invention is not limited to this and various applications are possible. For example, the present invention can be applied to other semiconductor integrated circuit devices such as a high-speed computer, a memory, a satellite device, a broadcast satellite device, a semiconductor integrated circuit device forming a radar or a microwave repeater, and the like.

[0058]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

According to the semiconductor integrated circuit device of the present invention described above, the following effects can be obtained.

That is, when the semiconductor integrated circuit device is not operating and the power supply voltage is not applied to the power supply voltage supply pad, the signal pad and the ground potential supply pad are electrically connected through the first semiconductor region. Therefore, at this time, even if an overvoltage or overcurrent due to static electricity is applied to the signal pad, the charge can be released to the ground potential supply pad side, and the overvoltage is directly applied to the internal circuit. It is possible to prevent this.

Further, when the semiconductor integrated circuit device is in operation, when the power supply voltage is applied to the power supply voltage supply pad, the channel portion of the first semiconductor region connecting the signal pad and the ground potential supply pad is connected. Is depleted by the opening / closing section, and the conduction state between the signal pad and the ground potential supply pad can be cut off, so that it is possible to prevent the problem that the protection circuit deteriorates the high frequency characteristics of the input signal. .

Therefore, in the semiconductor integrated circuit device using the compound semiconductor substrate, it is possible to improve the electrostatic breakdown voltage without impairing the high frequency characteristics. That is, the performance and reliability of the semiconductor integrated circuit device using the compound semiconductor substrate can be improved.

[Brief description of drawings]

FIG. 1 is an overall plan view of a semiconductor chip constituting a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a plan view of a main part of the semiconductor chip of FIG.

3 is a sectional view taken along line III-III in FIG.

FIG. 4 is a sectional view taken along line IV-IV in FIG.

FIG. 5 is an explanatory view schematically showing a cross section of a main part of a semiconductor integrated circuit device of this embodiment.

FIG. 6 is an explanatory view schematically showing a cross section of a main part of a semiconductor integrated circuit device of this embodiment.

FIG. 7 is a plan view of an essential part of a semiconductor chip constituting a semiconductor integrated circuit device which is another embodiment of the present invention.

8 is a cross-sectional view taken along the line VIII-VIII of FIG.

[Explanation of symbols]

1 Semiconductor Chip 2 Bonding Pad 2S Bonding Pad for Input Signal (Signal Pad) 2G Bonding Pad for Supplying Ground Potential (Pad for Grounding Potential) 2V Bonding Pad for Supplying Power Potential (Pad for Supplying Potential) 3 Semiconductor Substrate 4 MES • FET 4s Source region 4d Drain region 4c Channel region 4sp Source electrode 4dp Drain electrode 4g Gate electrode 5,5a-5c Insulation film 6a-6c Connection hole 7a-7d Wiring 8 Insulation film 9 Protection circuit 9a First semiconductor region 9a1 extraction region 9a2 channel region 9b second semiconductor region 9b1 extraction region 9b2 semiconductor region 9S, 9G, 9V, 9V1 metal layer 10 pn junction (opening / closing part) 11 depletion layer

Claims (4)

[Claims] 1. A signal pad, a power supply potential supply pad, and a ground potential supply pad are provided on a compound semiconductor substrate, and the signal pad and the ground potential supply pad are electrically connected. The first semiconductor region is provided on the compound semiconductor substrate and is electrically connected to the power supply potential supply pad, and when the power supply potential is supplied to the power supply potential supply pad, the signal pad and the ground potential supply are provided. A protective circuit for protecting a semiconductor integrated circuit formed on the compound semiconductor substrate is provided by providing an opening / closing portion for disconnecting a conduction state with the pad for use by depleting the first semiconductor region. Semiconductor integrated circuit device. 2. The second opening and closing part, wherein an impurity having a conductivity type opposite to that of the impurities in the first semiconductor region is introduced into the compound semiconductor substrate and is electrically connected to the power supply potential supply pad. 2. The semiconductor integrated circuit device according to claim 1, wherein one end of the semiconductor region is brought into contact with the first semiconductor region to form a pn junction. 3. The semiconductor integrated circuit device according to claim 1, wherein a p-type impurity is introduced into the first semiconductor region, and an n-type impurity is introduced into the second semiconductor region. . 4. The semiconductor integrated circuit device according to claim 3, wherein the compound semiconductor substrate is made of gallium arsenide, the p-type impurity is made of magnesium, and the n-type impurity is made of silicon.