JPH08228145A - Low voltage soi type logic circuit - Google Patents

Abstract

PURPOSE: To enable the high-speed operation of the logic circuit by using an MOSFET of a low threshold voltage and to reduce power consumption at the time of waiting by using the MOSFET for power source switch of a high threshold voltage. CONSTITUTION: The SOI type logic circuit is provided while serially connecting SOI type MOSFET 44 and 45 for power source switch and a logic circuit 43 composed of the SOI type MOSFET. The body part of the MOSFET of the logic circuit is turned to a floating state and defined as the MOSFET of the low threshold voltage and the body part of the MOSFET for power source switch is biased by a power source voltage and defined as the MOSFET of the high threshold voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low voltage SOI type logic circuit using an SOI (Silicon On Insulator) type field effect transistor operable with a 1V dry battery power source.

[0002]

2. Description of the Related Art As a conventional low voltage logic circuit, a circuit as shown in FIG. 1 is known. This is a bulk type CM
An OS circuit is used, which is disclosed in JP-A-6-29834 or S. Mutoh, et al. "1V HIGH SPEED DIGITAL".
CIRCUIT TECHNOLOGY WITH 0.5 μm MULTI-THRESHOLD CM
OS ", IEEE, 1993, pages 186-189.

This circuit has a CM between a power switch MOSFET 4 connected to the high potential power line 1 and a power switch MOSFET 5 connected to the low potential power line 2.
It has a basic configuration in which the OS logic circuit group 3 is connected. Here, the power switch MOSFETs 4 and 5 are high threshold voltage MOSFETs, and the logic circuit group 3 is composed of low threshold voltage MOSFETs.

High threshold voltage power switch MOSF
A sleep signal SL and its inverted signal * SL are supplied to the gates of ET4 and ET5, respectively, and during standby (sleep) of the logic circuit group 3, the signal SL is set to a high level and the MOSFETs 4 and 5 are turned off. And logic circuit group 3
To stop the power supply to. On the contrary, during the operation of the logic circuit group 3, the sleep signal SL is set to the low level and the MOSFE
T4 and 5 are turned on to supply power to the logic circuit group 3.

Generally, a low threshold voltage MOSFET
Has a characteristic that the operating speed is high but the leakage current at the time of interruption is large, and conversely, the MOSFET with a high threshold voltage has a characteristic that the operating speed is slow but the leakage current at the time of interruption is small.
Therefore, the circuit in FIG. 1 can maintain a small leak current in the sleep state and can continue high-speed operation in the operation of the logic circuit group 3.

It should be noted that, in the conventional low voltage logic circuit, each substrate of the MOSFETs of the logic circuit group 3 is connected to the high potential power supply line 1 or the low potential power supply line 2, respectively. . This is to prevent malfunction due to latch-up that is likely to occur in a bulk type CMOS circuit by applying a substrate bias. In addition, in Fig. 1 of the above-mentioned article by Mutoh, et al.
It is written as if the substrate of the OSFET is not connected anywhere, but this is for convenience of notation,
In reality, the substrates of these MOSFETs are also connected to their respective power lines.

When such a structure is applied to an SOI type CMOS logic circuit, there is a problem that the element area increases. Hereinafter, this point will be described.

FIG. 2 is a sectional view showing the structure of a conventional SOI MOSFET. A buried oxide film 12 is formed on a silicon substrate 11, and an active region 13 made of a single crystal silicon layer is formed on the buried oxide film 12. The active region 13 includes a source 131, a drain 132, and a body portion 133 sandwiched between them. The active region 13 is covered with a gate oxide film 14, and a gate electrode 15 is formed on the gate oxide film 14. By applying a voltage to the gate electrode 15, the channel part 134 is formed on the body part 133.
As described above, the active region 13 is composed of the source 131, the drain 132, and the body portion 133, and the body portion 133 is formed by the buried oxide film 12 in the silicon substrate 1.
Insulated from 1.

FIG. 3A shows a method of applying a bias to the substrate of the bulk MOSFET, and FIG. 3B shows SO.
A method of applying a bias to the body of the I-type MOSFET will be described. In the bulk type PMOSFET shown in FIG.
An N type well 20 is formed in the substrate, a P ⁺ type source 21 and a drain 22 are formed therein, and a gate electrode 23 is formed on the upper surface of the well 20 via a gate oxide film. In addition, a bias N ⁺ region 24 is formed in the well 20 so that a potential can be applied from above the silicon through the contact 25.

On the other hand, the SOI type PMOS shown in FIG.
As shown in FIG. 2, the FET has a structure in which the body portion 133 is insulated from the silicon substrate 11, and therefore the body portion 133 is connected to the bias region 34 by the connection portion 34A, and the contact 35 is formed therein. I had to.

As a result, the SOI type MOSFET has a drawback that the bias region is increased and the occupied area is increased by that amount as compared with the bulk type MOSFET. In particular, there is a problem that an increase in the size of the MOSFETs forming the logic circuit group 3 causes an increase in the circuit area and a reduction in the degree of integration.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to provide a low voltage SOI type logic circuit capable of high speed operation and high integration.

[0013]

According to the present invention, there is provided an SOI (Silicon On In) having a first power supply line, a second power supply line, a source and a body portion connected to the first power supply line.
a first field effect transistor of a
SO in which the source and body are connected to the second power line
An I-type second field effect transistor, and a logic circuit connected between the drain of the first field effect transistor and the drain of the second field effect transistor, wherein the logic circuit is an SOI. Type field effect transistor, the body of the SOI type field effect transistor is set in a floating state, and the first field effect transistor and the gate of the second field effect transistor are supplied with a signal by the signal supplied to the gate of the first field effect transistor. One of the power supply lines and the logic circuit, and the second power supply line and the logic circuit are turned on / off.

Further, according to the present invention, a first electric field of SOI type in which a first power supply line, a second power supply line and a source are connected to the first power supply line and a body portion is connected to a gate. An effect transistor and a source connected to the second power line,
An SOI-type second field effect transistor having a body connected to the gate, and a logic circuit connected between the drain of the first field effect transistor and the drain of the second field effect transistor. The logic circuit is composed of an SOI type field effect transistor, and
The body portion of the OI type field effect transistor is set in a floating state, and the first power supply line and the logic circuit are controlled by a signal supplied to the gate of the first field effect transistor and the gate of the second field effect transistor. And, the connection between the second power supply line and the logic circuit is turned on / off.

Further, according to the present invention, the impurity concentration of the body portion of the field effect transistor forming the logic circuit is adjusted so that the body portion is completely depleted, and the body of the first field effect transistor is formed. Part and said second
The impurity concentration of the body portion of the field effect transistor is adjusted so that the body portion is partially depleted.

Further, according to the present invention, the impurity concentration of the body portion of the field effect transistor constituting the logic circuit is adjusted, and the thickness of the depletion layer formed in the body portion is given by the following formula. Width W or more, the first
Adjusting the impurity concentration of the body part of the field effect transistor and the body part of the second field effect transistor,
It is characterized in that the thickness of the depletion layer formed in the body portion is set to be smaller than the depletion layer width W.

[0017]

[Equation 3] W = {2ε _si · 2φ _f / (q · N _body )} ^1/2 where ε _si is the dielectric constant φ _f of the silicon part, the Fermi potential q of the silicon part is the electron charge N _In the present invention, the body portion of the field effect transistor constituting the logic circuit has a thickness of 100 nm or less and an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less. Are completely depleted, and the thickness of the body of the first field effect transistor and the body of the second field effect transistor is 100 nm or less, and the impurity concentration thereof is larger than 1 × 10 ¹⁷ cm ^−3. Is set so that the body portion is in a partially depleted state.

According to the present invention, there is further provided a first power supply line, a second power supply line, an SOI type power switch field effect transistor whose source and body are connected to the first power supply line, and A logic circuit connected between the drain of the field effect transistor for power switch and the second power line, wherein the logic circuit is composed of an SOI type field effect transistor, The body portion is set in a floating state, and the connection between the first power supply line and the logic circuit is turned on / off by a signal supplied to the gate of the power switch field effect transistor.

Further, according to the present invention, an electric field for an SOI type power switch in which a first power supply line, a second power supply line and a source are connected to the first power supply line and a body is connected to a gate. An effect transistor and a logic circuit connected between the drain of the power switch field effect transistor and the second power line are provided, and the logic circuit is composed of an SOI type field effect transistor. Type body field effect transistor body is in a floating state,
The connection between the first power supply line and the logic circuit is turned on / off by a signal supplied to the gate of the power switch field effect transistor.

Further, according to the present invention, the impurity concentration of the body portion of the field effect transistor forming the logic circuit is adjusted so that the body portion is completely depleted, and the body of the power switch field effect transistor is formed. The impurity concentration of the body portion is adjusted so that the body portion is partially depleted.

Further, according to the present invention, the impurity concentration of the body portion of the field effect transistor constituting the logic circuit is adjusted, and the thickness of the depletion layer formed in the body portion is given by the following formula. The width of the depletion layer formed in the body is adjusted by adjusting the impurity concentration of the body of the power switch field effect transistor so that the width is not less than W.
It is characterized in that the width is set to be smaller than the depletion layer width W.

[0022]

[Equation 4] W = {2ε _si · 2φ _f / (q · N _body )} ^1/2 where ε _si is the dielectric constant φ _f of the silicon part, the Fermi potential q of the silicon part is the electron charge N _In the present invention, the body portion of the field effect transistor constituting the logic circuit has a thickness of 100 nm or less and an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less. Is completely depleted, and the thickness of the body of the field effect transistor for power switch is set to 100 nm or less and the impurity concentration thereof is set to more than 1 × 10 ¹⁷ cm ⁻³ to partially deplete the body. It is characterized in that it is in an activated state.

[0023]

The present invention is an SOI type MOSFET for a logic circuit.
The feature is that the body part of is set in a floating state. As a result, in the MOSFET forming the logic circuit, the bias region and the connecting portion, which have been conventionally required, are unnecessary, and the increase of the element area can be prevented.
Also, the NMOSF with the body part in a floating state
In ET (PMOSFET), holes (electrons) flow from the drain to the body (impact ionization), the potential of the body rises (falls), and the absolute value of the voltage between the body and the source increases. Therefore, there is an advantage that the threshold voltage is lowered and the voltage of the logic circuit element can be lowered.

In the power switch MOSFET,
A bias region and connection are required to achieve a high threshold voltage, but this MOSFET only needs to be placed on both sides (or one side) of the logic circuit block. Since the number of devices used is extremely small, the effect on the area of the entire circuit can be ignored.

Further, the threshold voltage can be set accurately by adjusting the impurity concentration of the body portion of the MOSFET. That is, in the low threshold voltage MOSFET for the logic circuit, the low threshold voltage can be realized with high accuracy by reducing the impurity concentration of the body part in the floating state to bring it into the fully depleted state. Along with MOSFET for power switch
Then, by increasing the impurity concentration of the body part biased to the power supply and making the body part partially depleted,
The high threshold voltage can be set accurately.

If the body portion of the power switch MOSFET is connected to the gate and biased by the gate voltage, the threshold voltage characteristic of this MOSFET has a high threshold voltage when cut off and a low threshold voltage when turned on. The voltage can be switched automatically. That is, more advantageous power supply control can be realized by the variable threshold voltage.

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 4 is a circuit diagram showing a configuration of a first embodiment of a low voltage SOI type logic circuit according to the present invention.

In the figure, reference numeral 41 is a high potential power supply line, 4
Reference numeral 2 is a low potential power line. The high-potential power line 41 is connected to the source terminal of the power switch PMOSFET 44,
The low-potential power supply line 42 is a power switch NMOSFET 4
5 is connected to the source terminal. Also, MOSF
The drain terminal of the ET 44 is connected to the high potential terminal of the logic circuit group 43, and the drain terminal of the MOSFET 45 is connected to the low potential terminal of the logic circuit group 43. In other words, the MOSFET 44, the logic circuit group 43 and the MOS
FET 45 is connected in series and MOSFETs 44 and 4 are connected.
Power is supplied to the logic circuit group 43 via the circuit 5. The sleep signal SL is applied to the gate terminal of the MOSFET 44, and its inverted signal * SL is applied to the gate terminal of the MOSFET 45. These signals are supplied to the power switch MOSFET 44.
And 45 for on / off control, turning off the MOSFETs 44 and 45 when the logic circuit group 43 is in a sleep state, and turning off the MOSF when the logic circuit group 43 is operating.
Turn on ETs 44 and 45.

The feature of this embodiment is that the body portions of all MOSFETs forming the logic circuit group 43 are set in a floating state. That is, the body portions of these MOSFETs are not biased. On the other hand, the body portions of the power switch MOSFETs 44 and 45 are biased. That is, M
The body portion of the OSFET 44 is connected to the high potential power source line 41, and the body portion of the MOSFET 45 is connected to the low potential power source line 42.

FIGS. 5A and 5B show MOSF.
9 is a graph showing changes in threshold voltage when the ET body is biased and when it is not biased. The horizontal axis represents the gate-source voltage V _GS , and the vertical axis represents the drain current I _DS on a logarithmic scale. V _TH1 and V
_TH2 is a threshold voltage. As is clear from the figure,
When the body is not biased, the threshold voltage drops. The reason for this is described above. in this way,
In the SOI type MOSFET, a high threshold voltage MOSFET and a low threshold voltage MOSFET are selected depending on whether or not the body portion is biased without using a special threshold voltage adjustment mask in the manufacturing process. MOSFE
T and can be realized.

In this embodiment, further, the threshold voltage is adjusted with high accuracy by controlling the impurity concentration of the body portion. Hereinafter, this point will be described in detail.

FIG. 6A shows a MOSF for the logic circuit group 43.
FIG. 6B is a cross-sectional view showing the structure of ET, and FIG. 6B is a cross-sectional view showing the structure of power switch MOSFETs 44 and 45. As can be seen from these figures, the logic circuit group 4
In the body portion 133A of the third MOSFET, the depletion layer width W is set to be equal to or larger than the thickness of the body portion. That is,
The body portion 133A is in a completely depleted state. On the other hand, the body portion 133B of the power switch MOSFET
Has a depletion layer width W smaller than the thickness of the body portion. That is, the body portion 133B is in a partially depleted state. Generally, as the width of the depletion layer is larger, the channel is formed at a lower voltage, and thus the threshold voltage is lowered. Therefore, the threshold voltage of the logic circuit group MOSFET is set to a desired low threshold voltage with high accuracy, and the threshold voltage of the power switch MOSFET is set to a high threshold voltage with high accuracy. It

The MO shown in FIGS. 6A and 6B.
In the SFET, the depletion layer width W is given by the following equation.

[0035]

W = {2ε _si · 2φ _f / (q · N _body )} ^1/2 (1) where ε _si is the dielectric constant of silicon, φ _f is the Fermi potential of silicon, and q is the charge amount N of electrons. _body is the impurity concentration of the body part. Further, the Fermi potential φ _f is given by the following equation.

[0036]

Φ _f = (kT / q) ln (N _body / n _i ) (2) where k is Boltzmann's constant T is the absolute temperature of the body part n _i is the intrinsic carrier density of silicon. In addition, ln represents a natural logarithm.

The thickness of the active region 13 is t _SOI ,
When the depletion layer width W is made larger than this film thickness t _SOI ,
133 A of body parts will be in a completely depleted state. In this state, it is known that the mutual conductance g _m of the MOSFET increases, the gate capacitance decreases, and the operating speed of the MOSFET improves.

On the other hand, the threshold voltage V of the MOSFET
_TH is given by the following approximate expression.

[0039]

[Formula 7] V _TH ≈ V _FB + 2φ _f + (2ε _si · 2φ _f · q · nN _body ) ^1/2 / C _OX (3) where V _FB is the flat band voltage C _OX is the capacitance due to the gate oxide film 14. Is.

From the equations (1)-(3), M for the logic circuit is obtained.
In order to completely deplete the body portion 133A of the OSFET, the thickness t _SOI of the active region 13 is set to 100 n.
m, the thickness t _OX of the gate oxide film 14 is 7 nm (C _OX = 0.49 μF / cm ^{2 due to this} ), and the impurity concentration N _body of the _body 133A is 8 × 10 ¹⁶ cm ⁻³ (where V _FB = −
0.9V and 2φ _f = + 0.8V). The threshold voltage at this time is 0.2 V as shown in FIG.
It is possible to realize a low threshold voltage MOSFET. As can be seen from FIG. 7, the threshold voltage is lowered by decreasing the impurity concentration and increasing the depletion layer width.

In this way, the fully depleted state of the body portion 133A of the logic circuit MOSFET can be realized, but when the film thickness t _SOI of the active region 13 is 100 nm, the impurity concentration N _body is 1 × 10 ¹⁷ cm ^-3 or less. Is preferred.

On the other hand, in the power switch MOSFETs 44 and 45 in which the body portion 133B is biased, the body portion 133B is partially depleted. For example, the impurity concentration N _body of the body portion 133B is set to 4 × 10 ¹⁷ cm ^−3.
When set to, the depletion layer thickness W = 54 nm, as shown in FIG.
As shown in (B), the body portion 133B can be partially depleted. At this time, V _FB = −1.0V,
Since 2φ _f = + 0.9V, a high threshold voltage MOSFET having a threshold voltage of about 0.6V can be realized. The thickness t _SOI of the active region 13 and the thickness t _OX of the gate oxide film 14 are set to be the same as those of the logic circuit MOSFET. The impurity concentration N _body of the body portion 133B is preferably 1 × 10 ¹⁷ cm ⁻³ or more.

Thus, the power switch MOSFET 4
The body portions 133B of Nos. 4 and 45 are partially depleted. The partially depleted body portion 133B has a high potential power supply line 41 and a low potential power supply line 42 via a bias region.
Respectively connected to. Therefore, the fluctuation of the threshold voltage can be made as small as that of the conventional bulk MOSFET. As a result, it is possible to reduce variations in the on-resistances of the power switch MOSFETs 44 and 45, and the logic circuit group 4
It is possible to supply a stable power supply voltage to 3.

Second Embodiment FIG. 8 is a circuit diagram showing a structure of a second embodiment of a low voltage SOI type logic circuit according to the present invention.

This embodiment is different from the first embodiment in that the body portion 1 of the power switch MOSFETs 44 and 45 is different.
33B is connected to the gate electrode 15.

According to this structure, when the logic circuit circuit group 43 is in the sleep state, the threshold voltages of the MOSFETs 44 and 45 are increased to reduce the leak current.
Lower the threshold voltage of MOSFETs 44 and 45,
The supply voltage to the logic circuit group 43 can be increased.

FIGS. 9A and 9B are graphs for explaining the reason. In these graphs, the horizontal axis represents the gate-source voltage V _GS , and the vertical axis represents the threshold voltage V _TH . As you can see from these figures,
If the absolute value of the gate-source voltage V _GS increases, the MO
The absolute value of the threshold voltage V _TH of the SFET decreases. The second embodiment utilizes this characteristic.

First, during sleep, the PMOSFET 4
A high level signal SL (1V) is supplied to the gate of 4.
A low level signal * SL (0
V) is added. At this time, the voltage V _GS also between the gate and the source of PMOSFET44, the voltage V _GS between the gate and the source of NMOSFET45, a low voltage (0V). That is, the threshold voltage V _TH becomes high.

On the contrary, when the logic circuit group 43 is operating, PM
Low level signal SL (0V) is applied to the gate of OSFET44
Is supplied, and a high level signal * SL (1V) is applied to the gate of the NMOSFET 45. At this time, PMOSF
The gate-source voltage V _GS of ET44 is also NMOSFE
Gate-source voltage V _{GS of} T45 is also high voltage (1V)
Becomes That is, the threshold voltage V _TH becomes low.

As a result, during sleep, the MOSFET is
The off resistances of 44 and 45 increase, the leak current can be suppressed to a low value, and the on resistances of the MOSFETs 44 and 45 decrease when the logic circuit group 43 operates.
The supply voltage to the logic circuit group 43 can be increased.

In each of the above embodiments, the power switch MOSFET is provided on both the high potential side and the low potential side.
Even if only one of them is used, almost the same operational effect can be obtained. For example, when the low potential side MOSFET 45 is excluded, the low potential terminal of the logic circuit group 43 may be directly connected to the low potential power supply line 42.

FIG. 10 shows a MOSFE which constitutes a logic circuit.
This is a prior art showing a structure in which the body part of T is connected to a gate electrode. T. Andoh, et al., "Design Methodology for
Low-Voltage MOSFETs ", 1994, IEEE, pages 79-82. This embodiment differs from this prior art in that the body portion is connected to the gate electrode.
In the prior art, the MOSFET is used as a logic circuit MOSFET, whereas in the present invention, a power switch MOS is used.
It is used as an FET. In the MOSFET in which the body portion is connected to the gate electrode, since the connection portion from the body portion to the gate electrode must be provided, the element occupying area increases and the input capacitance increases, so the body portion is set to the floating state. The operation speed is slower than that of the element, and it is not suitable for a logic circuit. In the present embodiment, such a MOSFET is used as a power supply switching element which has a slower operating speed than a logic element and is used in a small number. Therefore, such a defect can be avoided.

[0053]

As described above, according to the present invention,
It is possible to provide a low-voltage SOI type logic circuit capable of high-speed operation and high integration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional low voltage CMOS logic circuit.

FIG. 2 is a sectional view showing a general structure of an SOI MOSFET.

FIG. 3A is a plan view showing a substrate bias structure of a conventional bulk MOSFET, and FIG. 3B is a conventional SOI type MO.
It is a top view which shows the body part bias structure of SFET.

FIG. 4 is a circuit diagram showing a configuration of a first embodiment of a low voltage SOI type logic circuit according to the present invention.

FIG. 5A shows a MOSFET in the first embodiment.
(B) is a graph showing the source-gate voltage-drain current characteristics and the threshold voltage when the body part of the MOSFET is biased, (B) shows the case where the body part of the MOSFET is not biased in the first embodiment. 3 is a graph showing a source-gate voltage-drain current characteristic and a threshold voltage.

FIG. 6A is a cross-sectional view showing the structure of a low threshold voltage SOI type MOSFET for a logic circuit used in the first embodiment;
FIG. 3B is a sectional view showing the structure of a high threshold voltage SOI type MOSFET for a power switch used in the first embodiment.

FIG. 7 is a graph showing the relationship between the impurity concentration of the body portion and the threshold voltage.

FIG. 8 is a circuit diagram showing a configuration of a second embodiment of a low voltage SOI type logic circuit according to the present invention.

9A is a graph showing a source-gate voltage-threshold voltage characteristic when the body of an NMOSFET is connected to a gate electrode, and FIG. 9B is when the body of a PMOSFET is connected to a gate electrode. 3 is a graph showing the source-gate voltage-threshold voltage characteristic of FIG.

FIG. 10 is a diagram showing a conventional circuit having a configuration partially similar to that of the second embodiment.

[Explanation of symbols]

 1 High-potential power line 2 Low-potential power line 3 Logic circuit group 4 Power switch MOSFET 5 Power switch MOSFET 11 Silicon substrate 12 Buried oxide film 13 Active region 14 Gate oxide film 15 Gate electrode 41 High potential power line 42 Low potential Power line 43 Logic circuit group 44 Power switch MOSFET 45 Power switch MOSFET 131 Source 132 Drain 133 Body part 133A Body part 133B Body part 134 Channel part

Claims (10)

[Claims] 1. An SOI having a first power supply line, a second power supply line, a source and a body portion connected to the first power supply line.
(Silicon On Insulator) type first
Field effect transistor, and an SO having a source and a body connected to the second power line.
An I-type second field effect transistor, a drain of the first field effect transistor and the second
And a logic circuit connected to the drain of the field effect transistor of, wherein the logic circuit is composed of an SOI type field effect transistor, and a body portion of the SOI type field effect transistor is set in a floating state. Between the first power supply line and the logic circuit and between the second power supply line and the logic circuit according to a signal supplied to the gate of the first field effect transistor and the gate of the second field effect transistor. Low voltage SO characterized by turning on / off the connection
Type I logic circuit. 2. An SOI-type first field effect transistor having a first power supply line, a second power supply line, a source connected to the first power supply line, and a body connected to a gate. A second SOI-type field effect transistor having a source connected to the second power supply line and a body connected to a gate; a drain of the first field effect transistor;
And a logic circuit connected to the drain of the field effect transistor of, wherein the logic circuit is composed of an SOI type field effect transistor, and a body portion of the SOI type field effect transistor is set in a floating state. Between the first power supply line and the logic circuit and between the second power supply line and the logic circuit according to a signal supplied to the gate of the first field effect transistor and the gate of the second field effect transistor. Low voltage SO characterized by turning on / off the connection
Type I logic circuit. 3. The body portion of the field effect transistor forming the logic circuit is adjusted in impurity concentration to bring the body portion into a fully depleted state, and the body portion of the first field effect transistor and the first field effect transistor. 3. The low voltage SOI type logic circuit according to claim 1, wherein the body portion of the field effect transistor of No. 2 is adjusted in impurity concentration to make the body portion partially depleted. 4. The impurity concentration of the body portion of the field effect transistor forming the logic circuit is adjusted so that the thickness of the depletion layer formed in the body portion is not less than the depletion layer width W given by the following equation. And adjusting the impurity concentrations of the body portion of the first field effect transistor and the body portion of the second field effect transistor so that the thickness of the depletion layer formed in the body portion is the depletion layer width. 3. The low voltage SOI type logic circuit according to claim 1, wherein the low voltage SOI type logic circuit is set to be smaller than W. ## EQU1 ## W = {2ε _si · 2φ _f / (q · N _body )} ^1/2 where ε _si is the dielectric constant φ _f of the silicon part, the Fermi potential q of the silicon part is the electron charge N _body is the impurity concentration of the body part 5. The body portion of the field effect transistor constituting the logic circuit has a thickness of 100 nm or less and an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less to make the body portion completely depleted and The thickness of the body portion of the first field effect transistor and the body portion of the second field effect transistor is set to 100 nm or less, and the impurity concentration thereof is set to be larger than 1 × 10 ¹⁷ cm ⁻³ , and the body portion is The low voltage SOI type logic circuit according to claim 4, wherein the low voltage SOI type logic circuit is in a partially depleted state. 6. An SO having a first power supply line, a second power supply line, a source and a body portion connected to the first power supply line.
An I-type power switch field effect transistor, and a logic circuit connected between the drain of the power switch field effect transistor and the second power line, wherein the logic circuit is an SOI field effect transistor. Connection between the first power supply line and the logic circuit by a signal supplied to the gate of the power switch field effect transistor, the body part of the SOI type field effect transistor being in a floating state. A low-voltage SOI type logic circuit for turning on / off the switch. 7. A field effect transistor for an SOI type power switch, wherein a first power supply line, a second power supply line, a source is connected to the first power supply line, and a body is connected to a gate. A logic circuit connected between the drain of the power switch field effect transistor and the second power supply line, wherein the logic circuit is composed of an SOI field effect transistor; And a connection between the first power supply line and the logic circuit is turned on / off by a signal supplied to the gate of the power switch field effect transistor. Voltage SOI type logic circuit. 8. The impurity concentration of the body portion of the field effect transistor forming the logic circuit is adjusted so that the body portion is completely depleted, and the impurity concentration of the body portion of the power switch field effect transistor is adjusted. 8. The low voltage SOI type logic circuit according to claim 6, wherein the body portion is adjusted to a partially depleted state. 9. The impurity concentration of the body portion of the field effect transistor constituting the logic circuit is adjusted so that the thickness of the depletion layer formed in the body portion is not less than the depletion layer width W given by the following equation. And the impurity concentration of the body portion of the power switch field effect transistor is adjusted so that the thickness of the depletion layer formed in the body portion is smaller than the depletion layer width W. Claim 6
Alternatively, the low-voltage SOI type logic circuit described in 7. ## EQU2 ## W = {2ε _si · 2φ _f / (q · N _body )} ^1/2 where ε _si is the dielectric constant φ _f of the silicon part, the Fermi potential q of the silicon part is the electron charge N _body is the impurity concentration of the body part 10. A body portion of a field effect transistor constituting the logic circuit has a thickness of 100 nm or less and an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or less to make the body portion completely depleted. The body portion of the power switch field effect transistor has a thickness of 100 nm or less, and an impurity concentration thereof is set to be larger than 1 × 10 ¹⁷ cm ⁻³ to make the body portion partially depleted. The low-voltage SOI type logic circuit according to claim 9.