JPH0822695A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a non-volatile semiconductor memory device which can be operated with a constant voltage of about 2V. CONSTITUTION:A memory cell consists of a memory transistor and a selective gate transistor and is connected to a sense-amplifier with NAND constitution. This memory TR is obtd. by forming a floating gate electrode 24 via a gate insulating film on a channel region between diffusion regions 20 and 22 for a source and drain. Further, a control gate electrode 26 is formed via an insulating film thereon. The threshold voltage viewed from the control gate electrode 26 is so set as to attain negative, for example, -1.0V by implanting ions to the channel region under the floating gate electrode 24. The selective gate TR is obtd. by forming a selective gate electrode 30 of a polysilicon via a gate insulating film on the channel region between the diffusion region 20 and the diffusion region 28 of the extension part connecting to the sense-amplifier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device including a FAMOS type memory transistor having a floating gate electrode or a mask ROM memory transistor in a memory cell.

[0002]

2. Description of the Related Art FIG. 1A shows a FAMOS memory transistor, which has a floating gate made of polysilicon via a gate insulating film on a channel region between a drain 2 and a source 4 formed of a diffusion layer formed on a semiconductor substrate. Electrode 6
Is formed, and a control gate electrode 8 made of polysilicon is formed thereon via an insulating film. initial state,
That is, the threshold voltage in one memory state is +1.5 to 2V measured from the control gate electrode 8, and the threshold voltage is increased in the other memory state in which electrons are injected into the floating gate electrode 6. It goes up to + 5-6V. Therefore, at the time of reading, the control gate electrode 8
Must be set to a voltage at which one memory state memory transistor is turned on and the other memory state memory transistor is not turned on. For example, at a power supply voltage of 2 V, one memory state The memory transistor also cannot be turned on and cannot be used. That is, this memory transistor cannot be operated at a voltage as low as 2 V or less.

For high integration, an EEPROM has been proposed in which the threshold voltage of one memory state of a FAMOS memory transistor is set negative (US Pat. No. 4,933).
9690 publication). Here, as shown in FIG. 1B, a NAND type array in which a plurality of memory transistors 10 are connected in series to a sense amplifier is adopted. Reference numeral 12 is a diffusion region connected to the sense amplifier, 14 is a source diffusion region, and select gate electrodes 16 and 18 are provided at both ends of the array of the memory transistors 10 to select the NAND memory cell array. .

L for memory used in a microcomputer
In SI, after debugging with EPROM, mask ROM is often redesigned for mass production. In this case, the EPROM and the mask ROM have different current capacities due to the difference in the structure of the memory transistors, and they cannot be equivalent in terms of speed, which causes a problem that the timing must be redesigned. In addition, since the sense amplifier normally has a static circuit configuration, even if the sense amplifier is configured to have a CMOS configuration, a current flows through the CMOS circuit when the address signal is switched, resulting in a large power consumption.

[0005]

SUMMARY OF THE INVENTION A first object of the present invention is to provide a low voltage non-volatile semiconductor memory device having a memory transistor which can be operated even at a low voltage of about 2V. In that case, FIG. 1 (B)
In such a NAND type memory cell array, in order to select one of the vertically arranged memory cells of the NAND array, the memory cells in the middle must be turned on by the power supply voltage applied to each control gate electrode. Therefore, precise threshold voltage control is required. However, such control is not easy. Therefore, there is a problem in yield and a problem that speed cannot be compensated.

A second object of the present invention is EPROM or EEP.
It is possible to replace a circuit debugged by a ROM with a mask ROM having the same characteristics and enable development in a short period of time. A third object of the present invention is to realize low power consumption also in a word line drive circuit and a sense amplifier.

[0007]

A memory cell included in a nonvolatile semiconductor memory device of the present invention which enables a memory transistor to operate at a low voltage is realized as a two-transistor type or a one-transistor type. The two-transistor type memory cell includes a memory transistor and a select gate transistor inserted between the memory transistor and the sense amplifier. A memory transistor has a floating gate electrode formed on a channel region of a semiconductor substrate via a gate insulating film, and a control gate electrode formed on the floating gate electrode via an insulating film, and a threshold voltage measured from the control gate electrode. A gate electrode is formed on the channel region of the semiconductor substrate, or a memory transistor whose threshold voltage is set so as to be negative in one memory state and positive in the other memory state, via a gate insulating film, In the memory transistor, the threshold voltage is set so that the threshold voltage is negative in one memory state and positive in the other memory state.

This memory cell is connected in parallel to a sense amplifier so that a block including a plurality of memory cells is selected by a first selection signal, and a plurality of memory cells are sensed in parallel in each block. The NOR circuit is configured by being connected to the amplifier and being commonly supplied with the second selection signal to the selection gate transistors of the memory cells in the same block.

According to the one-transistor type memory cell of the present invention which enables a memory transistor to operate at a low voltage, a floating gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film, and further an insulating film is interposed on the floating gate electrode. A memory transistor or semiconductor in which a control gate electrode is formed and the threshold voltage measured from the control gate electrode is set to be negative in one memory state and positive in the other memory state. A memory transistor in which a gate electrode is formed on a channel region of a substrate via a gate insulating film, and the threshold voltage is set to be negative in one memory state and positive in the other memory state. The word line drive circuit including only the control gate electrode or the gate electrode of the memory cell Also the memory transistor of one of the storage state at the time of non-selection of Le and a negative voltage generating circuit for supplying a negative voltage which does not turn on. EEPROM, EPRO
In the M and the mask ROM as well, in order to make the threshold voltage negative, the threshold voltage can be adjusted by performing ion implantation in the channel region.

In order to realize low power consumption in the word line drive circuit and the sense amplifier, at least one of the word line drive circuit and the sense amplifier has a CMOS structure in the present invention, and the switching point of the address signal is detected to detect the change. A clock operation type that has an address switching detection circuit that generates a pulse signal corresponding to the switching time, and disables word line drive and sense amplifier operation during the period when the output pulse signal of the address switching detection circuit is generated. It has a drive circuit.

[0011]

The threshold voltage of the FAMOS memory transistor in one memory state or the threshold voltage of the mask ROM memory transistor in one memory state is negative, for example -1.0.
If the voltage is set to about V, even if the voltage applied to the control gate electrode or the gate electrode is 0V, an on-current flows through those memory transistors. Since the threshold voltage is positive in the other storage state of the FAMOS memory transistor or the other storage state of the mask ROM memory transistor, when the voltage applied to the control gate electrode or the gate electrode is 0 V, those memory transistors are Does not flow on current. Therefore, the memory transistor can be read even if the control gate voltage or the gate voltage is 0V. As described above, operation is possible even at a low voltage of 2 V or less, and a high voltage such as 5 V is used to turn on the FAMOS in one memory state or turn on the mask ROM in one memory state as in the conventional case. No need to apply.

On the other hand, since the ON current flows through the FAMOS memory transistor in one memory state or the mask ROM memory transistor in one memory state even if the control gate voltage or the gate voltage is 0 V, the select gate transistor is turned off when it is not selected. This prevents the sense amplifier from reading by mistake.

In the FAMOS memory cell and the mask ROM memory cell, the potential applied to the control gate electrode or the gate electrode of the memory transistor at the time of reading is 0 V, and the potential environment can be the same in both, and as a result, the FAMOS memory cell It is possible to realize a mask ROM having the same timing characteristics as the above. Therefore, there is no need to redesign the timing on both sides as in the conventional case. CM for address line drive circuit and sense amplifier
By having an OS configuration and a clock operation type,
It is possible to prevent a through current from flowing through the CMOS circuit when the address signal is switched, and it is possible to further reduce power consumption.

[0014]

DETAILED DESCRIPTION FIG. 2 shows a memory cell of one embodiment. FIG. 2A is an example of a nonvolatile memory cell for a microcomputer, in which a memory transistor is formed on a semiconductor substrate through a gate insulating film on a channel region between source / drain diffusion regions 20 and 22. The floating gate electrode 24 thus formed and the control gate electrode 26 formed on the floating gate electrode 24 with an insulating film interposed therebetween are provided. This memory transistor is set such that the channel region under the floating gate electrode 24 is ion-implanted and the threshold voltage seen from the control gate electrode 26 is negative, for example, -1.0V.

Further, in order to make it electrically erasable, at least a part of the gate insulating film of the memory transistor is a thin gate insulating film capable of tunneling (tunnel insulating film).
Has become. Further, in this memory cell, a polysilicon select gate electrode 30 is formed as a select gate transistor on the channel region between the diffusion region 20 and the diffusion region 28 connected to the sense amplifier via a gate insulating film.

FIG. 2B shows a mask ROM memory cell having the same characteristics as FIG. 2A. The memory transistor is formed on the diffusion regions 20 and 22 for source / drain through a gate insulating film and polysilicon. The gate electrode 32 is formed, and the threshold voltage is negative in the initial state, for example, −
Ion implantation is set in the channel region so as to be 1.0 V. The gate electrode 32 is used while being fixed to the ground potential. Also in this memory cell, a select gate transistor is formed by the select gate electrode 30.

The operation of the memory cell of FIG. 2A will be described with reference to FIG. (A) Programming "0" Apply 8V to the drain 28 and set 1 to the select gate electrode 30.
Apply 2.0V to select this memory cell, source 2
2 is set to 0 V, and the control gate electrode 26 has 12.
Apply 0V. At this time, drain 28 to source 2
A current flows through the memory transistor 2, and electrons are injected into the floating gate electrode 24 by the avalanche operation in the memory transistor to program "0".

(B) Programming "1" The drain 28 is brought into a floating state. Others are the same as (A), but the floating gate electrode 24
No electrons are injected into.

(C) Erase By setting the source 22 to 5V and applying -10V to the control gate electrode 26, the electrons injected into the floating gate electrode 24 flow to the source 22 through the tunnel insulating film and erase is performed. Is returned to the initial state.

(D) Other memory cells By not applying a voltage to the control gate electrode 26, even if a memory cell in which 12.0 V is applied to the select gate electrode 30 is selected, the floating gate electrode 2
The memory state of 4 does not change.

(E) 3V is applied to the read selection gate electrode 30 to select this memory cell, 1.5V is applied to the drain 28, and the source 2 is applied.
2 is 0V. The control gate electrode 26 is set to 0V. If the programming “0” state in which electrons are injected into the floating gate electrode 24, this memory transistor is not turned on because the threshold voltage is positive. On the other hand, in the programming "1" state in which electrons are not injected into the floating gate electrode 24, the memory transistor is turned on because the threshold voltage thereof is negative.

Next, EPROM or EEPROM,
Alternatively, a circuit including a mask ROM will be described. FIG.
1 is an example of a conventional circuit in the case where a memory cell (enclosed by a broken line) includes one conventional memory transistor 1 shown in FIG. The word line 44 is connected to the control gate electrode of the memory transistor 1 from the X decoder 40 through the word line driver 42.
The memory transistor 1 is connected to the sense amplifier 48 via the Y gate 46. This memory transistor 1 has a positive threshold voltage even in the initial state, and the threshold voltage is further increased when written, so that 5 V is applied to the word line when reading and 0 V when not reading.

FIG. 5 shows an example of a circuit in which the memory cell of FIG. 2A of the present invention is connected in a NOR configuration. The memory cell 50 includes a memory transistor 52 and a selection gate transistor 54.
Has a negative threshold voltage in the initial state "1" and is "0"
Is written, the threshold voltage changes to positive. 0V is applied to the control gate electrode of the memory transistor 52 during reading and non-reading. The word line 44 is connected to the select gate transistor 54 via the X decoder 40 and the word line driver 42 of CMOS structure, and the memory cell 50 is selected. The memory cell 50 is connected to the sense amplifier 48 having the CMOS structure via the Y gate 46 as in the conventional case.

6 and 7 show examples of preferable circuits in which the circuit of FIG. 5 is further reduced in power consumption. 6 and 7 are for preventing the flow of a through current in the CMOS circuit by prohibiting the driving of the sense amplifier at the time of switching the address signal. FIG. 6 is a schematic block diagram showing that address signals are transmitted from the address circuit 60 to the decoder 62.
After that, a predetermined word line is selected by the word line buffer 64. The memory cell of the selected word line is read by the sense amplifier 48 and output from the output circuit 66. ATD (Address Transition Detector) circuit 6
Reference numeral 8 is for detecting a change in the address signal from the output of the address circuit 60 and generating a pulse signal corresponding to the time during which the address signal is changing. The pulse signal is supplied to the word line buffer 64 and the sense amplifier 48. Is
While the address signal is changing, word line selection and sense amplifier driving are prohibited so that no current flows in the CMOS circuit during the transient period.

FIG. 7 shows a specific example thereof. The same parts as those in FIG. 5 are designated by the same reference numerals. In order to prohibit the operation of the CMOS inverter 42 of the word line driver that drives the word line 44 from the X decoder 40 while the address signal is changing, the CMOS inverter 42 is used.
The PMOS transistor 70 is inserted between the PMOS transistor and the power supply terminal, the output terminal of the CMOS inverter 42 is connected to the ground terminal through the NMOS transistor 72, and the gate electrodes of the MOS transistors 70 and 72 are connected to the ATD circuit. The pulse signal from 68 is applied. Further, in order to prohibit the operation of the sense amplifier while the address signal is changing, the input terminal and the output terminal of the CMOS inverter of the sense amplifier 48 are connected to the power supply voltage Vcc via the PMOS transistors 74 and 76, respectively. NMO of the CMOS inverter
An NMOS transistor 78 is inserted between the S transistor and the ground terminal, and these MOS transistors 7
The pulse signals from the ATD circuit 68 are inverted and applied to the gate electrodes of 4, 76 and 78. In this way, by prohibiting the driving of the word line and prohibiting the operation of the sense amplifier at the time of switching the address signal, it is possible to prevent a transient through current from flowing through the CMOS inverter that constitutes the word line driver and the sense amplifier. Prevents and reduces power consumption.

Although the above-described embodiments show an example in which the memory cell includes two MOS transistors of a memory transistor and a select gate transistor, the embodiment of FIG. 8 shown below has one memory cell 52a. 2 shows an embodiment including only the memory transistor 52 of FIG. This memory transistor 52 is the one shown in FIG. 2A. The channel region of the memory transistor 52 is ion-implanted so that the threshold voltage is changed to negative in the initial state, for example, -1.0 V, and becomes positive by writing. Is set to. The word line 46 connected to the control gate electrode of the memory transistor 52 is driven by the X decoder 40 and the word line driver 42a. When the word line 46 is selected, 0V or a slightly positive voltage is applied to the word line, When not selected, a negative voltage lower than the threshold voltage of the memory transistor 52 in the initial state, for example, -2.0V.
Is applied to the word line driver 42a, a negative voltage generating circuit 80 is connected.

As a result, when 0V or a slightly positive voltage is applied to the word line to select the memory transistor 52, when "0" is written in the memory transistor 52, the memory transistor 52 does not turn on, It turns on when "1" is written. When -2.0 V is applied to the word line and the memory transistor 52 is in the non-selected state, the written state is "0", "
It is not turned on by any of 1 ". By thus setting the voltage of the control gate electrode of the memory transistor 52 in the non-selected state to a negative voltage lower than the threshold voltage in the initial state, It is possible to realize a circuit in which the sense amplifier does not malfunction even when the memory cell is composed of only one memory transistor having a negative threshold voltage in the initial state.

In order to reduce the power consumption of the circuit of FIG. 8 as well, the driving of the word line is prohibited and the operation of the sense amplifier is prohibited during the switching of the address signal as in the case of FIGS. It is preferable to prevent a transient through-current from flowing through.

[0029]

According to the present invention, as the memory transistor,
A memory transistor whose threshold voltage is set to be negative in one memory state and positive in the other memory state is used. As a result, the memory transistor can be read even if the control gate voltage or the gate voltage is 0V, and it is not necessary to apply a high voltage such as 5V as in the conventional case, and low voltage operation becomes possible. Negative voltage is supplied to the word line drive circuit connected to the gate electrode of the memory transistor whose threshold voltage is negative in one memory state so that the memory transistor in one memory state does not turn on when the memory cell is not selected. By providing the voltage generation circuit, it becomes possible to configure a memory cell with only one memory transistor capable of low voltage operation. The word line drive circuit and the sense amplifier have a CMOS configuration, the point of time when the address signal is switched is detected, and the drive of the word line and the operation of the sense amplifier are prohibited during the switching period to prevent a shoot-through current in the CMOS circuit. Thus, low power consumption can be realized. The potential applied to the control gate electrode and the gate electrode of the memory transistor at the time of reading in the FAMOS memory cell and the mask ROM memory cell is common, for example, 0 V, so that both are performing the low voltage operation and are the same as the FAMOS memory cell. It is possible to realize a mask ROM having the above timing characteristics, and it is not necessary to redesign the timing between the two as in the conventional case, and the period required for the design is shortened.

[Brief description of drawings]

FIG. 1 is a plan view showing a conventional memory cell, (A)
Is a FAMOS memory transistor having a positive threshold voltage in the initial state, and (B) is an EEPR having a NAND structure in which the threshold voltage of the memory transistor is negative in the initial state.
It is an OM cell array.

FIG. 2 shows an embodiment of the present invention, in which (A) is a FAMOS memory cell having a negative threshold voltage in the initial state,
Similarly, (B) is a mask R with a negative threshold voltage in the initial state.
OM memory cell.

FIG. 3 is a diagram showing an operation of the memory cell in FIG.

FIG. 4 is a circuit diagram showing a memory device using conventional memory cells.

FIG. 5 is a circuit diagram showing a memory device having a NAND structure using the memory cells of one embodiment.

FIG. 6 is a block diagram of a preferred memory device.

FIG. 7 is a circuit diagram showing a specific example of FIG.

FIG. 8 is a circuit diagram showing an embodiment of one memory cell and one memory transistor configuration.

[Explanation of symbols]

 20, 22, 28 Diffusion region 24 Floating gate electrode 26 Control gate electrode 30 Select gate electrode 32 Mask ROM gate electrode 50, 50a Memory cell 52 Memory transistor 54 Select gate transistor 48 Sense amplifier 68 ATD circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (5)

[Claims] 1. A floating gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film, and a control gate electrode is further formed thereon via an insulating film, and a threshold measured from the control gate electrode. From the memory transistor whose threshold voltage is set so that the value voltage is negative in one memory state and positive in the other memory state, and the select gate transistor inserted between this memory transistor and the sense amplifier. Become 2
A non-volatile semiconductor memory device comprising: a memory cell including a plurality of MOS transistors, the memory cell being connected to a sense amplifier so as to form a NOR circuit. 2. A gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film, and the threshold voltage is set to be negative in one memory state and positive in the other memory state. A memory cell including two MOS transistors including a set memory transistor and a selection gate transistor inserted between the memory transistor and the sense amplifier is provided, and the memory cell constitutes a NOR circuit. A non-volatile semiconductor memory device, characterized in that it is connected to a sense amplifier. 3. In a memory cell, a floating gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film, and a control gate electrode is further formed on the floating gate electrode via an insulating film, and a control gate electrode. The memory transistor whose threshold voltage is set so that the threshold voltage measured from is negative in one memory state and positive in the other memory state, or through the gate insulating film on the channel region of the semiconductor substrate. A gate electrode is formed,
A word line drive connected to a control gate electrode or a gate electrode of a memory cell that includes only memory transistors whose threshold voltage is set so that the threshold voltage is negative in one memory state and positive in the other memory state A non-volatile semiconductor memory device characterized in that the circuit is provided with a negative voltage generating circuit for supplying a negative voltage that does not turn on a memory transistor in one of the memory states when a memory cell is not selected. 4. The word line drive circuit has a CMOS structure,
Equipped with an address switching detection circuit that detects the switching time of the address signal and generates a pulse signal corresponding to that switching time, and disables the operation of the sense amplifier while the output pulse signal of the address switching detection circuit is generated. 4. The non-volatile semiconductor memory device according to claim 1, comprising a clock operation type drive circuit. 5. A sense amplifier having a CMOS structure, comprising an address switching detection circuit for detecting a switching time point of an address signal and generating a pulse signal corresponding to the switching time point, and an output pulse signal of the address switching detection circuit is generated. 4. The non-volatile semiconductor memory device according to claim 1, further comprising a clock operation type drive circuit for prohibiting the operation of the sense amplifier during the period of operation.