JPH0822414A - Computer system - Google Patents

Abstract

PURPOSE:To prevent the information processing rate from decreasing accompanying alterations of system constitution such as variation in the number of mounted processors by controlling a snooping processing according to the number of mounted processors. CONSTITUTION:The computer system is provided with a quantity discriminating circuit 104 which grasps the number of mounted processors 101 and 108 and a snooping processing control circuit 105 controls a signal inquiring data for the snooping processing according to the number of mounted processors. Namely, the computer system wherein >=2 processors 101 and 108 operate send inquiry signals for data in cache memories 103 and 110 between the processors to the respective processors 101 and 108, and allows the snooping processing for guaranteeing the conformity of data. When only one processor 101 operates in the system, the snooping processing for data to the other cache memory 108 is not performed. Consequently, the system can be placed in high-speed operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system, and more particularly to a technique effectively applied to snoop processing between processors in a computer system capable of operating both a uniprocessor and a multiprocessor.

[0002]

2. Description of the Related Art In a multiprocessor system computer in which each processor (CPU) has a cache memory and a shared memory is provided on a host bus, snoop processing must be performed in order to make the data in the cache memory the same.

In a system in which a cache control system is a write-through system (a system in which data written in a shared memory from a processor is directly written in the shared memory without being stored in the cache memory), a CPU stores data in a certain block. When writing, if another cache has the same block, the block of the other cache must be invalidated in order to unify the data. Therefore, a signal is transmitted to the other cache to inform that the data in the block will be rewritten. Further, in the case of the operation of reading data from a certain block of the CPU, if the block does not exist in the own cache memory, the data of the block of the other cache memory and the data of the block of the shared memory are the same. Therefore, the CPU only needs to read the data from the shared memory and does not need to inquire of the other caches for the data. Therefore, the snoop process is not necessary to read the data.

Next, in a system in which the cache control system uses a write-back control system (a system in which data to be written from the processor to the shared memory is temporarily stored in the cache memory and then written to the shared memory),
When writing data to a certain block, if another cache memory has the same block, the other cache memory block is invalidated. When the CPU reads data from a block, if the block exists in another cache memory and the block is the latest data, the write-back operation is performed. Then, after the above operation is completed, the data is read from the shared memory. If the same block does not exist in the other cache memory, the CPU reads the data from the shared memory.

On the other hand, in the case of the uniprocessor system, the above-mentioned snoop processing is not necessary because there is no other cache memory, and only one CPU can immediately access its own cache memory or shared memory.

[0006]

From the above, the snoop processing required in the multiprocessor system is unnecessary in the uniprocessor system, and when the multiprocessor computer system is operated as it is in the uniprocessor, it is redundant. This causes a problem that the operation is slower than that of a normal uniprocessor computer system by the amount of such snoop processing.

The snoop processing of the conventional multiprocessor system is described in, for example, Japanese Patent Laid-Open No. 4-328.
The technique disclosed in Japanese Patent No. 653 is known. In other words, in this technology, addresses / bus-snoop-required addresses /
The shared bus connection is used for the command bus, and the multiple data buses connected by the interconnection network are used for the data bus that does not require bus snooping, thereby eliminating the bus neck in the shared bus connection. A technique to be attempted is disclosed. However, this conventional technique does not consider the above-mentioned performance degradation when the microprocessor system is used with a single processor mounted.

An object of the present invention is to control snoop processing in accordance with the number of installed processors, thereby preventing a decrease in information processing speed due to a change in system configuration such as the number of installed processors. To provide.

[0009]

In the computer system of the present invention, a number identifying circuit for grasping the number of installed processors is provided, and the snoop processing control circuit performs a snoop processing according to the installed number of processors. Controls data interrogation signals. In other words, the processor is 2
In a computer system operating with more than one processor, a snoop process for guaranteeing data consistency is permitted by sending a data inquiry signal to the cache memory between the processors to each processor. Further, in the case of a system in which only one processor is operating, snoop processing of data to another cache memory is not performed.

[0010]

By providing the number discriminating circuit in this way, the number of processors operating the computer can be grasped, and when one processor is operating, it is executed by the snoop processing control circuit. By suppressing the data inquiry process to the redundant cache memory, the system can be operated at high speed.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

1 and 2 are block diagrams showing an example of the configuration of a computer system according to an embodiment of the present invention. Although the computer system of this embodiment is configured as a multiprocessor system capable of mounting a plurality of processors, it can also be operated as a uniprocessor system having a single processor.

That is, FIG. 1 shows a case where the computer system of this embodiment is operated as a multiprocessor system, and FIG. 2 shows a case where it is operated as a uniprocessor system.

In the case of a multiprocessor system, a common processor bus 113, as illustrated in FIG.
A plurality of CPU units 201 (CU) and CPU units 202 (CU) ,. ． ． Is connected. Also,
The processor bus 113 has a shared memory 107 and a memory controller 10 for controlling the shared memory 107.
6 (MC) are connected to the CPU units 201 and 202 ,. ． ． Commonly accessed from.

Each CPU unit 201 (20
2 ,. ． ． ), The processor 101 (10
8 ,. ． ． ) (CPU) and the processor 101 (1
08 ,. ． ． ) Shared memory 10 accessed by
A cache memory 10 for temporarily holding the data in 7
3 (110, ...) (CM) and the cache controller 102 (109, ...) (CAC) that controls the operations of the cache memory 103 (110, ...) (CM).
Is provided.

Each CPU unit 201 (20
2 ,. ． ． ) Cache controller 102 (10
9 ,. ． ． ) Is connected to the snoop processing control circuit 105 and is connected to the individual cache memories 103 and 11
0 ,. ． ． Snoop processing as described later is performed to guarantee uniqueness between data transiently held in each of the above.

In this case, the snoop processing control circuit 105 is connected with a number identification circuit 104 for identifying the number of CPU units mounted on the processor bus 113, that is, the number of mounted processors. 104 is configured to transmit to the snoop processing control circuit 105 whether the number of processors implemented by the control signal 115 is single or plural. Although not particularly shown, the number identifying circuit 104 can be configured by, for example, a memory switch controlled by software or the like, a dip switch operated from the outside, or the like. Further, the snoop processing control circuit 105 is provided with control logic for selecting execution or execution suppression of the snoop processing based on the control signal 115.

An example of the operation of the computer system of this embodiment will be described below.

First, the case of the multiprocessor system illustrated in FIG. 1 will be described. When the processor 101 accesses data of a block in the shared memory 107, if the block does not exist in the cache memory 103, the cache controller 102 causes the snoop processing control circuit 105 to control the control signal 116 for accessing the shared memory 107. To send. The number identifying circuit 104 for identifying the number of processors notifies the snoop processing control circuit 105 that the number of processors is plural by setting the control signal 115 to "Hi". After that, the snoop processing control circuit 105, which receives the control signal 116 and the control signal 115, causes the other cache controller 109
A control signal 117 for inquiring whether or not the same block is present is transmitted to etc. If the same block exists in the cache controller 109 or the like, the cache controller 109 or the like flushes the data in the cache memory 110 or the like to the shared memory 107, or invalidates the block in the cache memory 110 or the like. After the above processing is completed, the snoop processing control circuit 105 transmits to the cache controller 102 that the data of a certain block existing in the shared memory 107 can be accessed. As a result, the cache controller 102 can access the shared memory 107, and the processor 101 can access data of a certain block in the shared memory 107.

On the other hand, the operation of the uniprocessor system shown in FIG. 2 will be described. In the case of FIG. 2, the system is configured using one processor, and when the processor 101 accesses data in a certain block, if the target block does not exist in the cache memory 103, the cache controller 102 snoops. A control signal 116 for accessing the shared memory 107 is transmitted to the processing control circuit 105. Also, the number identification circuit 10
4 transmits the fact that there is one processor to the snoop processing control circuit 105 by setting the control signal 115 to "Low". After that, the snoop processing control circuit 105 which receives the control signal 116 and the control signal 115 immediately transmits that the data of the target block of the shared memory 107 can be accessed because the other cache does not exist, and the cache controller 102 sends the shared memory. The access to 107 is started, and the processor 101 sets the shared memory 10
You can access the data in a block in 7.

Hereinafter, when the processor 101 accesses the data of a certain block, the operations of the number identification circuit 104 and the snoop processing control circuit 105 will be described with reference to the difference in the cache control method between FIG. 3, FIG. 4, FIG. 5, FIG. , FIG. 9, FIG. 9, and FIG.

First, the writing of data from the processor side to the shared memory 107 in the case where the cache control system is a write-through system and is operating in a multiprocessor system will be described.

In this case, the cache controller 102
When writing data to a certain block of the shared memory 107 at a certain time point, the cache controller 102 sends a control signal 116 indicating that the writing of data to the shared memory 107 is started, as shown in FIG.
It transmits to 05 (process 701). Also, the number identification circuit 1
Reference numeral 04 indicates that the number of processors is plural by setting the control signal 115 to the "Hi" level (process 70).
2).

After receiving the control signal 116 and the control signal 115, the snoop process control circuit 105 selects whether to perform the snoop process (process 703). Since the control signal 115 is "Hi" (multiprocessor configuration) as shown in FIG. 4, the snoop processing control circuit 105 inquires of other cache controllers 109, 111, etc. whether the same block exists. The control signal 117 is transmitted (process 704). The cache controller 10 that has received the control signal 117
9. In response to the inquiry, the cache controller 111 uses the control signal 118 to determine whether the same block exists or not, as shown in FIG.
It responds to 05 (process 705).

If there is the same block, the same block in the other cache memories 110 and 112 is invalidated (process 706). Then, the cache controller 109, the cache controller 111, and the like notify the snoop processing control circuit 10 that the snoop is completed.
5 (process 707). On the other hand, if the same block does not exist in the cache memory 110, the cache memory 112, etc., the snoop processing is notified to the snoop processing control circuit 105, and the snoop processing is ended (processing 707).

After the processing 707 is performed, the snoop processing control circuit 105 informs the cache controller 102 that the snoop processing is completed as shown in FIG.
Control signal 1 transmitted at 19 and instructing to start writing data to the memory controller 106 and the shared memory 107
Send 20. The cache controller 102 that has received the control signal 119 writes data to a certain block in the cache memory 103 and the shared memory 107 (process 708).

On the other hand, when the cache control system is the write-through system and is operating in the uniprocessor system, the writing process from the processor side to the shared memory 107 is as follows. The cache controller 102 is
A control signal 116 indicating that data writing is started is transmitted to the snoop process control circuit 105 (process 701). Further, the number identification circuit 104 notifies the control signal 115 that the number of processors is one. At this time, the control signal 115 is set to the "Low" level (process 702). The snoop processing control circuit 105 which receives the control signal 116 and the control signal 115 selects whether to perform snoop processing (processing 7).
03). Since the control signal 115 is “Low”,
The snoop processing control circuit 105 determines that it is not necessary to transmit the control signal for inquiry to another cache memory, and the snoop processing control circuit 105 sends the control signal 116 from the cache controller 102 to the memory controller 106 and the shared memory 107. Directly transmitted, the cache controller 102 writes data to a certain block in the cache memory 103 and the shared memory 107 (process 708).

When the cache control system is the write-through system, the process of reading data from the shared memory 107 by the cache controller 102 is the same in both the multiprocessor system and the uniprocessor system. This is shown in FIG. The cache controller 102 sends a control signal 116 to start reading data to the snoop processing control circuit 105 (processing 801). The snoop processing control circuit 105 which has received the control signal 116, the other cache memory 110,
Since the data in the block in the cache memory 112 and the like is the same as the data in the block in the shared memory 107 (since the data in the cache memory does not change by writing), the same block exists in the cache controller 109, the cache controller 111, and the like. Do not ask. Therefore, the snoop processing control circuit 10
5 is a control signal 11 from the cache controller 102
6 is directly transmitted to the memory controller 106 and the shared memory 107, and the cache controller 102 reads data from a block in the cache memory 103 and the shared memory 107 (process 802).

Next, the case where the cache control system is the write-back system and the multiprocessor is operating will be described with reference to the flowchart of FIG.

In this case, the cache controller 102
When writing data to a certain block of a certain shared memory 107, the cache controller 102 sends a control signal 116 to the snoop processing control circuit 105 to start writing data to the shared memory 107 as shown in FIG. 3 (process 901). ). At this time, the number identification circuit 104 informs that the number of processors is plural by setting the control signal 115 to the "Hi" level (process 902). After receiving the control signal 116 and the control signal 115, the snoop process control circuit 105 selects whether to perform the snoop process (process 903). Since the control signal 115 is "Hi" as shown in FIG. 4, the snoop processing control circuit 105 judges that the snoop processing is necessary,
The control signal 117 for inquiring whether or not the same block exists is transmitted to the other cache controller 109, the cache controller 111, etc. (process 904).

Upon receipt of the control signal 117, the cache controller 109 and the cache controller 111 respond to the inquiry to the snoop processing control circuit 105 by using the control signal 118 as shown in FIG. 5 as to whether or not the same block exists. (Process 905). The cache controller 109 and the cache controller 111 confirm whether or not the same block exists in the cache memory 110, the cache memory 112, etc., and that block holds the latest data (process 90).
6). If the latest data is held in the cache memory 110 as shown in FIG. 5, the cache controller 109 transfers the cache memory 11 to the shared memory 107.
The latest data of a block within 0 is swept out (process 907). If the same block exists in the other cache memories 110 and 112 but is not the latest data, the same block in the cache memory 110, cache memory 112, etc. is invalidated (process 90).
8).

Then, the cache controller 109,
The cache controller 111 or the like notifies the snoop processing control circuit 105 that the snoop is completed (processing 90).
9). On the other hand, the same block is the cache memory 110,
If it does not exist in the cache memory 112 or the like, the snoop processing control circuit 105 is notified that the snoop processing is completed, and the snoop processing is completed (processing 909).

After the processing 909 is performed, the snoop processing control circuit 105 informs the cache controller 102 that the snoop processing is completed as shown in FIG.
Control signal 1 transmitted at 19 and instructing to start writing data to the memory controller 106 and the shared memory 107
Send 20. The cache controller 102 that has received the control signal 119 writes data to a certain block in the cache memory 103 and the shared memory 107 (process 910).

On the other hand, a case where the cache control system is the write-back system and the uniprocessor system is operating will be described.

In this case, the cache controller 102
Is a control signal 1 which tells that when writing data to a block of the shared memory 107, the data writing is started.
16 is transmitted to the snoop processing control circuit 105 (processing 9).
01). At this time, the number identifying circuit 104 informs that the number of processors is one by setting the control signal 115 to the "Low" level (process 902). The snoop processing control circuit 105 which receives the control signal 116 and the control signal 115 selects whether to perform the snoop processing (processing 90).
3).

Since the control signal 115 is "Low", the snoop processing control circuit 105 does not need to send an inquiry control signal to another cache memory. Therefore, the snoop processing control circuit 105 directly transmits the control signal 116 from the cache controller 102 to the memory controller 106 and the shared memory 107, and the cache controller 102 writes the data to a certain block in the cache memory 103 and the shared memory 107 (processing 910).

The data read process from the shared memory 107 to the processor side in the case where the cache control system is the write-back system and the multi-processor is operating will be described with reference to the flowchart of FIG. It looks like this:

In this case, the cache controller 102
When reading data into a certain block of a certain shared memory 107, the cache controller 102 transmits a control signal 116 to the snoop processing control circuit 105 to start reading data to the shared memory 107 as shown in FIG. ). At this time, the number identification circuit 1
04 notifies that the number of processors is plural by setting the control signal 115 to the “Hi” level (Processing 1
2). The snoop processing control circuit 105 receives the control signal 116.
After receiving the control signal 115 and the control signal 115, it is selected whether to perform the snoop process (process 13).

Since the control signal 115 is "Hi" as shown in FIG. 4, the snoop processing control circuit 105
The control signal 117 for inquiring whether or not the same block exists is transmitted to the other cache controller 109, the cache controller 111, etc. (process 14). The cache controller 10 that has received the control signal 117
9. In response to the inquiry, the cache controller 111 uses the control signal 118 to determine whether the same block exists or not, as shown in FIG.
It responds to 05 (process 15). Then, the cache controller 109 and the cache controller 111 confirm whether or not the same block exists in the cache memory 110, the cache memory 112, etc., and that block holds the latest data (process 16).

As shown in FIG. 5, the cache memory 110
If the latest data is stored in the cache memory 109, the cache controller 109 causes the shared memory 107 to flush the latest data of a block in the cache memory 110 (process 17). If the same block exists in the other cache memory 110 or cache memory 112 but is not the latest data, it is considered that the same block exists in the shared memory 107, and the cache controller 109,
The cache controller 111 or the like notifies the snoop processing control circuit 105 that the snoop is completed (Process 1
9).

On the other hand, the same block is the cache memory 1
10. If it does not exist in the cache memory 112 or the like, the snoop processing is notified to the snoop processing control circuit 105 and the snoop processing is ended (processing 1).
9). After the processing 19 is performed, the snoop processing control circuit 1
As shown in FIG. 6, 05 sends a control signal 119 to the cache controller 102 that the snoop process is completed, and sends a control signal 120 to the memory controller 106 and the shared memory 107 to start reading the data. Upon receiving the control signal 119, the cache controller 102 reads data from a block in the shared memory 107 (process 20).

On the other hand, when the cache control system is the write-back system and the uniprocessor system is operating, the process of reading data from the shared memory 107 is as follows.

The cache controller 102 transmits a control signal 116 to the snoop processing control circuit 105 to start reading data (processing 11). Further, the number identification circuit 104 notifies the control signal 115 that the number of processors is one.

At this time, the control signal 115 is set to the "Low" level (process 12). Control signal 116 and control signal 115
The snoop process control circuit 105 which has received the command selects whether to perform the snoop process (process 13). And the control signal 11
Since 5 is “Low”, the snoop processing control circuit 105
Need not send control signals for inquiries to other cache memories. Therefore, the snoop processing control circuit 10
5 is a control signal 11 from the cache controller 102
6 is directly transmitted to the memory controller 106 and the shared memory 107, and the cache controller 102 reads data from a block in the cache memory 103 and the shared memory 107 (process 20).

As described above, according to the computer system of this embodiment, in the case of the multiprocessor configuration, it is possible to ensure the uniqueness of data among a plurality of cache memories and to implement a single processor. In the uniprocessor configuration, since the time-consuming and redundant snoop processing is suppressed, it is possible to minimize the efficiency decrease due to the system configuration change and improve the performance.

For example, when designing a multiprocessor system in a relatively small-scale microprocessor-based computer system, the multiprocessor system is originally designed as a multiprocessor system in order to diversify and differentiate the product lineup (price range, performance). Even if the designed one is commercialized as a uniprocessor system, it is possible to improve the performance by minimizing the efficiency decrease caused by the redundant processing such as snoop processing.

In the above description, the case where the cache controller and the snoop processing control circuit are separately provided has been described. However, the cache controller is configured to include various functions of the snoop processing control circuit, and is specified when the system is started. The cache controller may be used as a master and another slave may be used as a slave so that the master cache controller has the function of the snoop processing control circuit.

[0048]

According to the computer system of the present invention, in a computer system capable of realizing both a multiprocessor and a uniprocessor, the snoop processing is controlled in accordance with the number of processors installed, so that the number of processors installed, etc. The effect that the performance improvement can be realized by preventing the reduction of the information processing speed due to the change of the system configuration is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram when a computer system according to an embodiment of the present invention is operated as a multiprocessor system.

FIG. 2 is a block diagram when a computer system according to an embodiment of the present invention is operated as a uniprocessor system.

FIG. 3 is a block diagram showing an example of signal transmission / reception between a cache controller and a snoop processing control circuit in a computer system according to an embodiment of the present invention.

FIG. 4 is a block diagram showing an example of signal transmission / reception between a cache controller and a snoop processing control circuit in a computer system according to an embodiment of the present invention.

FIG. 5 is a block diagram showing an example of snoop processing of a cache controller in a computer system that is an embodiment of the present invention.

FIG. 6 is a block diagram showing an example of access to the shared memory after completion of snoop processing of the cache controller in the computer system according to the embodiment of the present invention.

FIG. 7 is a flowchart showing an example of a write operation to the shared memory in the write-through method of the cache controller in the computer system which is an embodiment of the present invention.

FIG. 8 is a flowchart showing an example of a read operation from the shared memory in the write-through method of the cache controller in the computer system according to the exemplary embodiment of the present invention.

FIG. 9 is a flowchart showing an example of a write operation to the shared memory in the write-back method of the cache controller in the computer system which is an embodiment of the present invention.

FIG. 10 is a flowchart showing an example of a read operation from the shared memory in the write-back method of the cache controller in the computer system which is an embodiment of the present invention.

[Explanation of symbols]

101 ... Processor, 102 ... Cache controller, 103 ... Cache memory, 104 ... Number identification circuit, 105 ... Snoop processing control circuit, 106 ... Memory controller, 107 ... Shared memory, 109 ... Cache controller, 110 ... Cache memory, 111 ... Cache Controller, 112 ... Cache memory, 1
13 ... Processor bus, 115-120 ... Control signal, 2
01, 202 ... CPU unit.

Claims (1)

[Claims] 1. One or more processors,
A shared memory accessed by the processor,
A cache memory that is provided in each of the processors and that temporarily holds at least one of data written from the processor to the shared memory and data read from the shared memory to the processor; and the cache memory A snoop processing control circuit for performing snoop processing for guaranteeing uniqueness of the data between the cache memories;
A number identifying circuit that identifies the number of mounted processors and transmits the number to the snoop processing control circuit, wherein the snoop processing control circuit performs the snoop processing when the number of mounted processors is plural, and the processor A computer system having a control logic for suppressing the snoop processing when the number of the devices is single.